)]}'
{
  "commit": "224e6ad727c6ef3ea737b094987e64d1fea61bf8",
  "tree": "6ae304c7f0626f370d5194989ae534c8af6777d0",
  "parents": [
    "fab5f032d44174fa748b9cf91f089f05c9600f20"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Fri Jun 03 14:16:23 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Fri Jun 03 14:16:23 2022 +0100"
  },
  "message": "Fixed valid time ranges in PWM test. Also added message saying valid range if the timing test fails.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6c06022d3f85c525bd8e11f9f2ba25a45c431f36",
      "old_mode": 33188,
      "old_path": "verilog/dv/peripheralsPWM/peripheralsPWM_tb.v",
      "new_id": "b2b5b5ab972cf587939e323f3dfc1360264eb18b",
      "new_mode": 33188,
      "new_path": "verilog/dv/peripheralsPWM/peripheralsPWM_tb.v"
    },
    {
      "type": "modify",
      "old_id": "e8029d5ee4b29de702d82e2e04629156cc20fcd6",
      "old_mode": 33188,
      "old_path": "verilog/dv/video/video_tb.v",
      "new_id": "aa1c6f22382f50641a03386460b2bc8413ddd794",
      "new_mode": 33188,
      "new_path": "verilog/dv/video/video_tb.v"
    }
  ]
}