)]}'
{
  "commit": "049d4be60f10b7c608a6dbf59230620c774aa8fd",
  "tree": "77b505f179bdbdaf9e23e1cb34bd32dbe3c1ff2c",
  "parents": [
    "4dfa7912db0fd9c483ea31d0d0a4f8951112db25"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sat May 21 23:41:59 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sat May 21 23:41:59 2022 +0100"
  },
  "message": "Fixed UART test not checking for the correct status bit. Also added some extra checks to make sure data leaves the FIFO buffers correctly.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c96a07a3281a644cd0c88b6c835938a1491f1455",
      "old_mode": 33188,
      "old_path": "verilog/dv/peripheralsUART/peripheralsUART.c",
      "new_id": "d4f1c00656ae68a7a122b004f95d4f7980b2a992",
      "new_mode": 33188,
      "new_path": "verilog/dv/peripheralsUART/peripheralsUART.c"
    },
    {
      "type": "modify",
      "old_id": "0d5d2e9671eaac1a3cad3febe386983757db18cd",
      "old_mode": 33188,
      "old_path": "verilog/dv/peripheralsUART/peripheralsUART_tb.v",
      "new_id": "738b21e65c3fe1abfefe9f05eab37172e8eb829d",
      "new_mode": 33188,
      "new_path": "verilog/dv/peripheralsUART/peripheralsUART_tb.v"
    }
  ]
}