diff --git a/verilog/dv/FPU_Half/FPU_Half_tb.v b/verilog/dv/FPU_Half/FPU_Half_tb.v
index 8ee44b5..a1bf0f2 100644
--- a/verilog/dv/FPU_Half/FPU_Half_tb.v
+++ b/verilog/dv/FPU_Half/FPU_Half_tb.v
@@ -74,6 +74,7 @@
             wait(mprj_io_0 == 16'hC178);
             */
             // Observe Output pins [23:8] for Fsign and I2F
+            /*
             wait(mprj_io_0 == 16'h449A);
             wait(mprj_io_0 == 16'h3042);
             wait(mprj_io_0 == 16'h491E);
@@ -89,7 +90,41 @@
             wait(mprj_io_0 == 16'h7AE4);
             wait(mprj_io_0 == 16'h7208);
             wait(mprj_io_0 == 16'h7AE7);
-           
+            */
+            // Observe Output pins [23:8] for FClass and F2I
+            /*
+            wait(mprj_io_0 == 16'd5);
+            wait(mprj_io_0 == 16'd132);
+            wait(mprj_io_0 == 16'd0);
+            wait(mprj_io_0 == 16'd1);
+            wait(mprj_io_0 == 16'd10);
+            wait(mprj_io_0 == 16'd200);
+            wait(mprj_io_0 == 16'd210);
+            wait(mprj_io_0 == 16'd190);
+            wait(mprj_io_0 == 16'h0040);
+            wait(mprj_io_0 == 16'h0040);
+            wait(mprj_io_0 == 16'h0002);
+            wait(mprj_io_0 == 16'h0002);
+            */
+            // Observe Output pins [23:8] for Comparison and Min/Max
+            
+            wait(mprj_io_0 == 16'h0001);
+            wait(mprj_io_0 == 16'h0001);
+            wait(mprj_io_0 == 16'h0001);
+            wait(mprj_io_0 == 16'h0000);
+            wait(mprj_io_0 == 16'h0001);
+            wait(mprj_io_0 == 16'h0001);
+            wait(mprj_io_0 == 16'h0001);
+            wait(mprj_io_0 == 16'h0001);
+            wait(mprj_io_0 == 16'h449A);
+            wait(mprj_io_0 == 16'h3042);
+            wait(mprj_io_0 == 16'h491E);
+            wait(mprj_io_0 == 16'h59EE);
+            wait(mprj_io_0 == 16'hDC87);
+            wait(mprj_io_0 == 16'hB03E);
+            wait(mprj_io_0 == 16'hBCF0);
+            
+            
             $display("MPRJ-IO state = %h", mprj_io[23:8]);  
 		
 		`ifdef GL
diff --git a/verilog/rtl/FPU/FPU_FSM_TOP.v b/verilog/rtl/FPU/FPU_FSM_TOP.v
index 0e28e4f..b2f55b8 100644
--- a/verilog/rtl/FPU/FPU_FSM_TOP.v
+++ b/verilog/rtl/FPU/FPU_FSM_TOP.v
@@ -49,22 +49,23 @@
 `include "LZD_comb.v"
 */
 
-module FPU_FSM_TOP(vccd1,vssd1,r_Rx_Serial,clk,rst_l,FPU_hp_result);
+module FPU_FSM_TOP(
 
 `ifdef USE_POWER_PINS
-    inout vccd1;	// User area 1 1.8V supply
-    inout vssd1;	// User area 1 digital ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
 `endif
     // FPU UART
-    input r_Rx_Serial;
+    input r_Rx_Serial,
     // FPU UART
 
     // FPU FSM 
-    input clk,rst_l;
+    input clk,
+    input rst_l,
     
-    output [15:0] FPU_hp_result;
+    output [15:0] FPU_hp_result
     // FPU FSM 
-
+);
     wire o_Rx_DV;
     wire [7:0]o_Rx_Byte;
     wire Active_Process;