)]}'
{
  "commit": "f9e8e46adbafb740e7a96dfe372e12b6961ec9c7",
  "tree": "75e4af707efd3a148af8d975ef95033b3223929a",
  "parents": [
    "3ffe64c196bbf72aadf4fdd277ead4802906beea"
  ],
  "author": {
    "name": "hamzashabbir517",
    "email": "shabbirhamza517@gmail.com",
    "time": "Wed May 18 10:46:39 2022 +0500"
  },
  "committer": {
    "name": "hamzashabbir517",
    "email": "shabbirhamza517@gmail.com",
    "time": "Wed May 18 10:46:39 2022 +0500"
  },
  "message": "First RTL files are added\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8f7b702d8c0b15ee326ba7ba14c36c825edecaa6",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/Dec_gpr_ctl.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e6d01fcdeead9b15f3e07a3c823668f78c6b7679",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/Execution.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e83f1223b8cbe8707b03bbc4ca0aa3cc95c801f2",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_Add_Post_Normalization.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3ef15c41d3f2fd2630efab1a502b1267633f55e9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_Exponent_Matching.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "026c41d374195332574562992378112ffdf7c45b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_LZD_L0.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "edd026c91d14a1a796f89c5df398e91534b459af",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_LZD_L1.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "218dace6a177e1cf8e1dabb05a778551f4ff71b7",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_LZD_L2.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "b6a64890d8bdee5a632676efa76b42084dd01dd5",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_LZD_L3.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "816bd8e57163cc4d2f620bec4c3beab58fd9e5b2",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_LZD_L4.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8a52ce037d5e92aa3d832e1bd90cb6611dc61d6c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_LZD_main.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3a942617fd18006a05ce99517194cf307d898827",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "b8bf8e2a3476dd5848114230f0da66be28e48c38",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_Top_Single_Cycle.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "4990447e81e090f720bfde757e2b61c7701c499b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_exponent_addition.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3cd243a6d20559876fa9341119a04f14de72ea2b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_extender.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "6df4a66a02e30fb243bd715cff3a3624d6be30d0",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_mantissa_addition.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "39e745cd3c61b61b15e6c539a132496d84c9685a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_mantissa_generator.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "4c0c0e338938748c327bc3d799e4e00d8904ddc6",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_mantissa_multiplication.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "509e51ce7c2f5b6684011f8ced68d56da845964a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_rounding_block_Addition.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "26dfafa7b5daf8ccaf0c3bd045f8b9b1e3950d90",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "fd3fa859ddbed217a245b2dbfaf0554186acd327",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_CSR.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "d25afda4155086eaf750303c8db5740e1909bbad",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_F2I.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8bd5804aac362f1287b8b4d723f43b27d2888f1e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_FSM_Control_Decode.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "dd989dc4f72527bc242f5f540a653739df51df86",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_FSM_TOP.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "67120982b376e462cf29d8cb28c9575af624da8c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_Fclass.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "11523fb10f13b57fad5257e37141858e8a09068c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_Input_Validation.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "1b54a37429dcac28434ecedb93e979b048c7ce57",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_Top_Single_Cycle.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "fc7282238be890bf4de6ae9faadd93fffef1f160",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_comparison.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "bc0a59b9aec7ed3ec603b5955e00b6b29da15b9b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_dec_ctl.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "9b5d3c55bf9c977ecd9aec35cd28a0c32e009767",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_decode.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "86b150625e78c357a914dde56246073bca05169b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_exu.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "7b1c185d2dae3d453e9f79d131d72908b51e08e2",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_fpr_ctl.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "59320b678f6f26b314277467ee703e80b43c0218",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_move.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8110b5863a3b876274628de6d2731321218b1a1f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_sign_injection.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "52a81379fb34b7018524612967c048f280368694",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/I2F_main.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "dbe53233db804c3f99e988ec00a9a45f6edd4f83",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/LZD_comb.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "345c091eb535f069ce241c5f0e9a5d6362388690",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/LZD_layer0.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3cf47ce754a0d184a9d698286738fedb7cba08be",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/LZD_layer1.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "5cd2c08258f534e6ebfa93a2719e33bc16b6cd20",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/LZD_layer2.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "32bf5e503aa92ec18ef3b536fe321583abb1638e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/LZD_layer3.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "911ceac37a08835f43137e788adea14d6167bf9c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/LZD_layer4.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "574e976f279612880f0f6192894227949c0c5305",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/LZD_main.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "86737075aa8e53689fc2108223f24338df681cfb",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/LZD_mux.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "506280207472e34154f9fbb7be8975476cadccf9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/Main_Decode.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e4c4aa0037ed10990109e932496d3b658b67215a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/Sky130_SRAM_1kbyte_Memory.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "32a2894a9197f4d6ee01bdac2a138b29030cc1bd",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/beh_lib.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "611396f05d5ff7818ab2636c9adc4f6bd0ab79ab",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/iccm_controller.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "788c9a5d5f786d42f03503b87eab9e05ff25f324",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/inst_checker.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "7af503199d73e6c2cc27f166e31e257f50c6b22f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/uart_rx_prog.v"
    }
  ]
}