)]}'
{
  "commit": "ee8f304480aa80b5904b09811c0b4b3820cb2708",
  "tree": "6b05eda44ea1c96966aaa21a934330dc5e01d1d4",
  "parents": [
    "27a862353fb37911f3a96d61c187d690c46adb0a"
  ],
  "author": {
    "name": "hamzashabbir517",
    "email": "shabbirhamza517@gmail.com",
    "time": "Mon May 30 01:33:35 2022 +0500"
  },
  "committer": {
    "name": "hamzashabbir517",
    "email": "shabbirhamza517@gmail.com",
    "time": "Mon May 30 01:33:35 2022 +0500"
  },
  "message": "Finals Files\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "9b83be6f3be606510b2d99164bac46004883ccb2",
      "old_mode": 33188,
      "old_path": "verilog/rtl/FPU/FMADD_Add_Post_Normalization.v",
      "new_id": "ad35cd75609d2f2d5f099441efdf493d70caa0b3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_Add_Post_Normalization.v"
    },
    {
      "type": "modify",
      "old_id": "cc7e802d589c655b6bd383963447c31b8b1bd93c",
      "old_mode": 33188,
      "old_path": "verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v",
      "new_id": "c2398ab192bdb0949cfe5379caf37829752f0730",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v"
    },
    {
      "type": "modify",
      "old_id": "8e9a69f247d3507d6799bcc8b8806b045655979b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/FPU/FMADD_Top_Single_Cycle.v",
      "new_id": "6a89bee523d386d8f512bee85aa57a032c6e9d62",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_Top_Single_Cycle.v"
    },
    {
      "type": "modify",
      "old_id": "4990447e81e090f720bfde757e2b61c7701c499b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/FPU/FMADD_exponent_addition.v",
      "new_id": "1e64dcd44dbcbbf9f3606eaeb001268bfaf260f7",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_exponent_addition.v"
    },
    {
      "type": "modify",
      "old_id": "e330e875ee181f5ccf7065fafdbd4e1589d41dd4",
      "old_mode": 33188,
      "old_path": "verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v",
      "new_id": "400fc07fb18d558dca521a029e1ef2ec0a2d3637",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v"
    },
    {
      "type": "modify",
      "old_id": "e698e05d2a386bf3b4b8d9bf4759a85294c54c83",
      "old_mode": 33188,
      "old_path": "verilog/rtl/FPU/FPU_F2I.v",
      "new_id": "7fa09431728680522cf08f8668e16d9653d45a34",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_F2I.v"
    },
    {
      "type": "modify",
      "old_id": "08a577e043876383f216edac631c1870406ead94",
      "old_mode": 33188,
      "old_path": "verilog/rtl/FPU/FPU_Input_Validation.v",
      "new_id": "dced614b1ffe4d7c8ade5a08abf0414176bcdb3c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_Input_Validation.v"
    },
    {
      "type": "modify",
      "old_id": "17379a5c3b9c1bae1691d5ae22bd4c8bf67033f7",
      "old_mode": 33188,
      "old_path": "verilog/rtl/FPU/FPU_Top_Single_Cycle.v",
      "new_id": "445eeefbd3b0639aadcad7a63a3c8ad3c9ef6c9d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_Top_Single_Cycle.v"
    },
    {
      "type": "modify",
      "old_id": "479cfdfefc750a3281b5b0e1fb78a7d162cc5c17",
      "old_mode": 33188,
      "old_path": "verilog/rtl/FPU/FPU_exu.v",
      "new_id": "e84c91cbb4b8d742a468d45243049ce5b9fde420",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_exu.v"
    },
    {
      "type": "modify",
      "old_id": "59320b678f6f26b314277467ee703e80b43c0218",
      "old_mode": 33188,
      "old_path": "verilog/rtl/FPU/FPU_move.v",
      "new_id": "51c3d776dcd49fb73cdb09c796c6bd67da0c5c16",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_move.v"
    },
    {
      "type": "modify",
      "old_id": "8110b5863a3b876274628de6d2731321218b1a1f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/FPU/FPU_sign_injection.v",
      "new_id": "9120f1c4c4bd4d457cb841492799481b0be1c80b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/FPU/FPU_sign_injection.v"
    }
  ]
}