diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index ad7cc28..d369405 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -34,6 +34,7 @@
  *
  *-------------------------------------------------------------
  */
+`define MPRJ_IO_PADS 38
 
 module user_proj_example #(
     parameter BITS = 32