# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
-v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/beh_lib.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/Dec_gpr_ctl.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/Execution.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_Add_Post_Normalization.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_exponent_addition.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_Exponent_Matching.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_extender.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_LZD_L0.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_LZD_L1.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_LZD_L2.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_LZD_L3.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_LZD_L4.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_LZD_main.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_mantissa_addition.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_mantissa_generator.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_mantissa_multiplication.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_Mul_Post_Normalization.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_rounding_block_Addition.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_rounding_block_Multiplication.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_Top_Single_Cycle.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_comparison.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_CSR.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_dec_ctl.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_decode.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_exu.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_F2I.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_Fclass.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_fpr_ctl.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_FSM_Control_Decode.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_FSM_TOP.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_Input_Validation.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_move.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_sign_injection.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_Top_Single_Cycle.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/I2F_main.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/iccm_controller.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/inst_checker.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_comb.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_layer0.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_layer1.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_layer2.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_layer3.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_layer4.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_main.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_mux.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/Main_Decode.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/uart_rx_prog.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU/Sky130_SRAM_1kbyte_Memory.v