diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 31ab09b..d18202d 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,5 +1,53 @@
 # Caravel user project includes
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
 -v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/beh_lib.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/Dec_gpr_ctl.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/Execution.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_Add_Post_Normalization.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_exponent_addition.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_Exponent_Matching.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_extender.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_LZD_L0.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_LZD_L1.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_LZD_L2.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_LZD_L3.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_LZD_L4.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_LZD_main.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_mantissa_addition.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_mantissa_generator.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_mantissa_multiplication.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_Mul_Post_Normalization.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_rounding_block_Addition.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_rounding_block_Multiplication.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FMADD_Top_Single_Cycle.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_comparison.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_CSR.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_dec_ctl.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_decode.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_exu.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_F2I.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_Fclass.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_fpr_ctl.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_FSM_Control_Decode.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_FSM_TOP.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_Input_Validation.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_move.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_sign_injection.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/FPU_Top_Single_Cycle.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/I2F_main.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/iccm_controller.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/inst_checker.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_comb.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_layer0.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_layer1.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_layer2.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_layer3.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_layer4.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_main.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/LZD_mux.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/Main_Decode.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/uart_rx_prog.v
+-v $(USER_PROJECT_VERILOG)/rtl/FPU/Sky130_SRAM_1kbyte_Memory.v
 
- 
\ No newline at end of file
+ 
diff --git a/verilog/rtl/FPU/Dec_gpr_ctl.v b/verilog/rtl/FPU/Dec_gpr_ctl.v
index 8f7b702..384bde4 100644
--- a/verilog/rtl/FPU/Dec_gpr_ctl.v
+++ b/verilog/rtl/FPU/Dec_gpr_ctl.v
@@ -1,5 +1,3 @@
-`include "beh_lib.v"
-
 module dec_gpr_ctl
 #(
   parameter XLEN = 32
diff --git a/verilog/rtl/FPU/Execution.v b/verilog/rtl/FPU/Execution.v
index e6d01fc..25c7e48 100644
--- a/verilog/rtl/FPU/Execution.v
+++ b/verilog/rtl/FPU/Execution.v
@@ -1,6 +1,4 @@
-`include "FPU_exu.v"
-
-module Execution(clk,rst_l,RS1_d,RS2_d,result,Flag_ADDI,Flag_LI,Activation_Signal,Flag_Reset,fpu_active,illegal_config,valid_execution,fs1_data,fs2_data,fs3_data,sfpu_op,fpu_pre,fpu_rounding,float_control,fpu_result_1,S_flag,dec_i0_rs1_en_d,dec_i0_rs2_en_d,IV_exception,fpu_complete,fpu_sel);
+module Execution(clk,rst_l,RS1_d,RS2_d,result,Flag_ADDI,Flag_LI,Activation_Signal,Flag_Reset,fpu_active,illegal_config,valid_execution,fs1_data,fs2_data,fs3_data,sfpu_op,fpu_pre,fpu_rounding,float_control,fpu_result_1,S_flag,dec_i0_rs1_en_d,dec_i0_rs2_en_d,IV_exception,fpu_complete,fpu_sel,fpu_result_rd_w,fpu_complete_rd);
     input clk,rst_l,Flag_ADDI,Flag_LI,Flag_Reset,fpu_active,illegal_config,valid_execution,dec_i0_rs1_en_d,dec_i0_rs2_en_d;
     input [31:0]RS1_d,RS2_d;
     input [15:0]fs1_data,fs2_data,fs3_data;
@@ -14,10 +12,11 @@
     output [4:0]S_flag;
     output IV_exception;
     output fpu_complete;
+    output [31:0]fpu_result_rd_w;
+    output fpu_complete_rd;
 
     wire [31:0]result_w;
     wire complete; 
-    wire [31:0]fpu_result_rd_w;
 
     FPU_exu FPU_Execution(
                          .clk(clk),
@@ -40,7 +39,8 @@
                          .fpu_result_rd(fpu_result_rd_w),                          // integer result
                          .fpu_complete(fpu_complete),
                          .sflags(S_flag),
-                         .IV_exception(IV_exception)
+                         .IV_exception(IV_exception),
+                         .fpu_complete_rd(fpu_complete_rd)
                          );
 
     assign result_w = (~rst_l) ? 32'h00000000 : (Flag_ADDI | Flag_LI) ? (RS1_d + RS2_d) : 32'h00000000;
@@ -57,7 +57,7 @@
         else
         begin
             result = result_w;
-            Activation_Signal = complete;
+            Activation_Signal =  complete;
         end
     end
 
diff --git a/verilog/rtl/FPU/FMADD_Exponent_Matching.v b/verilog/rtl/FPU/FMADD_Exponent_Matching.v
index 3ef15c4..bc8c78c 100644
--- a/verilog/rtl/FPU/FMADD_Exponent_Matching.v
+++ b/verilog/rtl/FPU/FMADD_Exponent_Matching.v
@@ -68,7 +68,7 @@
 //decision fo rrounding bits
 assign Exponent_Matching_output_Guard = Exponent_Matching_Shifter_output[man+man+3] ;
 assign Exponent_Matching_output_Round = Exponent_Matching_Shifter_output[man+man+2] ;
-assign Exponent_Matching_output_Sticky = (|Exponent_Matching_Shifter_output [man+man:0]) ;
+assign Exponent_Matching_output_Sticky = (Exponent_Matching_Shif_Amount >= 96) ? 1'b1: (|Exponent_Matching_Shifter_output [man+man+1:0]) ;
 
 
 endmodule
\ No newline at end of file
diff --git a/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v b/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v
index 3a94261..32ec8c9 100644
--- a/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v
+++ b/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v
@@ -1,12 +1,7 @@
-`include "fma_LZD.v"
 
 module FMADD_PN_MUL( FMADD_PN_MUL_input_sign, FMADD_PN_MUL_input_exp_DB, FMADD_PN_MUL_input_multiplied_man, FMADD_PN_MUL_input_lzd, FMADD_PN_MUL_input_rm, FMADD_PN_MUL_input_A_neg, FMADD_PN_MUL_input_A_pos, FMADD_PN_MUL_input_A_sub, FMADD_PN_MUL_input_B_neg, FMADD_PN_MUL_input_B_pos, FMADD_PN_MUL_input_B_sub, FMADD_PN_MUL_output_no, FMADD_PN_MUL_output_overflow, FMADD_PN_MUL_output_sticky_PN);
 
-initial
-begin
-	$dumpfile("dump.vcd");
-	$dumpvars(0);
-end
+
 
 //Defining Parameters
 parameter std = 31;//Standard - 1
@@ -77,14 +72,13 @@
 assign FMADD_PN_MUL_wire_expDB_sub_127_extra_bit = FMADD_PN_MUL_input_exp_DB - bias[exp+1:0];
 
 
-
+//condition1 == FMADD_PN_MUL_wire_op_3
 assign FMADD_PN_MUL_wire_exp_shifts_interim = FMADD_PN_MUL_wire_op_3 ? (FMADD_PN_MUL_wire_expDB_sub_127_extra_bit[exp : 0]) : (FMADD_PN_MUL_wire_127_sub_expDB_extra_bit[exp : 0]);
 
 //man+man+4 is first stored here since man is a parameter and parameters are 32 bit wide so using parameter directly will raise a mismatch error.
 assign FMADD_PN_MUL_wire_useless = man+man+4;
-assign FMADD_PN_MUL_wire_shifts_overflow = (FMADD_PN_MUL_wire_exp_shifts_interim > man+man+4) | (FMADD_PN_MUL_input_A_sub & FMADD_PN_MUL_input_B_sub);
 //If shifts are greater than 48 then set then to 48.
-assign FMADD_PN_MUL_wire_exp_shifts = (FMADD_PN_MUL_wire_shifts_overflow) ? (FMADD_PN_MUL_wire_useless[(lzd+1) : 0]) : (FMADD_PN_MUL_wire_exp_shifts_interim[(lzd+1) : 0]) ; 
+assign FMADD_PN_MUL_wire_exp_shifts = (FMADD_PN_MUL_wire_exp_shifts_interim > (man+man+4)) ? (FMADD_PN_MUL_wire_useless[(lzd+1) : 0]) : (FMADD_PN_MUL_wire_exp_shifts_interim[(lzd+1) : 0]) ; 
 
 assign FMADD_PN_MUL_wire_condition_2 = FMADD_PN_MUL_wire_op_3 & (!(FMADD_PN_MUL_input_lzd_shifts > FMADD_PN_MUL_wire_expDB_sub_127_extra_bit));
 assign FMADD_PN_MUL_wire_shifts_lzd_msb = FMADD_PN_MUL_wire_condition_2 ? ({1'b0,FMADD_PN_MUL_input_lzd_shifts}) : { ({(lzd+1){1'b0}}) , (!FMADD_PN_MUL_input_multiplied_man[man+man+3])} ;
@@ -123,9 +117,9 @@
 assign FMADD_PN_MUL_wire_man_final = (FMADD_PN_MUL_wire_man_interim[man+man+4]) ? FMADD_PN_MUL_wire_man_interim[man+man+4 : 1] : FMADD_PN_MUL_wire_man_interim[man+man+3 : 0];
 
 //Exponent Logic
-
-
-assign FMADD_PN_MUL_wire_condition_5 = FMADD_PN_MUL_wire_op_4 | (FMADD_PN_MUL_wire_op_5 & PM_MUL_wire_sub_or_norm_op5) | (FMADD_PN_MUL_wire_op_3 & (FMADD_PN_MUL_input_lzd_shifts > FMADD_PN_MUL_wire_expDB_sub_127_extra_bit)) | (FMADD_PN_MUL_input_A_sub & FMADD_PN_MUL_input_B_sub) ;
+wire FMADD_PN_MUL_wire_pos_into_sub_subnormal;
+assign FMADD_PN_MUL_wire_pos_into_sub_subnormal = (FMADD_PN_MUL_wire_op_3 & (FMADD_PN_MUL_input_lzd_shifts > FMADD_PN_MUL_wire_expDB_sub_127_extra_bit)) | (FMADD_PN_MUL_input_A_sub & FMADD_PN_MUL_input_B_sub);
+assign FMADD_PN_MUL_wire_condition_5 = FMADD_PN_MUL_wire_op_4 | (FMADD_PN_MUL_wire_op_5 & PM_MUL_wire_sub_or_norm_op5) | FMADD_PN_MUL_wire_pos_into_sub_subnormal ;
 
 // Zero is first stored here since exponent size of different standards is different and using one specific size for FMADD_PN_MUL_wire_exp_interim_1 will raise a mismatch error.
 assign FMADD_PN_MUL_wire_zero_useless = 0;
@@ -142,18 +136,28 @@
 
 assign FMADD_PN_MUL_wire_exp_interim_5 = FMADD_PN_MUL_wire_condition_7 ? FMADD_PN_MUL_wire_exp_interim_4 : FMADD_PN_MUL_wire_exp_interim_3 ;
 
+wire [exp+1 : 0] FMADD_PN_MUL_wire_exp_interim_6 ;
+wire FMADD_PN_MUL_wire_condition_8 ;
+
+assign FMADD_PN_MUL_wire_condition_8 = ((FMADD_PN_MUL_wire_man_final[man+man+3]) & FMADD_PN_MUL_wire_pos_into_sub_subnormal & (&(!FMADD_PN_MUL_wire_exp_interim_5)));
+assign FMADD_PN_MUL_wire_exp_interim_6 = (FMADD_PN_MUL_wire_condition_8) ? (FMADD_PN_MUL_wire_exp_interim_5 + 1'b1) : (FMADD_PN_MUL_wire_exp_interim_5) ;
+
 //Selection of what exception to output in case of overflow, max normal number or infinity
 
 assign FMADD_PN_MUL_wire_exception_cond1 = (FMADD_PN_MUL_input_rm == 3'b000 | FMADD_PN_MUL_input_rm == 3'b100) | ((!FMADD_PN_MUL_input_sign) & (FMADD_PN_MUL_input_rm == 3'b011)) | ((FMADD_PN_MUL_input_sign) & (FMADD_PN_MUL_input_rm == 3'b010));
 assign FMADD_PN_MUL_wire_output_interim_1 = (FMADD_PN_MUL_wire_exception_cond1) ? ({ FMADD_PN_MUL_input_sign, ({exp+1{1'b1}}), ({man+man+4{1'b0}}) }) : ({ FMADD_PN_MUL_input_sign, ({{exp{1'b1}}, 1'b0}), ({man+man+4{1'b1}}) });
 //condition to select output, either exception or result from main, in case 9th bit (singke precision) of exp is high or bits from 8:0 are high then it is overflow
-assign FMADD_PN_MUL_wire_exception_cond2 = FMADD_PN_MUL_wire_exp_interim_5[exp+1] | (&FMADD_PN_MUL_wire_exp_interim_5[exp : 0]);
+assign FMADD_PN_MUL_wire_exception_cond2 = FMADD_PN_MUL_wire_exp_interim_6[exp+1] | (&FMADD_PN_MUL_wire_exp_interim_6[exp : 0]);
 //Selecting what to output exception or result coming form main
-assign FMADD_PN_MUL_output_no = (FMADD_PN_MUL_wire_exception_cond2) ? (FMADD_PN_MUL_wire_output_interim_1) : ({FMADD_PN_MUL_input_sign, (FMADD_PN_MUL_wire_exp_interim_5[exp : 0]), FMADD_PN_MUL_wire_man_final}) ;
+assign FMADD_PN_MUL_output_no = (FMADD_PN_MUL_wire_exception_cond2) ? (FMADD_PN_MUL_wire_output_interim_1) : ({FMADD_PN_MUL_input_sign, (FMADD_PN_MUL_wire_exp_interim_6[exp : 0]), FMADD_PN_MUL_wire_man_final}) ;
 //In case cond2 is high overflow flag is set to one
 assign FMADD_PN_MUL_output_overflow = FMADD_PN_MUL_wire_exception_cond2;
 
 //in case shifts are greater than M+N or subnormal numbers are getting multiplied with each other then sticky_PN will get high.
 assign FMADD_PN_MUL_output_sticky_PN = FMADD_PN_MUL_wire_shifts_overflow;
 
+//If mantissa after all the processing is zero than it means it has became zero due to shifting and sticky is one.
+assign FMADD_PN_MUL_wire_shifts_overflow = (!(|FMADD_PN_MUL_wire_man_final)) | (FMADD_PN_MUL_input_A_sub & FMADD_PN_MUL_input_B_sub);
+
+
 endmodule
\ No newline at end of file
diff --git a/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v b/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v
index b8bf8e2..781d5c2 100644
--- a/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v
+++ b/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v
@@ -1,16 +1,25 @@
 
 // Designed by : ALi Raza Zaidi
 //mains modue of FMADD 
-/*
-//including coommon blocks
+
+
+//mains modue of FMADD 
+
+/*//including coommon blocks
+
 `include "FMADD_M_G.v"
 `include "FMADD_Ext.v"
 `include "F_LZD_Main.v"
+`include "fma_LZD_L0.v"
+`include "fma_LZD_L1.v"
+`include "fma_LZD_L2.v"
+`include "fma_LZD_L3.v"
+`include "fma_LZD_L4.v"
 
 //including Multiplication LANE
 `include "FMADD_E_A.v"
 `include "FMADD_mult.v"
-`include "FMADD_PN_MUL.v"
+`include "FMADD_PN_Mul.v"
 `include "FMADD_RB_MUL.v"
 
 //Includign Addition/Subtraction LANE
@@ -20,13 +29,38 @@
 `include "FMADD_RB_Ad.v"*/
 
 
+
+//including coommon blocks
+/*
+`include "FMADD_mantissa_generator.v"
+`include "FMADD_extender.v"
+`include "fma_LZD.v"
+`include "fma_LZD_L0.v"
+`include "fma_LZD_L1.v"
+`include "fma_LZD_L2.v"
+`include "fma_LZD_L3.v"
+`include "fma_LZD_L4.v"
+
+//including Multiplication LANE
+`include "FMADD_exponent_addition.v"
+`include "FMADD_mantissa_multiplication.v"
+`include "FMADD_mul_post_normalization.v"
+`include "FMADD_mul_rounding_block.v"
+
+//Includign Addition/Subtraction LANE
+`include "FMADD_exponent_matching.v"
+`include "FMADD_mantissa_addition.v"
+`include "FMADD_add_post_normalization.v"
+`include "FMADD_add_rounding_Block.v"
+*/
+
 module FPU_FMADD_SUBB_Top (FMADD_SUBB_input_IEEE_A, FMADD_SUBB_input_IEEE_B, FMADD_SUBB_input_IEEE_C, FMADD_SUBB_input_opcode,rst_l,FMADD_SUBB_input_Frm,FMADD_SUBB_output_IEEE_FMADD, FMADD_SUBB_output_S_Flags_FMADD, FMADD_SUBB_output_IEEE_FMUL, FMADD_SUBB_output_S_Flags_FMUL );
 
 parameter std =31;
 parameter man =22;
 parameter exp = 7;
-parameter bias = 8'b01111111;
-parameter lzd = 3;
+parameter bias = 127;
+parameter lzd = 4;
 
 //declaration of inputs
 input  [std:0] FMADD_SUBB_input_IEEE_A, FMADD_SUBB_input_IEEE_B,FMADD_SUBB_input_IEEE_C;
@@ -138,7 +172,7 @@
 
 //instantiation of LZD module
 wire [23:0] input_LZD;
-wire [4:0] output_interim_LZD;
+wire [lzd : 0] output_interim_LZD, output_interim_1_LZD;
 
 assign input_LZD = (output_interim_A_sub_norm) ? output_interim_M_G_A[man+1:0] : output_interim_M_G_B[man+1:0] ;
 
@@ -146,7 +180,11 @@
 FMADD_PN_LZD Leading_Zero_detection (
                   .FMADD_PN_LZD_input_man_48(input_LZD), 
                   .FMADD_PN_LZD_output_pos(output_interim_LZD)
-                  );
+);
+
+//5'b1100 == 2;s compliment of 8, 8 is subtracted from the final result since the LZD is of 32 bit and actual data is of 24 bit.                  
+//assign to_add_in_lzd_mul = (output_interim_LZD + 5'b11000);
+assign output_interim_1_LZD = output_interim_LZD ;
 
 
 //post normalaization Module
@@ -157,7 +195,7 @@
                   . FMADD_PN_MUL_input_sign (output_interim_exponent_addition_sign),  
                   . FMADD_PN_MUL_input_multiplied_man (output_interim_mantissa_multiplication),
                   . FMADD_PN_MUL_input_exp_DB (output_interim_exponent_addition),
-                  . FMADD_PN_MUL_input_lzd (output_interim_LZD),
+                  . FMADD_PN_MUL_input_lzd (output_interim_1_LZD),
                   . FMADD_PN_MUL_input_A_sub  (output_interim_A_sub_norm),
                   . FMADD_PN_MUL_input_B_sub  (output_interim_B_sub_norm),
                   . FMADD_PN_MUL_input_A_pos  (output_interim_A_pos_exp),
@@ -305,7 +343,7 @@
 defparam Rounding_Block_Add.man = man;
 
 //Multiplication lane output ports
-assign  FMADD_SUBB_output_IEEE_FMUL = ( (~FMADD_SUBB_input_opcode[2]) | underflow_FMUL | (~rst_l) ) ?  { std+1 {1'b0} } : output_rounding_Block ;
+assign  FMADD_SUBB_output_IEEE_FMUL = ( (~FMADD_SUBB_input_opcode[2]) | (~rst_l) ) ?  { std+1 {1'b0} } : output_rounding_Block ;
 assign  FMADD_SUBB_output_S_Flags_FMUL = (  ( FMADD_SUBB_input_opcode[2] ) & (rst_l)  ) ? output_interim_rounding_Block_S_Flag : 3'b000;
 
 //addition Lane output POrts
diff --git a/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v b/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v
index 26dfafa..812bf9c 100644
--- a/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v
+++ b/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v
@@ -1,4 +1,4 @@
-module FMADD_ROUND_MUL(FMADD_ROUND_MUL_input_overflow, FMADD_ROUND_MUL_input_sticky_PN, FMADD_ROUND_MUL_input_no, FMADD_ROUND_MUL_input_rm, FMADD_ROUND_MUL_output_no, FMADD_ROUND_MUL_output_S_Flags);
+module FMADD_ROUND_MUL (FMADD_ROUND_MUL_input_overflow, FMADD_ROUND_MUL_input_sticky_PN, FMADD_ROUND_MUL_input_no, FMADD_ROUND_MUL_input_rm, FMADD_ROUND_MUL_output_no, FMADD_ROUND_MUL_output_S_Flags);
 
 parameter std=31;
 parameter man =22;
@@ -44,16 +44,13 @@
 FMADD_ROUND_MUL_input_no[man+2+man+2+exp : man+2+man+2]  + 1'b1 : FMADD_ROUND_MUL_input_no[man+2+man+2+exp : man+2+man+2];
 
 //overflow occurs in case the exp and man before rounding is complete zero.
-assign FMADD_ROUND_MUL_output_underflow = &(!FMADD_ROUND_MUL_input_no[man+man+exp+4]);
+assign FMADD_ROUND_MUL_output_underflow = &(!(FMADD_ROUND_MUL_input_no[(man+man+exp+4) : (man+man+3)]));
 //Inexact is high in case any of the GRS are high or if overflow has occured
 assign FMADD_ROUND_MUL_output_inexact = FMADD_ROUND_MUL_wire_guard | FMADD_ROUND_MUL_wire_round | FMADD_ROUND_MUL_wire_sticky | FMADD_ROUND_MUL_input_sticky_PN | FMADD_ROUND_MUL_input_overflow;
 //overflow is detected in previous module of PN
 assign FMADD_ROUND_MUL_output_overflow = FMADD_ROUND_MUL_input_overflow;
 
-assign FMADD_ROUND_MUL_wire_final_man = FMADD_ROUND_MUL_output_overflow ? 
-( {(man+1){1'b0}} ) : FMADD_ROUND_MUL_wire_rounded_man[man : 0];
-
-assign FMADD_ROUND_MUL_output_no = {FMADD_ROUND_MUL_input_no[man+man+exp+5], FMADD_ROUND_MUL_wire_rounded_exp, FMADD_ROUND_MUL_wire_final_man[man:0]};
+assign FMADD_ROUND_MUL_output_no = {FMADD_ROUND_MUL_input_no[man+man+exp+5], (FMADD_ROUND_MUL_wire_rounded_exp), FMADD_ROUND_MUL_wire_rounded_man[man:0]};
 
 
 endmodule
\ No newline at end of file
diff --git a/verilog/rtl/FPU/FPU_F2I.v b/verilog/rtl/FPU/FPU_F2I.v
index d25afda..e698e05 100644
--- a/verilog/rtl/FPU/FPU_F2I.v
+++ b/verilog/rtl/FPU/FPU_F2I.v
@@ -30,11 +30,7 @@
 output FLOAT_TO_INT_output_invalid_flag;
 output FLOAT_TO_INT_output_inexact_flag;
 
-initial
-begin
-$dumpfile("Dump.vcd");
-$dumpvars(0);
-end
+
 
 
 wire [std : 0] FLOAT_TO_INT_input_wire_float;
@@ -54,7 +50,7 @@
 wire FLOAT_TO_INT_wire_hidden_bit_decision;
 
 //Setting the input to zero if rst_l or opcode_FI is low
-assign FLOAT_TO_INT_input_wire_float = (FLOAT_TO_INT_input_opcode_FI && rst_l) ? FLOAT_TO_INT_input_float
+assign FLOAT_TO_INT_input_wire_float = (FLOAT_TO_INT_input_opcode_FI && rst_l) ? FLOAT_TO_INT_input_float : {32{1'b0}};
 
 //Mapping the data to 64bit precision std
 assign FLOAT_TO_INT_wire_float_mapped = {FLOAT_TO_INT_input_wire_float[std], (FLOAT_TO_INT_input_wire_float[std-1 : man+1] - bias[exp : 0] + 11'b011_1111_1111), ( {FLOAT_TO_INT_input_wire_float[man:0], {(51-man){1'b0}}} ) };
@@ -185,4 +181,4 @@
 
 assign FLOAT_TO_INT_output_invalid_flag = FLOAT_TO_INT_wire_max | FLOAT_TO_INT_wire_min ;
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/FPU/FPU_FSM_TOP.v b/verilog/rtl/FPU/FPU_FSM_TOP.v
index dd989dc..08d4cfa 100644
--- a/verilog/rtl/FPU/FPU_FSM_TOP.v
+++ b/verilog/rtl/FPU/FPU_FSM_TOP.v
@@ -5,6 +5,48 @@
 `include "Main_Decode.v"
 `include "Execution.v"
 `include "inst_checker.v"
+`include "FPU_exu.v"
+`include "FPU_fpr_ctl.v"
+`include "FPU_dec_ctl.v"
+`include "Dec_gpr_ctl.v"
+`include "FPU_CSR.v"
+`include "FPU_decode.v"
+`include "beh_lib.v"
+`include "tb_prog.v"
+
+`include "FPU_comparison.v"
+`include "FPU_F2I.v"
+`include "FPU_Fclass.v"
+`include "FPU_Input_Validation.v"
+`include "FPU_move.v"
+`include "FPU_sign_injection.v"
+`include "FPU_Top_Single_Cycle.v"
+`include "FMADD_Add_Post_Normalization.v"
+`include "FMADD_exponent_addition.v"
+`include "FMADD_Exponent_Matching.v"
+`include "FMADD_extender.v"
+`include "FMADD_LZD_L0.v"
+`include "FMADD_LZD_L1.v"
+`include "FMADD_LZD_L2.v"
+`include "FMADD_LZD_L3.v"
+`include "FMADD_LZD_L4.v"
+`include "FMADD_LZD_main.v"
+`include "FMADD_mantissa_addition.v"
+`include "FMADD_mantissa_generator.v"
+`include "FMADD_mantissa_multiplication.v"
+`include "FMADD_Mul_Post_Normalization.v"
+`include "FMADD_rounding_block_Addition.v"
+`include "FMADD_rounding_block_Multiplication.v"
+`include "FMADD_Top_Single_Cycle.v"
+`include "I2F_main.v"
+`include "LZD_layer0.v"
+`include "LZD_layer1.v"
+`include "LZD_layer2.v"
+`include "LZD_layer3.v"
+`include "LZD_layer4.v"
+`include "LZD_main.v"
+`include "LZD_mux.v"
+`include "LZD_comb.v"
 
 
 module FPU_FSM_TOP(r_Rx_Serial,clk,rst_l);
@@ -43,12 +85,14 @@
     wire [15:0] fs1_data,fs2_data,fs3_data;
     wire [2:0] fpu_pre,fpu_rounding;
     wire [23:0] sfpu_op;
-    wire fpu_active,fpu_complete;
+    wire fpu_active,fpu_complete,fpu_complete_rd;
     wire [15:0]fpu_result_1;
     wire dec_i0_rs1_en_d,dec_i0_rs2_en_d;
     wire [4:0]S_flag;
     wire IV_exception;
     wire[2:0]fpu_sel;
+    wire [31:0]fpu_result_rd_w;
+
     FPU_FSM FSM(
                 .clk(clk),
                 .rst_l(rst_l),
@@ -123,7 +167,9 @@
                     .fpu_rounding(fpu_rounding),
                     .dec_i0_rs1_en_d(dec_i0_rs1_en_d),
                     .dec_i0_rs2_en_d(dec_i0_rs2_en_d),
-                    .fpu_sel(fpu_sel)
+                    .fpu_sel(fpu_sel),
+                    .fpu_result_rd_w(fpu_result_rd_w),
+                    .fpu_complete_rd(fpu_complete_rd)
                 );
 
     Execution Excecution_Unit(
@@ -152,7 +198,9 @@
                             .dec_i0_rs2_en_d(dec_i0_rs2_en_d),
                             .IV_exception(IV_exception),
                             .fpu_complete(fpu_complete),
-                            .fpu_sel(fpu_sel)
+                            .fpu_sel(fpu_sel),
+                            .fpu_result_rd_w(fpu_result_rd_w),
+                            .fpu_complete_rd(fpu_complete_rd)
                             );
 
     Inst_check Inst_Checker(
diff --git a/verilog/rtl/FPU/FPU_Fclass.v b/verilog/rtl/FPU/FPU_Fclass.v
index 6712098..cf6c3a5 100644
--- a/verilog/rtl/FPU/FPU_Fclass.v
+++ b/verilog/rtl/FPU/FPU_Fclass.v
@@ -1,24 +1,33 @@
-module Parameterized_Classification_32 (Classification_Input,rst_l,Classification_Qnan_Output,Classification_Snan_Output,Classification_Pos_Infinity_Output,Classification_Pos_Normal_Output, Classification_Pos_Subnormal_Output,Classification_Pos_Zero_Output,Classification_Neg_Zero_Output,Classification_Neg_Subnormal_Output,Classification_Neg_Normal_Output,Classification_Neg_Infinity_Output,Classification_Output);
+module FPU_Fclass (Classification_Input,rst_l,Classification_Output,opcode);
+  
+  
   // Parameters
   parameter Std = 15; // Std = Std - 1
-  parameter Man = 7; // Mantissa  
+  parameter Man = 9; // Mantissa  
+  
   // Inputs 
   input [Std:0] Classification_Input;
   input rst_l;
+  input opcode;
+
   // Outputs
-  output Classification_Qnan_Output,Classification_Snan_Output,Classification_Pos_Infinity_Output,Classification_Pos_Normal_Output, Classification_Pos_Subnormal_Output,Classification_Pos_Zero_Output,Classification_Neg_Zero_Output,Classification_Neg_Subnormal_Output,Classification_Neg_Normal_Output,Classification_Neg_Infinity_Output; 
-  output [9:0] Classification_Output;
-  
+   output [31:0] Classification_Output;
+
+  //wires
+  wire Classification_Qnan_Output,Classification_Snan_Output,Classification_Pos_Infinity_Output,Classification_Pos_Normal_Output, Classification_Pos_Subnormal_Output,Classification_Pos_Zero_Output,Classification_Neg_Zero_Output,Classification_Neg_Subnormal_Output,Classification_Neg_Normal_Output,Classification_Neg_Infinity_Output; 
+
+
+
   // Check to see if reset is either high or low
-  assign Classification_Output = rst_l ? {Classification_Qnan_Output,Classification_Snan_Output,Classification_Pos_Infinity_Output,Classification_Pos_Normal_Output, Classification_Pos_Subnormal_Output,Classification_Pos_Zero_Output,Classification_Neg_Zero_Output,Classification_Neg_Subnormal_Output,Classification_Neg_Normal_Output,Classification_Neg_Infinity_Output} : 10'b0000000000;
+  assign Classification_Output = (rst_l & opcode ) ? { {22{1'b0}},  Classification_Qnan_Output,Classification_Snan_Output,Classification_Pos_Infinity_Output,Classification_Pos_Normal_Output, Classification_Pos_Subnormal_Output,Classification_Pos_Zero_Output,Classification_Neg_Zero_Output,Classification_Neg_Subnormal_Output,Classification_Neg_Normal_Output,Classification_Neg_Infinity_Output} : {32{1'b0}};
   
   
   // -ve infinity
-  assign Classification_Neg_Infinity_Output = Classification_Input[Std] & (&(Classification_Input[Std-1:Man])) & (&(~Classification_Input[Man-1:0])); 
+  assign Classification_Neg_Infinity_Output = Classification_Input[Std] & (&(Classification_Input[Std-1:Man+1])) & (&(~Classification_Input[Man:0])); 
   
   
   // +ve infinity
-  assign Classification_Pos_Infinity_Output = ~Classification_Input[Std] & (&(Classification_Input[Std-1:Man])) & (&(~Classification_Input[Man-1:0]));
+  assign Classification_Pos_Infinity_Output = ~Classification_Input[Std] & (&(Classification_Input[Std-1:Man+1])) & (&(~Classification_Input[Man:0]));
   
   
   // -ve 0
@@ -30,26 +39,26 @@
   
   
   // snan
-  assign Classification_Snan_Output = &(Classification_Input[Std-1:Man]) & ~Classification_Input[Man-1] & (|(Classification_Input[Man-2:0]));
+  assign Classification_Snan_Output = &(Classification_Input[Std-1:Man+1]) & (~Classification_Input[Man]) & (|(Classification_Input[Man-1:0]));
   
   
   // qnan
-  assign Classification_Qnan_Output = &(Classification_Input[Std-1:Man]) & Classification_Input[Man-1] & (|(Classification_Input[Man-2:0]));
+  assign Classification_Qnan_Output = &(Classification_Input[Std-1:Man+1]) & Classification_Input[Man] ;
   
   
   // +ve normal 
-  assign Classification_Pos_Normal_Output = ~Classification_Input[Man] & (~(&(Classification_Input[Std-1:Man])) & (|(Classification_Input[Std-1:Man])));
+  assign Classification_Pos_Normal_Output = ( (~Classification_Input[Std]) & ( |(Classification_Input[Std-1:Man+1]) )   ) & (~(& Classification_Input[Std-1:Man+1]))  ;
 
   
   // -ve normal
-  assign Classification_Neg_Normal_Output = Classification_Input[Std] & (~(&(Classification_Input[Std-1:Man])) & (|(Classification_Input[Std-1:Man])));
+  assign Classification_Neg_Normal_Output =  ( (Classification_Input[Std]) & (|(Classification_Input[Std-1:Man+1]))  ) & (~(& Classification_Input[Std-1:Man+1])) ;
   
   
   // +ve subnormal
-  assign Classification_Pos_Subnormal_Output = ~Classification_Input[Std] & (&(~Classification_Input[Std-1:Man])) & (|(Classification_Input[Man-1:0]));
+  assign Classification_Pos_Subnormal_Output = ~Classification_Input[Std] & (&(~Classification_Input[Std-1:Man+1])) & (|(Classification_Input[Man:0]));
   
   
   // -ve subnormal
-  assign Classification_Neg_Subnormal_Output = Classification_Input[Std] & (&(~Classification_Input[Std-1:Man])) & (|(Classification_Input[Man-1:0]));
+  assign Classification_Neg_Subnormal_Output = Classification_Input[Std] & (&(~Classification_Input[Std-1:Man+1])) & (|(Classification_Input[Man:0]));
   
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/FPU/FPU_Top_Single_Cycle.v b/verilog/rtl/FPU/FPU_Top_Single_Cycle.v
index 1b54a37..79cf168 100644
--- a/verilog/rtl/FPU/FPU_Top_Single_Cycle.v
+++ b/verilog/rtl/FPU/FPU_Top_Single_Cycle.v
@@ -141,6 +141,7 @@
               .IEEE_B(Operand_B),
               .IEEE_out(output_interim_FPU_sign)
 );
+
 defparam Floating_sign_injection.Std=std;
 defparam Floating_sign_injection.Man=man;
 defparam Floating_sign_injection.Exp=exp;
@@ -205,8 +206,8 @@
 defparam Floating_Comparison.Man=man;
 defparam Floating_Comparison.Exp=exp;
 
-/*//module instantiation for FCLASS instruction
-wire [std:0] output_interim_Fclass;
+//module instantiation for FCLASS instruction
+wire [31:0] output_interim_Fclass;
 
 FPU_Fclass Floating_Classify (
                             .rst_l (rst_l),
@@ -214,10 +215,12 @@
                             .Classification_Input (Operand_A),
                             .opcode (sfpu_op[21] | vfpu_op[25])
 );
+
 defparam Floating_Classify.Std=std;
-defparam Floating_Classify.man=man;
-defparam Floating_Classify.exp=exp;
-*/
+defparam Floating_Classify.Man=man;
+
+
+
 // module instantiation for Fmadd/fmsub/fnmadd/fnmsub/fadd/fsub/fmul instruction
 wire [std:0] output_interim_FMADD,output_interim_Fmul;
 wire [2:0] output_interim_S_Flags_Fmul, output_interim_S_Flags_Fmadd;
@@ -322,12 +325,12 @@
     S_Flags_reg <= 5'b00000; 
     end            
 
-  /*else if (sfpu_op[21] | vfpu_op[25])               //output slection for Fclass instructions
+  else if (sfpu_op[21] | vfpu_op[25])               //output slection for Fclass instructions
     begin
      FPU_resultant_reg <= 32'h00000000;
      FPU_Result_rd_reg <= output_interim_Fclass;
      S_Flags_reg <= 5'b00000; 
-    end*/
+    end
   else    
     begin
      FPU_resultant_reg <= 32'h00000000;
diff --git a/verilog/rtl/FPU/FPU_decode.v b/verilog/rtl/FPU/FPU_decode.v
index 9b5d3c5..ca3d2f5 100644
--- a/verilog/rtl/FPU/FPU_decode.v
+++ b/verilog/rtl/FPU/FPU_decode.v
@@ -1,6 +1,3 @@
-`include "FPU_fpr_ctl.v"
-`include "FPU_dec_ctl.v"
-
 module FPU_decode #(parameter FPLEN = 16)
    (
    input 		clk,
diff --git a/verilog/rtl/FPU/FPU_exu.v b/verilog/rtl/FPU/FPU_exu.v
index 86b1506..1e11800 100644
--- a/verilog/rtl/FPU/FPU_exu.v
+++ b/verilog/rtl/FPU/FPU_exu.v
@@ -1,38 +1,3 @@
-`include "FPU_comparison.v"
-`include "FPU_F2I.v"
-`include "FPU_Fclass.v"
-`include "FPU_Input_Validation.v"
-`include "FPU_move.v"
-`include "FPU_sign_injection.v"
-`include "FPU_Top_Single_Cycle.v"
-`include "FMADD_Add_Post_Normalization.v"
-`include "FMADD_exponent_addition.v"
-`include "FMADD_Exponent_Matching.v"
-`include "FMADD_extender.v"
-`include "FMADD_LZD_L0.v"
-`include "FMADD_LZD_L1.v"
-`include "FMADD_LZD_L2.v"
-`include "FMADD_LZD_L3.v"
-`include "FMADD_LZD_L4.v"
-`include "FMADD_LZD_main.v"
-`include "FMADD_mantissa_addition.v"
-`include "FMADD_mantissa_generator.v"
-`include "FMADD_mantissa_multiplication.v"
-`include "FMADD_Mul_Post_Normalization.v"
-`include "FMADD_rounding_block_Addition.v"
-`include "FMADD_rounding_block_Multiplication.v"
-`include "FMADD_Top_Single_Cycle.v"
-`include "I2F_main.v"
-`include "LZD_layer0.v"
-`include "LZD_layer1.v"
-`include "LZD_layer2.v"
-`include "LZD_layer3.v"
-`include "LZD_layer4.v"
-`include "LZD_main.v"
-`include "LZD_mux.v"
-`include "LZD_comb.v"
-
-
 module FPU_exu #(parameter FPLEN = 16) (
 input clk,
 input rst_l,
@@ -55,7 +20,9 @@
 output [31:0]       fpu_result_rd,                          // integer result
 output fpu_complete,
 output [4:0] sflags,
-output IV_exception
+output IV_exception,
+output fpu_complete_rd
+
 );
 
 reg [23:0] sfpu_op_r;
@@ -68,6 +35,7 @@
 wire [FPLEN-1:0]           fpu_result_rx;
 wire [4:0] fpu_flags;
 wire [31:0]FPU_Result_rd,Operand_Int;
+
 // sfpu_op [0]  = fadd
 // sfpu_op [1]  = fsub
 // sfpu_op [2]  = fmul
@@ -145,5 +113,5 @@
 	// FPU GPR result
 	assign fpu_result_rd = (rst_l == 1'b0) ? {32{1'b0}} : (fpu_complete & ((|sfpu_op_r[11:9]) | sfpu_op_r[14] | sfpu_op_r[8] | sfpu_op_r[21])) ? FPU_Result_rd : 
 								   {32{1'b0}};
-	
+	assign fpu_complete_rd = (~rst_l) ? 1'b0 : (fpu_complete & ((|sfpu_op_r[11:8]) | sfpu_op_r[14] | sfpu_op_r[21])) ? 1'b1 : 1'b0;
 endmodule
diff --git a/verilog/rtl/FPU/I2F_main.v b/verilog/rtl/FPU/I2F_main.v
index 52a8137..f98aa5d 100644
--- a/verilog/rtl/FPU/I2F_main.v
+++ b/verilog/rtl/FPU/I2F_main.v
@@ -1,4 +1,4 @@
-`include "I2F_LZD.v"
+
 
 module FPU_Int_to_Float(INT_TO_FLOAT_input_int, INT_TO_FLOAT_input_rm, INT_TO_FLOAT_input_opcode_IF, INT_TO_FLOAT_input_opcode_signed, INT_TO_FLOAT_input_opcode_unsigned, INT_TO_FLOAT_output_float, INT_TO_FLOAT_output_invalid_flag, INT_TO_FLOAT_output_inexact_flag, rst_l);
 
@@ -117,4 +117,4 @@
 //Inexact Flag
 assign INT_TO_FLOAT_output_inexact_flag = INT_TO_FLOAT_wire_guard | INT_TO_FLOAT_wire_round | INT_TO_FLOAT_wire_sticky;
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/FPU/Main_Decode.v b/verilog/rtl/FPU/Main_Decode.v
index 5062802..4bf7239 100644
--- a/verilog/rtl/FPU/Main_Decode.v
+++ b/verilog/rtl/FPU/Main_Decode.v
@@ -1,15 +1,9 @@
-`include "Dec_gpr_ctl.v"
-`include "FPU_CSR.v"
-`include "FPU_decode.v"
+module Main_Decode(clk,rst_l,Instruction,S_flag,Flag_LI,Flag_ADDI,RS1_d,RS2_d,Activation_Signal,result,Flag_Reset,Flag_CSR,Flag_CSR_r,fpu_active,fpu_complete,sfpu_op,fpu_pre,fs1_data,fs2_data,fs3_data,valid_execution,illegal_config,float_control,halt_req,fpu_result_1,fpu_rounding,dec_i0_rs1_en_d,dec_i0_rs2_en_d,fpu_sel,fpu_result_rd_w,fpu_complete_rd);
 
 
-
-module Main_Decode(clk,rst_l,Instruction,S_flag,Flag_LI,Flag_ADDI,RS1_d,RS2_d,Activation_Signal,result,Flag_Reset,Flag_CSR,Flag_CSR_r,fpu_active,fpu_complete,sfpu_op,fpu_pre,fs1_data,fs2_data,fs3_data,valid_execution,illegal_config,float_control,halt_req,fpu_result_1,fpu_rounding,dec_i0_rs1_en_d,dec_i0_rs2_en_d,fpu_sel);
-
-
-    input clk,rst_l,Activation_Signal,fpu_active,fpu_complete;
+    input clk,rst_l,Activation_Signal,fpu_active,fpu_complete,fpu_complete_rd;
     input [4:0]S_flag;
-    input [31:0]Instruction,result;
+    input [31:0]Instruction,result,fpu_result_rd_w;
     input [15:0]fpu_result_1;
     output Flag_ADDI,Flag_LI,Flag_Reset,Flag_CSR,CSR_Write,valid_execution,illegal_config,halt_req,dec_i0_rs1_en_d,dec_i0_rs2_en_d;
     output [31:0]RS1_d,RS2_d;
@@ -36,6 +30,7 @@
     wire [2:0]scalar_control;
     wire write_en;
     wire illegal_instr;
+    wire [23:0]sfpu_op_w;
 
     always @(posedge clk)
     begin
@@ -76,7 +71,7 @@
                             .raddr1(rs2),
                             .wen0(write_en),
                             .waddr0(rd),
-                            .wd0((CSR_Read_r) ? CSR_Read_Data_r : result),
+                            .wd0((CSR_Read_r) ? CSR_Read_Data_r : (fpu_complete_rd & (~Activation_Signal) & (~CSR_Read_r)) ? fpu_result_rd_w : result),
                             .rd0(gpr_rs1),
                             .rd1(gpr_rs2),
                             .scan_mode(1'b0)
@@ -110,7 +105,7 @@
                           .rs2_address(rs2_address),
                           .rd_address(rd_address),
                           .illegal_instr(illegal_instr),
-                          .sfpu_op(sfpu_op),
+                          .sfpu_op(sfpu_op_w),
                           .fpu_rnd(fpu_rnd),
                           .fpu_pre(fpu_pre),
                           .fs1_data(fs1_data),
@@ -133,13 +128,13 @@
 
 
     // INTEGER REGISTER  FILE ASSIGNEMENTS
-    assign rs1_en = (~rst_l) ? 1'b0 : (Instruction[11:7] != 5'b00000) ? 1'b1 : (fpu_active & ~illegal_instr) ? scalar_control[0] : 1'b0;
+    assign rs1_en = (~rst_l) ? 1'b0 : ((Instruction[11:7] != 5'b00000) & (~fpu_active)) ? 1'b1 : (fpu_active & ~illegal_instr) ? scalar_control[0] : 1'b0;
     assign rs2_en = (~rst_l) ? 1'b0 : (Instruction[11:7] != 5'b00000) ? 1'b1 : (fpu_active & ~illegal_instr) ? scalar_control[1] : 1'b0;
     assign rs1 = (~rst_l) ? 5'b00000 : (Flag_ADDI) ? Instruction[19:15] : ((Function_CSR == 3'b001) & Flag_CSR) ? Instruction[19:15] : (fpu_active & ~illegal_instr) ? rs1_address : 5'b00000;
     assign rs2 = (~rst_l) ? 5'b00000 : (fpu_active & ~illegal_instr) ? rs2_address : 5'b00000;
     assign RS2_d = (~rst_l) ? 32'h00000000 : Flag_LI ? IMM_LI : (Flag_ADDI) ? {{20{IMM_ADDI[11]}},IMM_ADDI} : gpr_rs2;
     assign RS1_d = (~rst_l) ? 32'h00000000 : /*(Flag_LI) ? 32'h00000000 :*/ gpr_rs1;
-    assign write_en = (~rst_l) ? 1'b0 : (Activation_Signal | CSR_Read_r)  ? 1'b1 :  1'b0;
+    assign write_en = (~rst_l) ? 1'b0 : (Activation_Signal | CSR_Read_r)  ? 1'b1 : (fpu_complete_rd & (~Activation_Signal)) ? 1'b1 : 1'b0;
 
     // CSRRW & CSRRWI instructions ASSIGNEMENTS
     assign Flag_CSR = (~rst_l) ? 1'b0 : (Instruction[6:0] == 7'b1110011) ? 1'b1 : 1'b0;
@@ -151,5 +146,6 @@
     assign fpu_rounding = (~rst_l) ? 3'b000 : (fpu_active & (~illegal_instr) & (fpu_rnd==3'b111)) ? Fpu_Frm : (fpu_active & (~illegal_instr) & (fpu_rnd!=3'b111)) ? fpu_rnd : 3'b000;
     assign dec_i0_rs1_en_d = (~rst_l) ? 1'b0 : rs1_en;
     assign dec_i0_rs2_en_d = (~rst_l) ? 1'b0 : rs2_en;
+    assign sfpu_op = (~rst_l) ? 24'b000000 : sfpu_op_w;
 
 endmodule
\ No newline at end of file
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index c66c17f..c3c03e4 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -58,7 +58,7 @@
     `include "FPU/FPU_Input_Validation.v"
     `include "FPU/FPU_move.v"
     `include "FPU/FPU_sign_injection.v"
-    `include "FPU/FPU_Too_Single_Cycle.v"
+    `include "FPU/FPU_Top_Single_Cycle.v"
     `include "FPU/I2F_main.v"
     `include "FPU/iccm_controller.v"
     `include "FPU/inst_checker.v"
@@ -71,7 +71,7 @@
     `include "FPU/LZD_main.v"
     `include "FPU/LZD_mux.v"
     `include "FPU/Main_Decode.v"
-    `include "FPU/uart_rx_prob.v"
+    `include "FPU/uart_rx_prog.v"
     `include "FPU/Sky130_SRAM_1kbyte_Memory.v"
      
 `endif