2022-03-20 22:53:12 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: /home/wisla/sky130_skel/Myschematics/Receptor/my_chip/caravel_user_project_analog
2022-03-20 22:53:12 - [INFO] - {{Project Type Info}} analog
2022-03-20 22:53:12 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: d27b57fff3ee1d7b22beec6f2a3928e4ed7754b9
2022-03-20 22:53:12 - [INFO] - {{Tools Info}} KLayout: v0.27.7 | Magic: v8.3.265
2022-03-20 22:53:12 - [INFO] - {{PDKs Info}} Open PDKs: 32cdb2097fd9a629c91e8ea33e1f6de08ab25946 | Skywater PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
2022-03-20 22:53:12 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in '/home/wisla/sky130_skel/Myschematics/Receptor/my_chip/caravel_user_project_analog/precheck_results/20_MAR_2022___22_53_12/logs'
2022-03-20 22:53:12 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
2022-03-20 22:53:12 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
2022-03-20 22:53:13 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/wisla/sky130_skel/Myschematics/Receptor/my_chip/caravel_user_project_analog.
2022-03-20 22:53:13 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2022-03-20 22:53:14 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/wisla/sky130_skel/Myschematics/Receptor/my_chip/caravel_user_project_analog.
2022-03-20 22:53:15 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/wisla/sky130_skel/Myschematics/Receptor/my_chip/caravel_user_project_analog.
2022-03-20 22:53:15 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2022-03-20 22:53:15 - [INFO] - {{SPDX COMPLIANCE CHECK PASSED}} Project is compliant with the SPDX Standard
2022-03-20 22:53:15 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
2022-03-20 22:53:15 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2022-03-20 22:53:15 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
2022-03-20 22:53:15 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2022-03-20 22:53:16 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2022-03-20 22:53:16 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
2022-03-20 22:53:16 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2022-03-20 22:53:16 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
2022-03-20 22:53:17 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan. 
2022-03-20 22:53:17 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances). 
2022-03-20 22:53:17 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
2022-03-20 22:53:17 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
2022-03-20 22:53:17 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
2022-03-20 22:53:17 - [INFO] - PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
2022-03-20 22:53:17 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (1 instances). 
2022-03-20 22:53:17 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
2022-03-20 22:53:17 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
2022-03-20 22:53:17 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
2022-03-20 22:53:17 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2022-03-20 22:53:17 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
2022-03-20 22:53:20 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 2, for more details view /home/wisla/sky130_skel/Myschematics/Receptor/my_chip/caravel_user_project_analog/precheck_results/20_MAR_2022___22_53_12/outputs/user_analog_project_wrapper.xor.gds
2022-03-20 22:53:20 - [WARNING] - {{XOR CHECK FAILED}} The GDS file has non-conforming geometries.
2022-03-20 22:53:20 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
2022-03-20 22:53:21 - [INFO] - 0 DRC violations
2022-03-20 22:53:21 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-20 22:53:21 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
2022-03-20 22:53:24 - [INFO] - No DRC Violations found
2022-03-20 22:53:24 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-20 22:53:24 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
2022-03-20 22:53:28 - [INFO] - No DRC Violations found
2022-03-20 22:53:28 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-20 22:53:28 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
2022-03-20 22:53:31 - [INFO] - No DRC Violations found
2022-03-20 22:53:31 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-20 22:53:31 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
2022-03-20 22:53:32 - [INFO] - No DRC Violations found
2022-03-20 22:53:32 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-20 22:53:32 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
2022-03-20 22:53:34 - [INFO] - No DRC Violations found
2022-03-20 22:53:34 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-20 22:53:34 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
2022-03-20 22:53:35 - [INFO] - No DRC Violations found
2022-03-20 22:53:35 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-20 22:53:35 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in '/home/wisla/sky130_skel/Myschematics/Receptor/my_chip/caravel_user_project_analog/precheck_results/20_MAR_2022___22_53_12/logs'
2022-03-20 22:53:35 - [CRITICAL] - {{FAILURE}} 1 Check(s) Failed: ['XOR'] !!!