)]}'
{
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      "message": "routing done\n"
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      "message": "updated C4 - lvs passing\n"
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      "message": "adding C4 changes\n"
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        "time": "Mon Jun 06 00:42:52 2022 -0400"
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        "time": "Sun Jun 05 19:35:48 2022 -0400"
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        "time": "Sun Jun 05 14:49:39 2022 -0400"
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      "message": "capacitor added to c4\n"
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        "time": "Thu Jun 02 15:14:33 2022 -0400"
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        "time": "Wed Jun 01 18:50:33 2022 -0400"
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      "message": "adding C4 symbol and schematic\n"
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        "time": "Tue May 31 14:14:09 2022 -0400"
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        "time": "Tue May 31 14:14:09 2022 -0400"
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      "message": "Adding C4\n"
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        "time": "Mon May 30 23:03:12 2022 -0400"
      },
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        "name": "Charana Sonnadara",
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        "time": "Mon May 30 23:03:12 2022 -0400"
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      "message": "c4 structure added\n"
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        "time": "Fri May 27 17:32:11 2022 -0400"
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        "name": "Charana Sonnadara",
        "email": "charanas@umd.edu",
        "time": "Fri May 27 17:32:11 2022 -0400"
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        "time": "Fri May 27 16:42:10 2022 -0400"
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        "name": "Charana Sonnadara",
        "email": "charanas@umd.edu",
        "time": "Fri May 27 16:42:10 2022 -0400"
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      "message": "debug vssa1 vdda1\n"
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        "time": "Thu Mar 17 00:51:42 2022 -0400"
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        "time": "Tue Mar 15 09:59:50 2022 -0400"
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        "time": "Wed Mar 09 16:51:56 2022 -0500"
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      "committer": {
        "name": "Carl Brando",
        "email": "carllb52@gmail.com",
        "time": "Mon Mar 07 12:29:49 2022 -0500"
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      "message": "wrote gds for current magic file\n"
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    {
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        "email": "carllb52@gmail.com",
        "time": "Sun Mar 06 15:28:21 2022 -0500"
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      "message": "added 1t1r_2x2 schmatic and symbol\n"
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        "email": "carllb52@gmail.com",
        "time": "Sun Mar 06 15:15:01 2022 -0500"
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      "message": "added schematic to xschem\n"
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        "email": "carllb52@gmail.com",
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      "message": "added 2x2 1t1r reram structure to project magic file\n"
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      },
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        "email": "carllb52@gmail.com",
        "time": "Sun Mar 06 14:30:53 2022 -0500"
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      "message": "added reram cell magic file, wired select and bit lines\n"
    },
    {
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      "message": "Merge pull request #18 from efabless/EFIC-233\n\nEFIC-233"
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        "time": "Thu Feb 03 20:29:50 2022 +0200"
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      "message": "Update index.rst"
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    {
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      "message": "Update Caravel to `mpw-5a`\n\nAlso remove `make pdk-nonnative`.\n"
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        "time": "Fri Jan 28 12:40:31 2022 -0800"
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      "message": "Merge pull request #16 from efabless/EFIC-232\n\nEFIC-232 - Makefile Updates"
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    {
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      "message": "Makefile Updates\n\nUpdates to \u0027Makefile\u0027 reflected appropriate mpw-5 shuttle tags and updated precheck instructions"
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      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sun Dec 19 17:03:41 2021 -0500"
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      "message": "Modified the xschem schematics so that the wrapper level correctly\nrepresents the metal resistors that were added to the layout to\nmaintain all the pins on isolated nets.  The LVS with the xschem\nnetlist is now correct with the modified layout.  The verilog\nnetlist has not yet been updated.\n"
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    {
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      "message": "Updated the layout to properly use the metal resistors in front of\npins that are connected to the same net.  Updated the GDS with this\nchange, and also to properly generate hierarchical layers, which\napparently had not been done previously.  Verilog and schematic\nhave not yet been updated with the metal resistor change, and so\nwill fail LVS until they are.\n"
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      "message": "Merge pull request #13 from efabless/caravel_openframe\n\nremove submodule"
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      "message": "Update run-truck.sh"
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        "time": "Wed Oct 27 11:57:38 2021 -0700"
      },
      "message": "Merge pull request #12 from Manarabdelaty/update_gds\n\nUpdate gds view to match the mag view"
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      "message": "Update gds view to match the mag view\n"
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      "message": "Delete info.yaml"
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        "time": "Sun Oct 24 10:08:46 2021 -0700"
      },
      "message": "Update index.rst\n\nAdd\\ checklist item for spice netlist"
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        "time": "Tue Oct 12 15:49:11 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Tue Oct 12 15:49:11 2021 -0400"
      },
      "message": "Additional corrections to the analog wrapper testbench schematic to\nproperly quote net names with brackets, and to name a net that is\nreferenced in the plot command but hadn\u0027t been named in the\nschematic.\n"
    },
    {
      "commit": "00336fefcbe85ba1859b311b66fa1b68f7d2bf46",
      "tree": "46197294e2a37b6789841ba058e6b437825d56a8",
      "parents": [
        "ab6ba9c30b06bc7e68d9478afca6f676c7e4c1ff"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Mon Oct 11 21:43:55 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Mon Oct 11 21:43:55 2021 -0400"
      },
      "message": "Modified the xschem files to reflect the handling of Tcl variables\nthat was implemented since this repository was first created.  This\nmakes use of xschemrc to define PDKPATH and to allow it to be\noverridden from the local OS environment.\n"
    },
    {
      "commit": "ab6ba9c30b06bc7e68d9478afca6f676c7e4c1ff",
      "tree": "ac34c32719e92a95375578a447b5324b10c11f4d",
      "parents": [
        "3dc29b1a727082c620b308b4894b625acc803c92"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Tue Sep 28 10:50:49 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Tue Sep 28 10:50:49 2021 -0400"
      },
      "message": "Modified the user_analog_project_wrapper layouts (empty and example)\nto add the metal4 and metal5 layers on io_analog[6:4] that are part\nof the top level layout.  This will show users where the layers are\nso that they do not route close enough to create DRC violations where\nthey cannot see them.\n"
    },
    {
      "commit": "3dc29b1a727082c620b308b4894b625acc803c92",
      "tree": "de82ae87f9fb1e2cdf1b0d6dc1de1a23a0a116f1",
      "parents": [
        "f2d0147a8ee57175112bbc1a44d53cc72107b91e",
        "627ebc75276a18e3bf1268bc6114c5ee2e98df07"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "42048757+jeffdi@users.noreply.github.com",
        "time": "Tue Sep 21 07:45:19 2021 -0700"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Tue Sep 21 07:45:19 2021 -0700"
      },
      "message": "Merge pull request #7 from Manarabdelaty/update_spice\n\nUpdate spice netlist to pass the precheck, documentation updates, and minor CI update"
    },
    {
      "commit": "627ebc75276a18e3bf1268bc6114c5ee2e98df07",
      "tree": "de82ae87f9fb1e2cdf1b0d6dc1de1a23a0a116f1",
      "parents": [
        "eeb2287fde073efa9d48bc9f385c7088b87f7fd2",
        "03aa1fa01634c4e97e377dc7e6a27f73e1b82c03"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Tue Sep 21 01:42:33 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Tue Sep 21 01:42:33 2021 +0200"
      },
      "message": "Merge branch \u0027update_spice\u0027 of https://github.com/Manarabdelaty/caravel_user_project_analog into update_spice\n"
    },
    {
      "commit": "eeb2287fde073efa9d48bc9f385c7088b87f7fd2",
      "tree": "fbaa675f6bd73c28e409672cf1aee758bf75513c",
      "parents": [
        "5afa59116361fa3d66cc6e8786eca819a8c8e88c"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Tue Sep 21 01:41:51 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Tue Sep 21 01:41:51 2021 +0200"
      },
      "message": "[CI] Run jobs on workflow dispatch\n"
    }
  ],
  "next": "03aa1fa01634c4e97e377dc7e6a27f73e1b82c03"
}