)]}' { "commit": "f4d92bf2d5dbda8fe5d04d051879691524dcebd0", "tree": "68f876891a7484bdfc6d109398c74461ed6d0bfa", "parents": [ "00336fefcbe85ba1859b311b66fa1b68f7d2bf46" ], "author": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Tue Oct 12 15:49:11 2021 -0400" }, "committer": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Tue Oct 12 15:49:11 2021 -0400" }, "message": "Additional corrections to the analog wrapper testbench schematic to\nproperly quote net names with brackets, and to name a net that is\nreferenced in the plot command but hadn\u0027t been named in the\nschematic.\n", "tree_diff": [ { "type": "modify", "old_id": "70de684c8c13e0a00c22d7d865689449d33469e4", "old_mode": 33188, "old_path": "xschem/analog_wrapper_tb.sch", "new_id": "ee08803375adb51a4cbf4202371681a3114d53a3", "new_mode": 33188, "new_path": "xschem/analog_wrapper_tb.sch" }, { "type": "modify", "old_id": "9c566a41da2135e8ff06244c5e442f35168051ae", "old_mode": 33188, "old_path": "xschem/analog_wrapper_tb.spice", "new_id": "b32d07cf34556eaacb5dd7a301b7980e00373cfe", "new_mode": 33188, "new_path": "xschem/analog_wrapper_tb.spice" } ] }