tree 686edc225872336525566264f1e19560d81e6419
parent ea5ff7d937a3422c805b506215ae5242935638b2
author Tim Edwards <tim@opencircuitdesign.com> 1639951421 -0500
committer Tim Edwards <tim@opencircuitdesign.com> 1639951421 -0500

Modified the xschem schematics so that the wrapper level correctly
represents the metal resistors that were added to the layout to
maintain all the pins on isolated nets.  The LVS with the xschem
netlist is now correct with the modified layout.  The verilog
netlist has not yet been updated.