2022-06-08 22:25:35 - [INFO] - {{Project Git Info}} Repository: https://gitlab.com/carllb52/mixed-signal-re-ram-mpw-6.git | Branch: main | Commit: 378d35e5b1ea144852e5812a9c5a1c3b9b57012e
2022-06-08 22:25:35 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: mixed_signal_circuits_mpw6
2022-06-08 22:25:35 - [INFO] - {{Project Type Info}} analog
2022-06-08 22:25:35 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: ede6fb460a2477348ec33c934810b1c4d280c841
2022-06-08 22:25:35 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
2022-06-08 22:25:35 - [INFO] - {{PDKs Info}} Open PDKs: 27ecf1c16911f7dd4428ffab96f62c1fb876ea70 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
2022-06-08 22:25:35 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'mixed_signal_circuits_mpw6/jobs/mpw_precheck/8daa518c-0db7-4224-b312-63175ba987ab/logs'
2022-06-08 22:25:35 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
2022-06-08 22:25:35 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
2022-06-08 22:25:36 - [INFO] - An approved LICENSE (Apache-2.0) was found in mixed_signal_circuits_mpw6.
2022-06-08 22:25:36 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2022-06-08 22:25:37 - [INFO] - An approved LICENSE (Apache-2.0) was found in mixed_signal_circuits_mpw6.
2022-06-08 22:25:37 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2022-06-08 22:25:37 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in mixed_signal_circuits_mpw6/openlane/Makefile
2022-06-08 22:25:37 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 54 non-compliant file(s) with the SPDX Standard.
2022-06-08 22:25:37 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['mixed_signal_circuits_mpw6/Makefile', 'mixed_signal_circuits_mpw6/docs/Makefile', 'mixed_signal_circuits_mpw6/docs/environment.yml', 'mixed_signal_circuits_mpw6/docs/source/conf.py', 'mixed_signal_circuits_mpw6/docs/source/index.rst', 'mixed_signal_circuits_mpw6/netgen/run_lvs_por.sh', 'mixed_signal_circuits_mpw6/netgen/run_lvs_wrapper_verilog.sh', 'mixed_signal_circuits_mpw6/netgen/run_lvs_wrapper_xschem.sh', 'mixed_signal_circuits_mpw6/verilog/dv/Makefile', 'mixed_signal_circuits_mpw6/verilog/dv/mprj_por/Makefile', 'mixed_signal_circuits_mpw6/verilog/dv/mprj_por/mprj_por.c', 'mixed_signal_circuits_mpw6/verilog/dv/mprj_por/mprj_por_tb.v', 'mixed_signal_circuits_mpw6/verilog/rtl/example_por.v', 'mixed_signal_circuits_mpw6/verilog/rtl/uprj_analog_netlists.v', 'mixed_signal_circuits_mpw6/verilog/rtl/user_analog_proj_example.v']
2022-06-08 22:25:37 - [INFO] - For the full SPDX compliance report check: mixed_signal_circuits_mpw6/jobs/mpw_precheck/8daa518c-0db7-4224-b312-63175ba987ab/logs/spdx_compliance_report.log
2022-06-08 22:25:37 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
2022-06-08 22:25:37 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2022-06-08 22:25:37 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
2022-06-08 22:25:37 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2022-06-08 22:25:37 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2022-06-08 22:25:37 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
2022-06-08 22:25:37 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2022-06-08 22:25:37 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
2022-06-08 22:25:39 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan. 
2022-06-08 22:25:39 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances). 
2022-06-08 22:25:39 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
2022-06-08 22:25:39 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
2022-06-08 22:25:39 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
2022-06-08 22:25:39 - [INFO] - PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
2022-06-08 22:25:39 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (6 instances). 
2022-06-08 22:25:39 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
2022-06-08 22:25:39 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
2022-06-08 22:25:39 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
2022-06-08 22:25:39 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2022-06-08 22:25:39 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
2022-06-08 22:25:42 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view mixed_signal_circuits_mpw6/jobs/mpw_precheck/8daa518c-0db7-4224-b312-63175ba987ab/outputs/user_analog_project_wrapper.xor.gds
2022-06-08 22:25:42 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2022-06-08 22:25:42 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
2022-06-08 22:25:43 - [INFO] - 0 DRC violations
2022-06-08 22:25:43 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-06-08 22:25:43 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
2022-06-08 22:25:46 - [INFO] - No DRC Violations found
2022-06-08 22:25:46 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-06-08 22:25:46 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
2022-06-08 22:25:49 - [INFO] - No DRC Violations found
2022-06-08 22:25:49 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-06-08 22:25:49 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
2022-06-08 22:25:51 - [INFO] - No DRC Violations found
2022-06-08 22:25:51 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-06-08 22:25:51 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
2022-06-08 22:25:52 - [INFO] - No DRC Violations found
2022-06-08 22:25:52 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-06-08 22:25:52 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
2022-06-08 22:25:54 - [INFO] - No DRC Violations found
2022-06-08 22:25:54 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-06-08 22:25:54 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
2022-06-08 22:25:55 - [INFO] - No DRC Violations found
2022-06-08 22:25:55 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-06-08 22:25:55 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'mixed_signal_circuits_mpw6/jobs/mpw_precheck/8daa518c-0db7-4224-b312-63175ba987ab/logs'
2022-06-08 22:25:55 - [INFO] - {{SUCCESS}} All Checks Passed !!!