)]}'
{
  "commit": "f989c64eec2d9b563eea8c482c9fc18240bbf776",
  "tree": "7bc470abd1d58b96d22ab12790ff0d6459efe1ac",
  "parents": [
    "7ad767e82876548abbfc36b0f52224fb7cfbaf0d"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu Apr 15 20:48:24 2021 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu Apr 15 20:48:24 2021 -0400"
  },
  "message": "Corrected the user_project_wrapper verilog to have the correct\nnumber of GPIO analog-through bits (reduced by 2 since MPW-one).\nCorrected the mprj_stimulus testbench, which failed due to a\nbyproduct of the change to add flash I/O channels 2 and 3 to the\nhighest two GPIO channels.  This makes the channels different\nfrom the others and cannot be configured in the same way for the\nstimulus.  The solution was to move the status vector down by\ntwo bits to avoid those channels.  Also improved the make process\nby making the #include statement in the .c file a relative path\nand adding -I $(CARAVEL_PATH) as a gcc option.  This lets the\ntestbench run correctly with CARAVEL_PATH coming from an overriding\nenvironment variable.  This change should be applied to the other\ntestbenches as well.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8c5f7294e85bda7028b13c8c8dec39125b32adb2",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/Makefile",
      "new_id": "d94ea2225ff5264f843b40154173560b07470631",
      "new_mode": 33188,
      "new_path": "verilog/dv/mprj_stimulus/Makefile"
    },
    {
      "type": "modify",
      "old_id": "4b6d899598356a7a78c2896378cb0c05cf787339",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/mprj_stimulus.c",
      "new_id": "2fae0f1343ce15256d607d10e9a7c33d4f01eef0",
      "new_mode": 33188,
      "new_path": "verilog/dv/mprj_stimulus/mprj_stimulus.c"
    },
    {
      "type": "modify",
      "old_id": "0aaca76cb97e062a41bc789682a73fd47e4ad5aa",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/mprj_stimulus_tb.v",
      "new_id": "1409015e71ad8b171d10da7129ab3f26b05df0b7",
      "new_mode": 33188,
      "new_path": "verilog/dv/mprj_stimulus/mprj_stimulus_tb.v"
    },
    {
      "type": "modify",
      "old_id": "7cf8dada254bcb4192ace356ebdeb788ac3579fb",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "796d3aafeb69a96710751af09cdfffd00cb8f70a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}