diff --git a/gds/Marmot.gds.gz b/gds/Marmot.gds.gz
index cd14fbe..784b9d1 100644
--- a/gds/Marmot.gds.gz
+++ b/gds/Marmot.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index b787a4a..e659690 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/openlane/marmot/base.sdc b/openlane/marmot/base.sdc
index da6753b..39ed907 100644
--- a/openlane/marmot/base.sdc
+++ b/openlane/marmot/base.sdc
@@ -31,10 +31,10 @@
  -group [get_clocks {jtag_TCK}]\
 
 # max delay for RAM clocks
-set MAX_DELAY_RAM_CLOCK 6.0
+#set MAX_DELAY_RAM_CLOCK 6.0
 #set_max_delay $MAX_DELAY_RAM_CLOCK -from [get_ports wb_clk_i] -to [get_ports data_arrays_0_ext_ram_clk]
-set_max_delay $MAX_DELAY_RAM_CLOCK -from [get_ports wb_clk_i] -to [get_ports tag_array_ext_ram_clk]
-set_max_delay $MAX_DELAY_RAM_CLOCK -from [get_ports wb_clk_i] -to [get_ports data_arrays_0_0_ext_ram_clk]
+#set_max_delay $MAX_DELAY_RAM_CLOCK -from [get_ports wb_clk_i] -to [get_ports tag_array_ext_ram_clk]
+#set_max_delay $MAX_DELAY_RAM_CLOCK -from [get_ports wb_clk_i] -to [get_ports data_arrays_0_0_ext_ram_clk]
 
 # input/output delay
 set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
@@ -103,10 +103,6 @@
 set_input_delay  $input_delay_value  -clock [get_clocks jtag_TCK] [get_ports $TDI_port]
 set_output_delay $output_delay_value -clock [get_clocks jtag_TCK] [get_ports $TDO_port]
 
-# false path: static RAM clock skew adjust signals
-set_false_path -from [get_ports la_data_in[46:32]]
-set_false_path -from [get_ports la_oenb[46:32]]
-
 # max fanout
 set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
 
diff --git a/openlane/marmot/config.tcl b/openlane/marmot/config.tcl
index 5f076af..7b2577c 100644
--- a/openlane/marmot/config.tcl
+++ b/openlane/marmot/config.tcl
@@ -25,27 +25,23 @@
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 
 set ::env(DESIGN_IS_CORE) 0
+
 set ::env(DESIGN_NAME) Marmot
 
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/marmot]
 
 set ::env(VERILOG_FILES) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-  $script_dir/../../verilog/lib/clk_skew_adjust.gv \
-  $script_dir/../../verilog/lib/ctech_cells.sv \
 	[glob $script_dir/../../verilog/rtl/marmot/*.v]"
 
 set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_PERIOD) 40
+set ::env(CLOCK_PERIOD) 35
 set ::env(IO_PCT)     0.2
 set ::env(IO_PCT_RAM) 0.3
 
-#set ::env(SYNTH_CAP_LOAD) 70
-
 set ::env(BASE_SDC_FILE) $script_dir/base.sdc
 
 #set ::env(SYNTH_STRATEGY) "AREA 0"
-#set ::env(SYNTH_NO_FLAT) 1
 
 set ::env(FP_CORE_UTIL) 30
 #set ::env(FP_SIZING) absolute
diff --git a/openlane/marmot/pin_order.cfg b/openlane/marmot/pin_order.cfg
index 605f79f..0a0e4aa 100644
--- a/openlane/marmot/pin_order.cfg
+++ b/openlane/marmot/pin_order.cfg
@@ -7,6 +7,7 @@
 irq.*
 
 #N
+ram_clk_delay_sel\[.*\]
 tag_array_ext_ram_rdata0\[.*\]
 tag_array_ext_ram_addr\[.*\]
 tag_array_ext_ram_clk
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index c63b19c..7ee8ff8 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -44,64 +44,69 @@
 set ::env(ROUTING_CORES) 4
 
 # Define
-set ::env(SYNTH_DEFINES) "MARMOT_EMPTY"
+set ::env(SYNTH_DEFINES) "MARMOT_EMPTY clk_skew_adjust_EMPTY"
 
 ## Source Verilog Files
 set ::env(VERILOG_FILES) "\
-	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_project_wrapper.v"
+  $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+  $script_dir/../../verilog/rtl/user_project_wrapper.v"
 
 ## Clock configurations
 set ::env(CLOCK_PORT) "wb_clk_i"
-#set ::env(CLOCK_NET) "Marmot.clk"
 
-set ::env(CLOCK_PERIOD) "40"
+set ::env(CLOCK_PERIOD) 35
 
 set ::env(BASE_SDC_FILE) $script_dir/base.sdc
 
 set ::env(FP_PDN_HPITCH) 105
 set ::env(FP_PDN_VPITCH) 100
 
-#set ::env(FP_PDN_HWIDTH) 2.9
-
 ## Internal Macros
 ### Macro PDN Connections
 set ::env(FP_PDN_MACRO_HOOKS) "\
-	Marmot vccd1 vssd1 \
-        data_arrays_0_0_ext_ram0l vccd1 vssd1 \
-        data_arrays_0_0_ext_ram0h vccd1 vssd1 \
-        data_arrays_0_0_ext_ram1l vccd1 vssd1 \
-        data_arrays_0_0_ext_ram1h vccd1 vssd1 \
-        data_arrays_0_0_ext_ram2l vccd1 vssd1 \
-        data_arrays_0_0_ext_ram2h vccd1 vssd1 \
-        data_arrays_0_0_ext_ram3l vccd1 vssd1 \
-        data_arrays_0_0_ext_ram3h vccd1 vssd1 \
-        tag_array_ext_ram0l vccd1 vssd1 \
-        tag_array_ext_ram0h vccd1 vssd1"
+  Marmot vccd1 vssd1 \
+  u_clk_skew_adjust_0 vccd1 vssd1 \
+  u_clk_skew_adjust_1 vccd1 vssd1 \
+  u_clk_skew_adjust_2 vccd1 vssd1 \
+  u_clk_skew_adjust_3 vccd1 vssd1 \
+  u_clk_skew_adjust_4 vccd1 vssd1 \
+  data_arrays_0_0_ext_ram0l vccd1 vssd1 \
+  data_arrays_0_0_ext_ram0h vccd1 vssd1 \
+  data_arrays_0_0_ext_ram1l vccd1 vssd1 \
+  data_arrays_0_0_ext_ram1h vccd1 vssd1 \
+  data_arrays_0_0_ext_ram2l vccd1 vssd1 \
+  data_arrays_0_0_ext_ram2h vccd1 vssd1 \
+  data_arrays_0_0_ext_ram3l vccd1 vssd1 \
+  data_arrays_0_0_ext_ram3h vccd1 vssd1 \
+  tag_array_ext_ram0l vccd1 vssd1 \
+  tag_array_ext_ram0h vccd1 vssd1"
 
 ### Macro Placement
 set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
 
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
-	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/marmot/Marmot.v \
-        $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
-        $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
+  $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+  $script_dir/../../verilog/rtl/marmot/Marmot.v \
+  $script_dir/../../verilog/lib/clk_skew_adjust.gv \
+  $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+  $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
 
 set ::env(EXTRA_LEFS) "\
-	$script_dir/../../lef/Marmot.lef \
-        $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
-        $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
+  $script_dir/../../lef/Marmot.lef \
+  $script_dir/../../lef/clk_skew_adjust.lef \
+  $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
+  $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
 
 set ::env(EXTRA_GDS_FILES) "\
-	$script_dir/../../gds/Marmot.gds \
-        $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
-        $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
+  $script_dir/../../gds/Marmot.gds \
+  $script_dir/../../gds/clk_skew_adjust.gds \
+  $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
+  $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
 
 set ::env(EXTRA_LIBS) "\
-        $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib \
-        $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib"
+  $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib \
+  $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib"
 
 # Obstruction over SRAMs
 set ::env(GLB_RT_OBS) " \
@@ -157,6 +162,7 @@
 
 # The following is because there are no std cells in the example wrapper project.
 set ::env(SYNTH_TOP_LEVEL) 1
+#set ::env(PL_TIME_DRIVEN) 1
 set ::env(PL_RANDOM_GLB_PLACEMENT) 1
 
 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 70ee044..d451797 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,5 +1,5 @@
 # Logic
-Marmot 1000 300 N
+Marmot 1000 250 N
 
 # I-Cache / ITIM
 data_arrays_0_0_ext_ram0l  150  150 FN
@@ -8,8 +8,15 @@
 data_arrays_0_0_ext_ram1h  150 1830 FN
 data_arrays_0_0_ext_ram2l  150 2390 FN
 data_arrays_0_0_ext_ram2h  150 2950 FN
-data_arrays_0_0_ext_ram3l 1000 2270 FN
-data_arrays_0_0_ext_ram3h 2050 2270 N
-tag_array_ext_ram0l       1200 2890 FN
-tag_array_ext_ram0h       2050 2890 N
+data_arrays_0_0_ext_ram3l 1000 2390 FN
+data_arrays_0_0_ext_ram3h 2050 2390 N
+tag_array_ext_ram0l       1200 2950 FN
+tag_array_ext_ram0h       2050 2950 N
+
+# Clock skew adjust
+u_clk_skew_adjust_1       1000   63 N
+u_clk_skew_adjust_2       1000 2163 N
+u_clk_skew_adjust_3       1000 2898 N
+u_clk_skew_adjust_4       1845 2373 N
+u_clk_skew_adjust_0       1845 3003 N
 
diff --git a/verilog/gl/Marmot.v b/verilog/gl/Marmot.v
index f8c61ff..2dd22fe 100644
--- a/verilog/gl/Marmot.v
+++ b/verilog/gl/Marmot.v
Binary files differ
diff --git a/verilog/lib/clk_skew_adjust.gv b/verilog/lib/clk_skew_adjust.gv
index ccab011..40333c5 100644
--- a/verilog/lib/clk_skew_adjust.gv
+++ b/verilog/lib/clk_skew_adjust.gv
@@ -89,6 +89,7 @@
   output clk_out;
   input [4:0] sel;
 
+`ifndef clk_skew_adjust_EMPTY
   wire clk_d1;
   wire clk_d2;
   wire clk_d3;
@@ -229,4 +230,6 @@
   // output clock
   ctech_clk_buf u_clk_out_buf (.A(d40), .X(clk_out));
 
+`endif  // clk_skew_adjust_EMPTY
+
 endmodule