diff --git a/verilog/dv/prga/bcd2bin.v b/verilog/dv/prga/bcd2bin.v
new file mode 100644
index 0000000..70d7e91
--- /dev/null
+++ b/verilog/dv/prga/bcd2bin.v
@@ -0,0 +1,83 @@
+module bcd2bin (
+    input wire clk,
+    input wire reset,
+    input wire start,
+    input wire [3:0] bcd1,
+    input wire [3:0] bcd0,
+    output reg ready,
+    output reg done_tick,
+    output wire [6:0] bin
+    );
+
+    // symbolic state declaration
+    localparam [1:0] idle = 2'b00,
+                     op   = 2'b01,
+                     done = 2'b10;
+
+    // signal declaration
+    reg [1:0] state_reg, state_next;
+    reg [6:0] bin_reg, bin_next;
+    reg [3:0] n_reg, n_next;
+    reg [3:0] bcd1_reg, bcd0_reg;
+    reg [3:0] bcd1_next, bcd0_next;
+
+    // FSMD state & data registers
+    always @(posedge clk)
+        if (reset)
+        begin
+            state_reg <= idle;
+            bin_reg <= 0;
+            n_reg <= 0;
+            bcd1_reg <= 0;
+            bcd0_reg <= 0;
+        end else begin
+            state_reg <= state_next;
+            bin_reg <= bin_next;
+            n_reg <= n_next;
+            bcd1_reg <= bcd1_next;
+            bcd0_reg <= bcd0_next;
+        end
+
+    // FSMD next-state logic
+    always @*
+    begin
+        // defaults
+        state_next = state_reg;
+        ready = 1'b0;
+        done_tick = 1'b0;
+        bin_next = bin_reg;
+        bcd0_next = bcd0;   // route in bcd1 input
+        bcd1_next = bcd1;   // route in bcd0 input
+        n_next = n_reg;
+
+        case (state_reg)
+            idle: begin
+                ready = 1'b1;
+                if (start) begin
+                    state_next = op;
+                    n_next = 4'b0111; // iterate 7 times
+                end
+            end
+            op: begin
+                bin_next = {bcd0_reg[0], bin_reg[6:1]}; // right shift in lowest bit from bcd0_reg
+                bcd1_next = {1'b0, bcd1_reg[3:1]}; // right shift in 0 to bcd1
+                // right shift in bcd1[0] into bcd0, if bcd0 > 4, subtract 3
+                bcd0_next = ({bcd1_reg[0], bcd0_reg[3:1]} > 4) ? ({bcd1_reg[0], bcd0_reg[3:1]} - 4'b0011) : {bcd1_reg[0], bcd0_reg[3:1]};   
+
+                n_next = n_reg - 1; // decrement n
+                if (n_next==0)
+                    state_next = done; 
+            end
+            done: begin
+                done_tick = 1'b1;   
+                state_next = idle;  
+            end
+            default:
+                state_next = idle;
+        endcase
+    end  
+
+    // assign output
+    assign bin = bin_reg;
+
+endmodule
diff --git a/verilog/dv/prga/bcd2bin_test_basic.v b/verilog/dv/prga/bcd2bin_test_basic.v
new file mode 100644
index 0000000..065ef82
--- /dev/null
+++ b/verilog/dv/prga/bcd2bin_test_basic.v
@@ -0,0 +1,83 @@
+module basic (
+    input wire tb_clk,
+    input wire tb_rst,
+    output reg tb_pass,
+    output reg tb_fail,
+    input wire tb_prog_done,
+    input wire [31:0] tb_verbosity,
+    input wire [31:0] tb_cycle_cnt,
+
+    output wire clk,
+    output reg reset,
+    output reg start,
+    output reg [3:0] bcd0,
+    output reg [3:0] bcd1,
+    input wire ready,
+    input wire done_tick,
+    input wire [6:0] bin
+    );
+
+    assign clk = tb_clk;
+
+    reg [7:0] reset_buf;
+    always @(posedge tb_clk) begin
+        if (tb_rst || ~tb_prog_done) begin
+            {reset, reset_buf} <= 9'h03f;
+        end else begin
+            {reset, reset_buf} <= {reset_buf, 1'b0};
+        end
+    end
+    
+    reg [3:0] test_counter;
+    reg [7:0] source [0:15];
+    reg [6:0] sink [0:15];
+
+    // set up test source & sink
+    initial begin
+        source[0] = {4'd0, 4'd0}; sink[0] = 7'h00;
+        source[1] = {4'd9, 4'd9}; sink[1] = 7'h63;
+        source[2] = {4'd5, 4'd5}; sink[2] = 7'h37;
+        source[3] = {4'd0, 4'd9}; sink[3] = 7'h09;
+        source[4] = {4'd9, 4'd0}; sink[4] = 7'h5a;
+
+        reset = 1'b0;
+        reset_buf = 8'h0;
+        start = 1'b0;
+        test_counter = 0;
+        tb_pass = 1'b0;
+        tb_fail = 1'b0;
+        {bcd1, bcd0} = 0;
+    end
+
+    always @(posedge tb_clk) begin
+        if (tb_rst || ~tb_prog_done) begin
+            start           <=  1'b0;
+            test_counter    <=  0;
+            tb_pass     <=  1'b0;
+            tb_fail        <=  1'b0;
+            {bcd1, bcd0}    <=  0;
+        end else if (tb_prog_done) begin
+            if (~start || done_tick) begin
+                if (done_tick) begin
+                    if (bin == sink[test_counter - 1]) begin
+                        $display("[Cycle %04d] bcd2bin: %d => 0x%h",
+                            tb_cycle_cnt, bcd1 * 10 + bcd0, bin);
+                    end else begin
+                        $display("[Cycle %04d] bcd2bin: %d => 0x%h (0x%h expected), fail",
+                            tb_cycle_cnt, bcd1 * 10 + bcd0, bin, sink[test_counter - 1]);
+                        tb_fail    <=  1'b1;
+                    end
+                end
+
+                if (source[test_counter] === 8'hx) begin
+                    tb_pass     <=  1'b1;
+                end else begin
+                    {bcd1, bcd0}    <=  source[test_counter];
+                    test_counter    <=  test_counter + 1;
+                    start           <=  1'b1;
+                end
+            end
+        end
+    end
+
+endmodule
diff --git a/verilog/dv/prga/prga.c b/verilog/dv/prga/prga.c
index c316f0d..7557343 100644
--- a/verilog/dv/prga/prga.c
+++ b/verilog/dv/prga/prga.c
@@ -57,47 +57,64 @@
 	// so that the CSB line is not left floating.  This allows
 	// all of the GPIO pins to be used for user functions.
 
+    // Use GPIO as the signal that the mgmt core is ready
+    reg_gpio_mode1 = 1;
+    reg_gpio_mode0 = 1;
+    reg_gpio_ien = 1;
+    reg_gpio_oe = 1;
+
+    reg_gpio_out = 0;
+    reg_gpio_out = 0;
+
 	// Configure lower 8-IOs as user output
 	// Observe counter value in the testbench
-	//reg_mprj_io_0 =  GPIO_MODE_USER_STD_OUTPUT;
-	//reg_mprj_io_1 =  GPIO_MODE_USER_STD_OUTPUT;
-	//reg_mprj_io_2 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_3 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_4 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_5 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_6 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_7 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_8 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_9 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_10 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_11 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_12 =  GPIO_MODE_USER_STD_OUTPUT;        
-	reg_mprj_io_13 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_14 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_15 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_16 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_17 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_18 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_19 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_20 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_21 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_22 =  GPIO_MODE_USER_STD_OUTPUT;        
-	reg_mprj_io_23 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_24 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_25 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_26 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_27 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_28 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_29 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_30 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_31 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_32 =  GPIO_MODE_USER_STD_OUTPUT;        
-	reg_mprj_io_33 =  GPIO_MODE_USER_STD_OUTPUT;
-
-
+    reg_mprj_io_0 =  GPIO_MODE_USER_STD_OUTPUT;     // prog_we_o
+    reg_mprj_io_1 =  GPIO_MODE_USER_STD_OUTPUT;     // prog_dout
+    reg_mprj_io_2 =  GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_3 =  GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_4 =  GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_5 =  GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_6 =  GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_7 =  GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_8 =  GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_9 =  GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_26 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_27 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_28 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_29 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_30 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_31 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_32 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_33 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+    reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_PULLDOWN; // prog_we
+    reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_PULLDOWN; // prog_rst
+    reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_PULLDOWN; // prog_done
+    reg_mprj_io_35 = GPIO_MODE_USER_STD_INPUT_NOPULL;   // prog_din
+    reg_mprj_io_36 = GPIO_MODE_USER_STD_INPUT_NOPULL;   // clk
+    reg_mprj_io_37 = GPIO_MODE_USER_STD_INPUT_NOPULL;   // prog_clk
         
 	/* Apply configuration */
 	reg_mprj_xfer = 1;
 	while (reg_mprj_xfer == 1);
+
+    // set GPIO to 1 to signal the external bitstream loader
+    reg_gpio_out = 1;
+    reg_gpio_out = 1;
 }
 
diff --git a/verilog/dv/prga/prga_tb.v b/verilog/dv/prga/prga_tb.v
index ca03e76..9f7e95d 100644
--- a/verilog/dv/prga/prga_tb.v
+++ b/verilog/dv/prga/prga_tb.v
@@ -26,13 +26,8 @@
 
 	wire gpio;
 	wire [37:0] mprj_io;
-	wire [7:0] mprj_io_0;
-
-	assign mprj_io_0 = mprj_io[7:0];
-	// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
 
 	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
-	// assign mprj_io[3] = 1'b1;
 
 	// External clock is used by default.  Make this artificially fast for the
 	// simulation.  Normally this would be a slow clock and the digital PLL
@@ -49,10 +44,11 @@
 		$dumpvars(0, prga_tb);
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (25) begin
+		repeat (100) begin
 			repeat (1000) @(posedge clock);
 			// $display("+1000 cycles");
 		end
+
 		$display("%c[1;31m",27);
 		`ifdef GL
 			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
@@ -64,54 +60,27 @@
 	end
 
 	initial begin
-	    // Observe Output pins [7:0]
-		wait(mprj_io_0 == 8'h01);
-		wait(mprj_io_0 == 8'h02);
-		wait(mprj_io_0 == 8'h03);
-		wait(mprj_io_0 == 8'h04);
-		wait(mprj_io_0 == 8'h05);
-		wait(mprj_io_0 == 8'h06);
-		wait(mprj_io_0 == 8'h07);
-		wait(mprj_io_0 == 8'h08);
-		wait(mprj_io_0 == 8'h09);
-		wait(mprj_io_0 == 8'h0A);   
-		wait(mprj_io_0 == 8'hFF);
-		wait(mprj_io_0 == 8'h00);
-		
-		`ifdef GL
-	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
-		`else
-		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
-		`endif
-	    $finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		CSB  <= 1'b1;		// Force CSB high
+		RSTB = 1'b0;
+		CSB  = 1'b1;		// Force CSB high
 		#2000;
-		RSTB <= 1'b1;	    	// Release reset
+		RSTB = 1'b1;	    	// Release reset
 		#300000;
 		CSB = 1'b0;		// CSB can be released
 	end
 
 	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		power3 <= 1'b0;
-		power4 <= 1'b0;
+		power1 = 1'b0;
+		power2 = 1'b0;
+		power3 = 1'b0;
+		power4 = 1'b0;
 		#100;
-		power1 <= 1'b1;
+		power1 = 1'b1;
 		#100;
-		power2 <= 1'b1;
+		power2 = 1'b1;
 		#100;
-		power3 <= 1'b1;
+		power3 = 1'b1;
 		#100;
-		power4 <= 1'b1;
-	end
-
-	always @(mprj_io) begin
-		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+		power4 = 1'b1;
 	end
 
 	wire flash_csb;
@@ -167,5 +136,101 @@
 		.io3()			// not used
 	);
 
+    // -----------------------------------------------------------------------
+    // -- PRGA Testing -------------------------------------------------------
+    // -----------------------------------------------------------------------
+    wire f_tb_rst;
+    assign f_tb_rst = CSB || !gpio;
+
+    wire w_tb_pass, w_tb_fail, w_tb_prog_done;
+    assign w_tb_prog_done = 1'b1;
+
+    // Logging
+    wire [31:0] f_tb_verbosity;
+    reg [31:0] f_tb_cycle_cnt;
+
+    assign f_tb_verbosity = 1;
+
+    always @(posedge clock) begin
+        if (f_tb_rst) begin
+            f_tb_cycle_cnt <= 0;
+        end else begin
+            f_tb_cycle_cnt <= f_tb_cycle_cnt + 1;
+
+            if (w_tb_fail) begin
+                $display();
+                $display("[INFO] ++=========================++");
+                $display("[INFO] ||       TEST FAILED       ||");
+                $display("[INFO] ++=========================++");
+                $display();
+                $finish;
+            end else if (w_tb_pass) begin
+                $display();
+                $display("[INFO] ++=========================++");
+                $display("[INFO] ||       TEST PASSED       ||");
+                $display("[INFO] ++=========================++");
+                $display();
+                $finish;
+            end
+        end
+    end
+
+    // -- Test ---------------------------------------------------------------
+    // Signals
+    wire w_test_clk;
+    wire w_test_reset;
+    wire w_test_start;
+    wire [3:0] w_test_bcd1;
+    wire [3:0] w_test_bcd0;
+    wire w_test_ready;
+    wire w_test_done_tick;
+    wire [6:0] w_test_bin;
+
+    // Tester
+    basic i_tester (
+        .tb_clk(clock)
+        ,.tb_rst(f_tb_rst)
+        ,.tb_pass(w_tb_pass)
+        ,.tb_fail(w_tb_fail)
+        ,.tb_prog_done(w_tb_prog_done)
+        ,.tb_verbosity(f_tb_verbosity)
+        ,.tb_cycle_cnt(f_tb_cycle_cnt)
+        ,.clk(w_test_clk)
+        ,.reset(w_test_reset)
+        ,.start(w_test_start)
+        ,.bcd1(w_test_bcd1)
+        ,.bcd0(w_test_bcd0)
+        ,.ready(w_test_ready)
+        ,.done_tick(w_test_done_tick)
+        ,.bin(w_test_bin)
+        );
+
+    // -- Behavioral Model ---------------------------------------------------
+    // Signals
+    wire w_behav_ready;
+    wire w_behav_done_tick;
+    wire [6:0] w_behav_bin;
+
+    // DUT
+    bcd2bin i_behav (
+        .clk(w_test_clk)
+        ,.reset(w_test_reset)
+        ,.start(w_test_start)
+        ,.bcd1(w_test_bcd1)
+        ,.bcd0(w_test_bcd0)
+        ,.ready(w_behav_ready)
+        ,.done_tick(w_behav_done_tick)
+        ,.bin(w_behav_bin)
+        );
+
+    // -- Bitstream Loading --------------------------------------------------
+
+    // -----------------------------------------------------------------------
+    // -- Wiring -------------------------------------------------------------
+    // -----------------------------------------------------------------------
+    assign w_test_ready = w_behav_ready;
+    assign w_test_done_tick = w_behav_done_tick;
+    assign w_test_bin = w_behav_bin;
+
 endmodule
 `default_nettype wire
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 017a499..057647f 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -58,15 +58,13 @@
  wire prog_we_o;
  wire prog_dout;
 
- top dut (.ipin_x0y1_0(user_clock2),
-    .ipin_x0y1_1(io_in[33]),
-    .ipin_x0y2_0(io_in[32]),
-    .ipin_x0y2_1(io_in[31]),
-    .ipin_x0y3_0(io_in[30]),
-    .ipin_x0y4_0(io_in[29]),
-    .ipin_x0y5_0(io_in[28]),
-    .ipin_x0y6_0(io_in[27]),
-    .ipin_x0y6_1(io_in[26]),
+ top dut (.ipin_x0y1_0(io_in[36]),
+    .ipin_x0y1_1(io_in[31]),
+    .ipin_x0y2_0(io_in[30]),
+    .ipin_x0y3_0(io_in[29]),
+    .ipin_x0y4_0(io_in[28]),
+    .ipin_x0y5_0(io_in[27]),
+    .ipin_x0y6_0(io_in[26]),
     .ipin_x0y7_0(io_in[25]),
     .ipin_x0y8_0(io_in[24]),
     .ipin_x1y9_0(io_in[23]),
@@ -77,27 +75,26 @@
     .ipin_x5y9_0(io_in[18]),
     .ipin_x6y9_0(io_in[17]),
     .ipin_x7y9_0(io_in[16]),
-    .ipin_x7y9_1(io_in[15]),
-    .ipin_x8y9_1(io_in[14]),
-    .ipin_x9y1_0(io_in[3]),
+    .ipin_x8y9_1(io_in[15]),
+    .ipin_x9y1_0(io_in[2]),
+    .ipin_x9y1_1(io_in[3]),
     .ipin_x9y2_0(io_in[4]),
     .ipin_x9y2_1(io_in[5]),
     .ipin_x9y3_0(io_in[6]),
-    .ipin_x9y4_0(io_in[7]),
-    .ipin_x9y5_0(io_in[8]),
-    .ipin_x9y5_1(io_in[9]),
-    .ipin_x9y6_0(io_in[10]),
-    .ipin_x9y7_0(io_in[11]),
-    .ipin_x9y7_1(io_in[12]),
-    .ipin_x9y8_0(io_in[13]),
-    .oe_x0y1_1(io_oeb[33]),
-    .oe_x0y2_0(io_oeb[32]),
-    .oe_x0y2_1(io_oeb[31]),
-    .oe_x0y3_0(io_oeb[30]),
-    .oe_x0y4_0(io_oeb[29]),
-    .oe_x0y5_0(io_oeb[28]),
-    .oe_x0y6_0(io_oeb[27]),
-    .oe_x0y6_1(io_oeb[26]),
+    .ipin_x9y3_1(io_in[7]),
+    .ipin_x9y4_0(io_in[8]),
+    .ipin_x9y5_0(io_in[9]),
+    .ipin_x9y5_1(io_in[10]),
+    .ipin_x9y6_0(io_in[11]),
+    .ipin_x9y7_0(io_in[12]),
+    .ipin_x9y7_1(io_in[13]),
+    .ipin_x9y8_0(io_in[14]),
+    .oe_x0y1_1(io_oeb[31]),
+    .oe_x0y2_0(io_oeb[30]),
+    .oe_x0y3_0(io_oeb[29]),
+    .oe_x0y4_0(io_oeb[28]),
+    .oe_x0y5_0(io_oeb[27]),
+    .oe_x0y6_0(io_oeb[26]),
     .oe_x0y7_0(io_oeb[25]),
     .oe_x0y8_0(io_oeb[24]),
     .oe_x1y9_0(io_oeb[23]),
@@ -108,27 +105,26 @@
     .oe_x5y9_0(io_oeb[18]),
     .oe_x6y9_0(io_oeb[17]),
     .oe_x7y9_0(io_oeb[16]),
-    .oe_x7y9_1(io_oeb[15]),
-    .oe_x8y9_1(io_oeb[14]),
-    .oe_x9y1_0(io_oeb[3]),
+    .oe_x8y9_1(io_oeb[15]),
+    .oe_x9y1_0(io_oeb[2]),
+    .oe_x9y1_1(io_oeb[3]),
     .oe_x9y2_0(io_oeb[4]),
     .oe_x9y2_1(io_oeb[5]),
     .oe_x9y3_0(io_oeb[6]),
-    .oe_x9y4_0(io_oeb[7]),
-    .oe_x9y5_0(io_oeb[8]),
-    .oe_x9y5_1(io_oeb[9]),
-    .oe_x9y6_0(io_oeb[10]),
-    .oe_x9y7_0(io_oeb[11]),
-    .oe_x9y7_1(io_oeb[12]),
-    .oe_x9y8_0(io_oeb[13]),
-    .opin_x0y1_1(io_out[33]),
-    .opin_x0y2_0(io_out[32]),
-    .opin_x0y2_1(io_out[31]),
-    .opin_x0y3_0(io_out[30]),
-    .opin_x0y4_0(io_out[29]),
-    .opin_x0y5_0(io_out[28]),
-    .opin_x0y6_0(io_out[27]),
-    .opin_x0y6_1(io_out[26]),
+    .oe_x9y3_1(io_oeb[7]),
+    .oe_x9y4_0(io_oeb[8]),
+    .oe_x9y5_0(io_oeb[9]),
+    .oe_x9y5_1(io_oeb[10]),
+    .oe_x9y6_0(io_oeb[11]),
+    .oe_x9y7_0(io_oeb[12]),
+    .oe_x9y7_1(io_oeb[13]),
+    .oe_x9y8_0(io_oeb[14]),
+    .opin_x0y1_1(io_out[31]),
+    .opin_x0y2_0(io_out[30]),
+    .opin_x0y3_0(io_out[29]),
+    .opin_x0y4_0(io_out[28]),
+    .opin_x0y5_0(io_out[27]),
+    .opin_x0y6_0(io_out[26]),
     .opin_x0y7_0(io_out[25]),
     .opin_x0y8_0(io_out[24]),
     .opin_x1y9_0(io_out[23]),
@@ -139,36 +135,41 @@
     .opin_x5y9_0(io_out[18]),
     .opin_x6y9_0(io_out[17]),
     .opin_x7y9_0(io_out[16]),
-    .opin_x7y9_1(io_out[15]),
-    .opin_x8y9_1(io_out[14]),
-    .opin_x9y1_0(io_out[3]),
+    .opin_x8y9_1(io_out[15]),
+    .opin_x9y1_0(io_out[2]),
+    .opin_x9y1_1(io_out[3]),
     .opin_x9y2_0(io_out[4]),
     .opin_x9y2_1(io_out[5]),
     .opin_x9y3_0(io_out[6]),
-    .opin_x9y4_0(io_out[7]),
-    .opin_x9y5_0(io_out[8]),
-    .opin_x9y5_1(io_out[9]),
-    .opin_x9y6_0(io_out[10]),
-    .opin_x9y7_0(io_out[11]),
-    .opin_x9y7_1(io_out[12]),
-    .opin_x9y8_0(io_out[13]),
-    .prog_clk(user_clock2),
-    .prog_din(io_in[37]),
-    .prog_done(io_in[36]),
+    .opin_x9y3_1(io_out[7]),
+    .opin_x9y4_0(io_out[8]),
+    .opin_x9y5_0(io_out[9]),
+    .opin_x9y5_1(io_out[10]),
+    .opin_x9y6_0(io_out[11]),
+    .opin_x9y7_0(io_out[12]),
+    .opin_x9y7_1(io_out[13]),
+    .opin_x9y8_0(io_out[14]),
+    .prog_clk(io_in[37]),
+    .prog_din(io_in[35]),
+    .prog_done(io_in[34]),
     .prog_dout(prog_dout),
-    .prog_rst(io_in[35]),
-    .prog_we(io_in[34]),
+    .prog_rst(io_in[33]),
+    .prog_we(io_in[32]),
     .prog_we_o(prog_we_o),
     .vccd1(vccd1),
     .vssd1(vssd1));
  assign io_oeb[0] = one_;
  assign io_oeb[1] = one_;
+ assign io_oeb[32] = zero_;
+ assign io_oeb[33] = zero_;
  assign io_oeb[34] = zero_;
  assign io_oeb[35] = zero_;
  assign io_oeb[36] = zero_;
  assign io_oeb[37] = zero_;
  assign io_out[0] = prog_we_o;
  assign io_out[1] = prog_dout;
+ assign io_out[32] = zero_;
+ assign io_out[33] = zero_;
  assign io_out[34] = zero_;
  assign io_out[35] = zero_;
  assign io_out[36] = zero_;