diff --git a/verilog/dv/prga/Makefile b/verilog/dv/prga/Makefile
new file mode 100644
index 0000000..3fd0b56
--- /dev/null
+++ b/verilog/dv/prga/Makefile
@@ -0,0 +1,32 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+ 
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+
+
diff --git a/verilog/dv/prga/prga.c b/verilog/dv/prga/prga.c
new file mode 100644
index 0000000..c316f0d
--- /dev/null
+++ b/verilog/dv/prga/prga.c
@@ -0,0 +1,103 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+/*
+	IO Test:
+		- Configures MPRJ lower 8-IO pins as outputs
+		- Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
+*/
+
+void main()
+{
+	/* 
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+	
+	 
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+
+	*/
+
+	/* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+	// reg_spi_enable = 1;
+	// reg_spimaster_cs = 0x10001;
+	// reg_spimaster_control = 0x0801;
+
+	// reg_spimaster_control = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+	// Configure lower 8-IOs as user output
+	// Observe counter value in the testbench
+	//reg_mprj_io_0 =  GPIO_MODE_USER_STD_OUTPUT;
+	//reg_mprj_io_1 =  GPIO_MODE_USER_STD_OUTPUT;
+	//reg_mprj_io_2 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_3 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_4 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_5 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_6 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_7 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_8 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_9 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_10 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_11 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_12 =  GPIO_MODE_USER_STD_OUTPUT;        
+	reg_mprj_io_13 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_14 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_15 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_16 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_17 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_18 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_19 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_20 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_21 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_22 =  GPIO_MODE_USER_STD_OUTPUT;        
+	reg_mprj_io_23 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_24 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_25 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_26 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_27 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_28 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_29 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_30 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_31 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_32 =  GPIO_MODE_USER_STD_OUTPUT;        
+	reg_mprj_io_33 =  GPIO_MODE_USER_STD_OUTPUT;
+
+
+        
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+}
+
diff --git a/verilog/dv/prga/prga_tb.v b/verilog/dv/prga/prga_tb.v
new file mode 100644
index 0000000..ca03e76
--- /dev/null
+++ b/verilog/dv/prga/prga_tb.v
@@ -0,0 +1,171 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+module prga_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+	reg power3, power4;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+
+	assign mprj_io_0 = mprj_io[7:0];
+	// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
+
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+	// assign mprj_io[3] = 1'b1;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("prga.vcd");
+		$dumpvars(0, prga_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (25) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+	    // Observe Output pins [7:0]
+		wait(mprj_io_0 == 8'h01);
+		wait(mprj_io_0 == 8'h02);
+		wait(mprj_io_0 == 8'h03);
+		wait(mprj_io_0 == 8'h04);
+		wait(mprj_io_0 == 8'h05);
+		wait(mprj_io_0 == 8'h06);
+		wait(mprj_io_0 == 8'h07);
+		wait(mprj_io_0 == 8'h08);
+		wait(mprj_io_0 == 8'h09);
+		wait(mprj_io_0 == 8'h0A);   
+		wait(mprj_io_0 == 8'hFF);
+		wait(mprj_io_0 == 8'h00);
+		
+		`ifdef GL
+	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
+		`else
+		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
+		`endif
+	    $finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#300000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		power3 <= 1'b0;
+		power4 <= 1'b0;
+		#100;
+		power1 <= 1'b1;
+		#100;
+		power2 <= 1'b1;
+		#100;
+		power3 <= 1'b1;
+		#100;
+		power4 <= 1'b1;
+	end
+
+	always @(mprj_io) begin
+		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+	end
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+	
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vddio_2  (VDD3V3),
+		.vssio	  (VSS),
+		.vssio_2  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda1_2  (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa1_2  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock    (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("prga.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 31ab09b..29e120f 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,5 +1,4 @@
 # Caravel user project includes
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
--v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
-
- 
\ No newline at end of file
+-v $(USER_PROJECT_VERILOG)/rtl/top.pickled.v
+-v $(USER_PROJECT_VERILOG)/rtl/tile_clb.pickled.reduced.v
diff --git a/verilog/rtl/tile_clb.pickled.reduced.v b/verilog/rtl/tile_clb.pickled.reduced.v
new file mode 100644
index 0000000..547d788
--- /dev/null
+++ b/verilog/rtl/tile_clb.pickled.reduced.v
@@ -0,0 +1,1813 @@
+// SPDX-FileCopyrightText: (c) 2022 Princeton University
+// SPDX-License-Identifier: BSD-3-Clause
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright notice, this
+//    list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright notice,
+//    this list of conditions and the following disclaimer in the documentation
+//    and/or other materials provided with the distribution.
+//
+// 3. Neither the name of the copyright holder nor the names of its
+//    contributors may be used to endorse or promote products derived from
+//    this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+// Automatically generated by PRGA's RTL generator
+module tile_clb (
+`ifdef USE_POWER_PINS
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
+`endif
+    output wire [11:0] cu_x0y0n_L1
+    , output wire [11:0] cu_x0y0s_L1
+    , input wire [11:0] bi_u1y0n_L1
+    , input wire [11:0] bi_u1y0s_L1
+    , input wire [0:0] clk
+    , input wire [0:0] prog_clk
+    , input wire [0:0] prog_rst
+    , input wire [0:0] prog_done
+    , input wire [0:0] prog_we
+    , input wire [0:0] prog_din
+    , output wire [0:0] prog_dout
+    , output wire [0:0] prog_we_o
+    );
+    
+        
+    wire [7:0] _i_blk__out;
+    wire [0:0] _i_blk__prog_dout;
+    wire [0:0] _i_blk__prog_we_o;
+    wire [11:0] _i_cbox_e0__cu_x0y0n_L1;
+    wire [11:0] _i_cbox_e0__cu_x0y0s_L1;
+    wire [0:0] _i_cbox_e0__prog_dout;
+    wire [0:0] _i_cbox_e0__prog_we_o;
+    wire [15:0] _i_cbox_w0__bp_x0y0i0_in;
+    wire [0:0] _i_cbox_w0__prog_dout;
+    wire [0:0] _i_cbox_w0__prog_we_o;
+    wire [0:0] _i_buf_prog_rst_l0__Q;
+    wire [0:0] _i_buf_prog_done_l0__Q;
+    wire [0:0] _i_buf_prog_rst_l1__Q;
+    wire [0:0] _i_buf_prog_done_l1__Q;
+        
+    clb i_blk (
+        .clk(clk)
+        ,.in(_i_cbox_w0__bp_x0y0i0_in)
+        ,.out(_i_blk__out)
+        ,.prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l1__Q)
+        ,.prog_done(_i_buf_prog_done_l1__Q)
+        ,.prog_we(prog_we)
+        ,.prog_din(prog_din)
+        ,.prog_dout(_i_blk__prog_dout)
+        ,.prog_we_o(_i_blk__prog_we_o)
+        );
+    cbox_tile_clb_e0 i_cbox_e0 (
+        .bp_x0y0i0_out(_i_blk__out)
+        ,.cu_x0y0n_L1(_i_cbox_e0__cu_x0y0n_L1)
+        ,.cu_x0y0s_L1(_i_cbox_e0__cu_x0y0s_L1)
+        ,.prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l1__Q)
+        ,.prog_done(_i_buf_prog_done_l1__Q)
+        ,.prog_we(_i_blk__prog_we_o)
+        ,.prog_din(_i_blk__prog_dout)
+        ,.prog_dout(_i_cbox_e0__prog_dout)
+        ,.prog_we_o(_i_cbox_e0__prog_we_o)
+        );
+    cbox_tile_clb_w0 i_cbox_w0 (
+        .bp_x0y0i0_in(_i_cbox_w0__bp_x0y0i0_in)
+        ,.bi_u1y0n_L1(bi_u1y0n_L1)
+        ,.bi_u1y0s_L1(bi_u1y0s_L1)
+        ,.prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l1__Q)
+        ,.prog_done(_i_buf_prog_done_l1__Q)
+        ,.prog_we(_i_cbox_e0__prog_we_o)
+        ,.prog_din(_i_cbox_e0__prog_dout)
+        ,.prog_dout(_i_cbox_w0__prog_dout)
+        ,.prog_we_o(_i_cbox_w0__prog_we_o)
+        );
+    prga_simple_buf i_buf_prog_rst_l0 (
+        .C(prog_clk)
+        ,.D(_i_buf_prog_rst_l1__Q)
+        ,.Q(_i_buf_prog_rst_l0__Q)
+        );
+    prga_simple_bufr i_buf_prog_done_l0 (
+        .C(prog_clk)
+        ,.R(_i_buf_prog_rst_l0__Q)
+        ,.D(_i_buf_prog_done_l1__Q)
+        ,.Q(_i_buf_prog_done_l0__Q)
+        );
+    prga_simple_buf i_buf_prog_rst_l1 (
+        .C(prog_clk)
+        ,.D(prog_rst)
+        ,.Q(_i_buf_prog_rst_l1__Q)
+        );
+    prga_simple_bufr i_buf_prog_done_l1 (
+        .C(prog_clk)
+        ,.R(_i_buf_prog_rst_l0__Q)
+        ,.D(prog_done)
+        ,.Q(_i_buf_prog_done_l1__Q)
+        );
+        
+    assign cu_x0y0n_L1 = _i_cbox_e0__cu_x0y0n_L1;
+    assign cu_x0y0s_L1 = _i_cbox_e0__cu_x0y0s_L1;
+    assign prog_dout = _i_cbox_w0__prog_dout;
+    assign prog_we_o = _i_cbox_w0__prog_we_o;
+
+endmodule
+// Automatically generated by PRGA's RTL generator
+module clb (
+    input wire [0:0] clk
+    , input wire [15:0] in
+    , output wire [7:0] out
+    , input wire [0:0] prog_clk
+    , input wire [0:0] prog_rst
+    , input wire [0:0] prog_done
+    , input wire [0:0] prog_we
+    , input wire [0:0] prog_din
+    , output wire [0:0] prog_dout
+    , output wire [0:0] prog_we_o
+    );
+    
+        
+    wire [0:0] _cluster_i0__o;
+    wire [0:0] _cluster_i0__prog_dout;
+    wire [0:0] _cluster_i1__o;
+    wire [0:0] _cluster_i1__prog_dout;
+    wire [0:0] _cluster_i2__o;
+    wire [0:0] _cluster_i2__prog_dout;
+    wire [0:0] _cluster_i3__o;
+    wire [0:0] _cluster_i3__prog_dout;
+    wire [0:0] _cluster_i4__o;
+    wire [0:0] _cluster_i4__prog_dout;
+    wire [0:0] _cluster_i5__o;
+    wire [0:0] _cluster_i5__prog_dout;
+    wire [0:0] _cluster_i6__o;
+    wire [0:0] _cluster_i6__prog_dout;
+    wire [0:0] _cluster_i7__o;
+    wire [0:0] _cluster_i7__prog_dout;
+    wire [0:0] _i_sw_cluster_i0_i_0__o;
+    wire [0:0] _i_sw_cluster_i0_i_1__o;
+    wire [0:0] _i_sw_cluster_i0_i_2__o;
+    wire [0:0] _i_sw_cluster_i0_i_3__o;
+    wire [0:0] _i_sw_cluster_i1_i_0__o;
+    wire [0:0] _i_sw_cluster_i1_i_1__o;
+    wire [0:0] _i_sw_cluster_i1_i_2__o;
+    wire [0:0] _i_sw_cluster_i1_i_3__o;
+    wire [0:0] _i_sw_cluster_i2_i_0__o;
+    wire [0:0] _i_sw_cluster_i2_i_1__o;
+    wire [0:0] _i_sw_cluster_i2_i_2__o;
+    wire [0:0] _i_sw_cluster_i2_i_3__o;
+    wire [0:0] _i_sw_cluster_i3_i_0__o;
+    wire [0:0] _i_sw_cluster_i3_i_1__o;
+    wire [0:0] _i_sw_cluster_i3_i_2__o;
+    wire [0:0] _i_sw_cluster_i3_i_3__o;
+    wire [0:0] _i_sw_cluster_i4_i_0__o;
+    wire [0:0] _i_sw_cluster_i4_i_1__o;
+    wire [0:0] _i_sw_cluster_i4_i_2__o;
+    wire [0:0] _i_sw_cluster_i4_i_3__o;
+    wire [0:0] _i_sw_cluster_i5_i_0__o;
+    wire [0:0] _i_sw_cluster_i5_i_1__o;
+    wire [0:0] _i_sw_cluster_i5_i_2__o;
+    wire [0:0] _i_sw_cluster_i5_i_3__o;
+    wire [0:0] _i_sw_cluster_i6_i_0__o;
+    wire [0:0] _i_sw_cluster_i6_i_1__o;
+    wire [0:0] _i_sw_cluster_i6_i_2__o;
+    wire [0:0] _i_sw_cluster_i6_i_3__o;
+    wire [0:0] _i_sw_cluster_i7_i_0__o;
+    wire [0:0] _i_sw_cluster_i7_i_1__o;
+    wire [0:0] _i_sw_cluster_i7_i_2__o;
+    wire [0:0] _i_sw_cluster_i7_i_3__o;
+    wire [0:0] _i_buf_prog_rst_l0__Q;
+    wire [0:0] _i_buf_prog_done_l0__Q;
+    wire [0:0] _i_scanchain_head__prog_dout;
+    wire [0:0] _i_scanchain_head__prog_we_o;
+    wire [0:0] _i_prog_data_i_sw_cluster_i0_i_0__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i0_i_0__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i0_i_1__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i0_i_1__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i0_i_2__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i0_i_2__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i0_i_3__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i0_i_3__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i1_i_0__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i1_i_0__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i1_i_1__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i1_i_1__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i1_i_2__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i1_i_2__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i1_i_3__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i1_i_3__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i2_i_0__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i2_i_0__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i2_i_1__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i2_i_1__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i2_i_2__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i2_i_2__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i2_i_3__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i2_i_3__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i3_i_0__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i3_i_0__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i3_i_1__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i3_i_1__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i3_i_2__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i3_i_2__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i3_i_3__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i3_i_3__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i4_i_0__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i4_i_0__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i4_i_1__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i4_i_1__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i4_i_2__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i4_i_2__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i4_i_3__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i4_i_3__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i5_i_0__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i5_i_0__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i5_i_1__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i5_i_1__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i5_i_2__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i5_i_2__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i5_i_3__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i5_i_3__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i6_i_0__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i6_i_0__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i6_i_1__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i6_i_1__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i6_i_2__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i6_i_2__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i6_i_3__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i6_i_3__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i7_i_0__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i7_i_0__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i7_i_1__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i7_i_1__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i7_i_2__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i7_i_2__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cluster_i7_i_3__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cluster_i7_i_3__prog_data;
+    wire [0:0] _i_scanchain_tail__prog_dout;
+    wire [0:0] _i_scanchain_tail__prog_we_o;
+        
+    slice cluster_i0 (
+        .clk(clk)
+        ,.i({_i_sw_cluster_i0_i_3__o,
+            _i_sw_cluster_i0_i_2__o,
+            _i_sw_cluster_i0_i_1__o,
+            _i_sw_cluster_i0_i_0__o})
+        ,.o(_cluster_i0__o)
+        ,.prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_scanchain_head__prog_dout)
+        ,.prog_dout(_cluster_i0__prog_dout)
+        );
+    slice cluster_i1 (
+        .clk(clk)
+        ,.i({_i_sw_cluster_i1_i_3__o,
+            _i_sw_cluster_i1_i_2__o,
+            _i_sw_cluster_i1_i_1__o,
+            _i_sw_cluster_i1_i_0__o})
+        ,.o(_cluster_i1__o)
+        ,.prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_cluster_i0__prog_dout)
+        ,.prog_dout(_cluster_i1__prog_dout)
+        );
+    slice cluster_i2 (
+        .clk(clk)
+        ,.i({_i_sw_cluster_i2_i_3__o,
+            _i_sw_cluster_i2_i_2__o,
+            _i_sw_cluster_i2_i_1__o,
+            _i_sw_cluster_i2_i_0__o})
+        ,.o(_cluster_i2__o)
+        ,.prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_cluster_i1__prog_dout)
+        ,.prog_dout(_cluster_i2__prog_dout)
+        );
+    slice cluster_i3 (
+        .clk(clk)
+        ,.i({_i_sw_cluster_i3_i_3__o,
+            _i_sw_cluster_i3_i_2__o,
+            _i_sw_cluster_i3_i_1__o,
+            _i_sw_cluster_i3_i_0__o})
+        ,.o(_cluster_i3__o)
+        ,.prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_cluster_i2__prog_dout)
+        ,.prog_dout(_cluster_i3__prog_dout)
+        );
+    slice cluster_i4 (
+        .clk(clk)
+        ,.i({_i_sw_cluster_i4_i_3__o,
+            _i_sw_cluster_i4_i_2__o,
+            _i_sw_cluster_i4_i_1__o,
+            _i_sw_cluster_i4_i_0__o})
+        ,.o(_cluster_i4__o)
+        ,.prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_cluster_i3__prog_dout)
+        ,.prog_dout(_cluster_i4__prog_dout)
+        );
+    slice cluster_i5 (
+        .clk(clk)
+        ,.i({_i_sw_cluster_i5_i_3__o,
+            _i_sw_cluster_i5_i_2__o,
+            _i_sw_cluster_i5_i_1__o,
+            _i_sw_cluster_i5_i_0__o})
+        ,.o(_cluster_i5__o)
+        ,.prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_cluster_i4__prog_dout)
+        ,.prog_dout(_cluster_i5__prog_dout)
+        );
+    slice cluster_i6 (
+        .clk(clk)
+        ,.i({_i_sw_cluster_i6_i_3__o,
+            _i_sw_cluster_i6_i_2__o,
+            _i_sw_cluster_i6_i_1__o,
+            _i_sw_cluster_i6_i_0__o})
+        ,.o(_cluster_i6__o)
+        ,.prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_cluster_i5__prog_dout)
+        ,.prog_dout(_cluster_i6__prog_dout)
+        );
+    slice cluster_i7 (
+        .clk(clk)
+        ,.i({_i_sw_cluster_i7_i_3__o,
+            _i_sw_cluster_i7_i_2__o,
+            _i_sw_cluster_i7_i_1__o,
+            _i_sw_cluster_i7_i_0__o})
+        ,.o(_cluster_i7__o)
+        ,.prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_cluster_i6__prog_dout)
+        ,.prog_dout(_cluster_i7__prog_dout)
+        );
+    sw3 i_sw_cluster_i0_i_0 (
+        .i({_cluster_i0__o,
+            in[8],
+            in[0]})
+        ,.o(_i_sw_cluster_i0_i_0__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i0_i_0__prog_data)
+        );
+    sw3 i_sw_cluster_i0_i_1 (
+        .i({_cluster_i2__o,
+            in[10],
+            in[2]})
+        ,.o(_i_sw_cluster_i0_i_1__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i0_i_1__prog_data)
+        );
+    sw3 i_sw_cluster_i0_i_2 (
+        .i({_cluster_i4__o,
+            in[12],
+            in[4]})
+        ,.o(_i_sw_cluster_i0_i_2__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i0_i_2__prog_data)
+        );
+    sw3 i_sw_cluster_i0_i_3 (
+        .i({_cluster_i6__o,
+            in[14],
+            in[6]})
+        ,.o(_i_sw_cluster_i0_i_3__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i0_i_3__prog_data)
+        );
+    sw3 i_sw_cluster_i1_i_0 (
+        .i({_cluster_i1__o,
+            in[9],
+            in[1]})
+        ,.o(_i_sw_cluster_i1_i_0__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i1_i_0__prog_data)
+        );
+    sw3 i_sw_cluster_i1_i_1 (
+        .i({_cluster_i4__o,
+            in[11],
+            in[3]})
+        ,.o(_i_sw_cluster_i1_i_1__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i1_i_1__prog_data)
+        );
+    sw3 i_sw_cluster_i1_i_2 (
+        .i({_cluster_i5__o,
+            in[13],
+            in[5]})
+        ,.o(_i_sw_cluster_i1_i_2__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i1_i_2__prog_data)
+        );
+    sw3 i_sw_cluster_i1_i_3 (
+        .i({_cluster_i7__o,
+            in[15],
+            in[8]})
+        ,.o(_i_sw_cluster_i1_i_3__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i1_i_3__prog_data)
+        );
+    sw3 i_sw_cluster_i2_i_0 (
+        .i({_cluster_i0__o,
+            in[7],
+            in[0]})
+        ,.o(_i_sw_cluster_i2_i_0__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i2_i_0__prog_data)
+        );
+    sw3 i_sw_cluster_i2_i_1 (
+        .i({_cluster_i2__o,
+            in[10],
+            in[2]})
+        ,.o(_i_sw_cluster_i2_i_1__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i2_i_1__prog_data)
+        );
+    sw3 i_sw_cluster_i2_i_2 (
+        .i({_cluster_i3__o,
+            in[12],
+            in[4]})
+        ,.o(_i_sw_cluster_i2_i_2__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i2_i_2__prog_data)
+        );
+    sw3 i_sw_cluster_i2_i_3 (
+        .i({_cluster_i4__o,
+            in[14],
+            in[6]})
+        ,.o(_i_sw_cluster_i2_i_3__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i2_i_3__prog_data)
+        );
+    sw3 i_sw_cluster_i3_i_0 (
+        .i({_cluster_i0__o,
+            in[9],
+            in[1]})
+        ,.o(_i_sw_cluster_i3_i_0__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i3_i_0__prog_data)
+        );
+    sw3 i_sw_cluster_i3_i_1 (
+        .i({_cluster_i1__o,
+            in[11],
+            in[3]})
+        ,.o(_i_sw_cluster_i3_i_1__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i3_i_1__prog_data)
+        );
+    sw3 i_sw_cluster_i3_i_2 (
+        .i({_cluster_i5__o,
+            in[13],
+            in[5]})
+        ,.o(_i_sw_cluster_i3_i_2__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i3_i_2__prog_data)
+        );
+    sw3 i_sw_cluster_i3_i_3 (
+        .i({_cluster_i6__o,
+            in[15],
+            in[8]})
+        ,.o(_i_sw_cluster_i3_i_3__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i3_i_3__prog_data)
+        );
+    sw3 i_sw_cluster_i4_i_0 (
+        .i({_cluster_i2__o,
+            in[7],
+            in[0]})
+        ,.o(_i_sw_cluster_i4_i_0__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i4_i_0__prog_data)
+        );
+    sw3 i_sw_cluster_i4_i_1 (
+        .i({_cluster_i3__o,
+            in[9],
+            in[2]})
+        ,.o(_i_sw_cluster_i4_i_1__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i4_i_1__prog_data)
+        );
+    sw3 i_sw_cluster_i4_i_2 (
+        .i({_cluster_i4__o,
+            in[12],
+            in[4]})
+        ,.o(_i_sw_cluster_i4_i_2__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i4_i_2__prog_data)
+        );
+    sw3 i_sw_cluster_i4_i_3 (
+        .i({_cluster_i6__o,
+            in[14],
+            in[6]})
+        ,.o(_i_sw_cluster_i4_i_3__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i4_i_3__prog_data)
+        );
+    sw3 i_sw_cluster_i5_i_0 (
+        .i({_cluster_i2__o,
+            in[10],
+            in[3]})
+        ,.o(_i_sw_cluster_i5_i_0__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i5_i_0__prog_data)
+        );
+    sw3 i_sw_cluster_i5_i_1 (
+        .i({_cluster_i4__o,
+            in[11],
+            in[5]})
+        ,.o(_i_sw_cluster_i5_i_1__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i5_i_1__prog_data)
+        );
+    sw3 i_sw_cluster_i5_i_2 (
+        .i({_cluster_i6__o,
+            in[13],
+            in[6]})
+        ,.o(_i_sw_cluster_i5_i_2__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i5_i_2__prog_data)
+        );
+    sw3 i_sw_cluster_i5_i_3 (
+        .i({_cluster_i7__o,
+            in[15],
+            in[8]})
+        ,.o(_i_sw_cluster_i5_i_3__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i5_i_3__prog_data)
+        );
+    sw3 i_sw_cluster_i6_i_0 (
+        .i({_cluster_i1__o,
+            in[8],
+            in[0]})
+        ,.o(_i_sw_cluster_i6_i_0__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i6_i_0__prog_data)
+        );
+    sw3 i_sw_cluster_i6_i_1 (
+        .i({_cluster_i4__o,
+            in[10],
+            in[1]})
+        ,.o(_i_sw_cluster_i6_i_1__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i6_i_1__prog_data)
+        );
+    sw3 i_sw_cluster_i6_i_2 (
+        .i({_cluster_i5__o,
+            in[12],
+            in[5]})
+        ,.o(_i_sw_cluster_i6_i_2__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i6_i_2__prog_data)
+        );
+    sw3 i_sw_cluster_i6_i_3 (
+        .i({_cluster_i7__o,
+            in[14],
+            in[7]})
+        ,.o(_i_sw_cluster_i6_i_3__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i6_i_3__prog_data)
+        );
+    sw3 i_sw_cluster_i7_i_0 (
+        .i({_cluster_i0__o,
+            in[7],
+            in[0]})
+        ,.o(_i_sw_cluster_i7_i_0__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i7_i_0__prog_data)
+        );
+    sw3 i_sw_cluster_i7_i_1 (
+        .i({_cluster_i1__o,
+            in[11],
+            in[2]})
+        ,.o(_i_sw_cluster_i7_i_1__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i7_i_1__prog_data)
+        );
+    sw3 i_sw_cluster_i7_i_2 (
+        .i({_cluster_i2__o,
+            in[13],
+            in[4]})
+        ,.o(_i_sw_cluster_i7_i_2__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i7_i_2__prog_data)
+        );
+    sw3 i_sw_cluster_i7_i_3 (
+        .i({_cluster_i3__o,
+            in[15],
+            in[5]})
+        ,.o(_i_sw_cluster_i7_i_3__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i7_i_3__prog_data)
+        );
+    prga_simple_buf i_buf_prog_rst_l0 (
+        .C(prog_clk)
+        ,.D(prog_rst)
+        ,.Q(_i_buf_prog_rst_l0__Q)
+        );
+    prga_simple_bufr i_buf_prog_done_l0 (
+        .C(prog_clk)
+        ,.R(_i_buf_prog_rst_l0__Q)
+        ,.D(prog_done)
+        ,.Q(_i_buf_prog_done_l0__Q)
+        );
+    scanchain_delim i_scanchain_head (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(prog_we)
+        ,.prog_din(prog_din)
+        ,.prog_dout(_i_scanchain_head__prog_dout)
+        ,.prog_we_o(_i_scanchain_head__prog_we_o)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i0_i_0 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_cluster_i7__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i0_i_0__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i0_i_0__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i0_i_1 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i0_i_0__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i0_i_1__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i0_i_1__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i0_i_2 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i0_i_1__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i0_i_2__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i0_i_2__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i0_i_3 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i0_i_2__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i0_i_3__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i0_i_3__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i1_i_0 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i0_i_3__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i1_i_0__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i1_i_0__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i1_i_1 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i1_i_0__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i1_i_1__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i1_i_1__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i1_i_2 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i1_i_1__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i1_i_2__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i1_i_2__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i1_i_3 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i1_i_2__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i1_i_3__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i1_i_3__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i2_i_0 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i1_i_3__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i2_i_0__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i2_i_0__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i2_i_1 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i2_i_0__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i2_i_1__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i2_i_1__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i2_i_2 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i2_i_1__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i2_i_2__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i2_i_2__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i2_i_3 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i2_i_2__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i2_i_3__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i2_i_3__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i3_i_0 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i2_i_3__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i3_i_0__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i3_i_0__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i3_i_1 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i3_i_0__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i3_i_1__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i3_i_1__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i3_i_2 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i3_i_1__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i3_i_2__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i3_i_2__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i3_i_3 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i3_i_2__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i3_i_3__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i3_i_3__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i4_i_0 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i3_i_3__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i4_i_0__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i4_i_0__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i4_i_1 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i4_i_0__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i4_i_1__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i4_i_1__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i4_i_2 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i4_i_1__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i4_i_2__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i4_i_2__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i4_i_3 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i4_i_2__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i4_i_3__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i4_i_3__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i5_i_0 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i4_i_3__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i5_i_0__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i5_i_0__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i5_i_1 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i5_i_0__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i5_i_1__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i5_i_1__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i5_i_2 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i5_i_1__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i5_i_2__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i5_i_2__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i5_i_3 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i5_i_2__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i5_i_3__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i5_i_3__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i6_i_0 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i5_i_3__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i6_i_0__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i6_i_0__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i6_i_1 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i6_i_0__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i6_i_1__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i6_i_1__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i6_i_2 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i6_i_1__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i6_i_2__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i6_i_2__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i6_i_3 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i6_i_2__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i6_i_3__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i6_i_3__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i7_i_0 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i6_i_3__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i7_i_0__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i7_i_0__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i7_i_1 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i7_i_0__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i7_i_1__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i7_i_1__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i7_i_2 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i7_i_1__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i7_i_2__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i7_i_2__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cluster_i7_i_3 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i7_i_2__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cluster_i7_i_3__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cluster_i7_i_3__prog_data)
+        );
+    scanchain_delim i_scanchain_tail (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cluster_i7_i_3__prog_dout)
+        ,.prog_dout(_i_scanchain_tail__prog_dout)
+        ,.prog_we_o(_i_scanchain_tail__prog_we_o)
+        );
+        
+    assign out = {_cluster_i7__o,
+        _cluster_i6__o,
+        _cluster_i5__o,
+        _cluster_i4__o,
+        _cluster_i3__o,
+        _cluster_i2__o,
+        _cluster_i1__o,
+        _cluster_i0__o};
+    assign prog_dout = _i_scanchain_tail__prog_dout;
+    assign prog_we_o = _i_scanchain_tail__prog_we_o;
+
+endmodule
+// Automatically generated by PRGA's RTL generator
+module cbox_tile_clb_e0 (
+    input wire [7:0] bp_x0y0i0_out
+    , output wire [11:0] cu_x0y0n_L1
+    , output wire [11:0] cu_x0y0s_L1
+    , input wire [0:0] prog_clk
+    , input wire [0:0] prog_rst
+    , input wire [0:0] prog_done
+    , input wire [0:0] prog_we
+    , input wire [0:0] prog_din
+    , output wire [0:0] prog_dout
+    , output wire [0:0] prog_we_o
+    );
+    
+        
+    wire [0:0] _i_sw_cu_x0y0n_L1_0__o;
+    wire [0:0] _i_sw_cu_x0y0n_L1_2__o;
+    wire [0:0] _i_sw_cu_x0y0n_L1_7__o;
+    wire [0:0] _i_sw_cu_x0y0n_L1_8__o;
+    wire [0:0] _i_sw_cu_x0y0s_L1_0__o;
+    wire [0:0] _i_sw_cu_x0y0s_L1_2__o;
+    wire [0:0] _i_sw_cu_x0y0s_L1_7__o;
+    wire [0:0] _i_sw_cu_x0y0s_L1_8__o;
+    wire [0:0] _i_buf_prog_rst_l0__Q;
+    wire [0:0] _i_buf_prog_done_l0__Q;
+    wire [0:0] _i_scanchain_head__prog_dout;
+    wire [0:0] _i_scanchain_head__prog_we_o;
+    wire [0:0] _i_prog_data_i_sw_cu_x0y0n_L1_0__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cu_x0y0n_L1_0__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cu_x0y0n_L1_2__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cu_x0y0n_L1_2__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cu_x0y0n_L1_7__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cu_x0y0n_L1_7__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cu_x0y0n_L1_8__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cu_x0y0n_L1_8__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cu_x0y0s_L1_0__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cu_x0y0s_L1_0__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cu_x0y0s_L1_2__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cu_x0y0s_L1_2__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cu_x0y0s_L1_7__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cu_x0y0s_L1_7__prog_data;
+    wire [0:0] _i_prog_data_i_sw_cu_x0y0s_L1_8__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_cu_x0y0s_L1_8__prog_data;
+    wire [0:0] _i_scanchain_tail__prog_dout;
+    wire [0:0] _i_scanchain_tail__prog_we_o;
+        
+    sw2 i_sw_cu_x0y0n_L1_0 (
+        .i({bp_x0y0i0_out[7],
+            bp_x0y0i0_out[0]})
+        ,.o(_i_sw_cu_x0y0n_L1_0__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0n_L1_0__prog_data)
+        );
+    sw2 i_sw_cu_x0y0n_L1_2 (
+        .i({bp_x0y0i0_out[6],
+            bp_x0y0i0_out[2]})
+        ,.o(_i_sw_cu_x0y0n_L1_2__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0n_L1_2__prog_data)
+        );
+    sw2 i_sw_cu_x0y0n_L1_7 (
+        .i(bp_x0y0i0_out[7:6])
+        ,.o(_i_sw_cu_x0y0n_L1_7__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0n_L1_7__prog_data)
+        );
+    sw2 i_sw_cu_x0y0n_L1_8 (
+        .i(bp_x0y0i0_out[5:4])
+        ,.o(_i_sw_cu_x0y0n_L1_8__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0n_L1_8__prog_data)
+        );
+    sw2 i_sw_cu_x0y0s_L1_0 (
+        .i({bp_x0y0i0_out[7],
+            bp_x0y0i0_out[0]})
+        ,.o(_i_sw_cu_x0y0s_L1_0__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0s_L1_0__prog_data)
+        );
+    sw2 i_sw_cu_x0y0s_L1_2 (
+        .i({bp_x0y0i0_out[6],
+            bp_x0y0i0_out[2]})
+        ,.o(_i_sw_cu_x0y0s_L1_2__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0s_L1_2__prog_data)
+        );
+    sw2 i_sw_cu_x0y0s_L1_7 (
+        .i(bp_x0y0i0_out[7:6])
+        ,.o(_i_sw_cu_x0y0s_L1_7__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0s_L1_7__prog_data)
+        );
+    sw2 i_sw_cu_x0y0s_L1_8 (
+        .i(bp_x0y0i0_out[5:4])
+        ,.o(_i_sw_cu_x0y0s_L1_8__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0s_L1_8__prog_data)
+        );
+    prga_simple_buf i_buf_prog_rst_l0 (
+        .C(prog_clk)
+        ,.D(prog_rst)
+        ,.Q(_i_buf_prog_rst_l0__Q)
+        );
+    prga_simple_bufr i_buf_prog_done_l0 (
+        .C(prog_clk)
+        ,.R(_i_buf_prog_rst_l0__Q)
+        ,.D(prog_done)
+        ,.Q(_i_buf_prog_done_l0__Q)
+        );
+    scanchain_delim i_scanchain_head (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(prog_we)
+        ,.prog_din(prog_din)
+        ,.prog_dout(_i_scanchain_head__prog_dout)
+        ,.prog_we_o(_i_scanchain_head__prog_we_o)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cu_x0y0n_L1_0 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_scanchain_head__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cu_x0y0n_L1_0__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0n_L1_0__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cu_x0y0n_L1_2 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cu_x0y0n_L1_0__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cu_x0y0n_L1_2__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0n_L1_2__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cu_x0y0n_L1_7 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cu_x0y0n_L1_2__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cu_x0y0n_L1_7__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0n_L1_7__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cu_x0y0n_L1_8 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cu_x0y0n_L1_7__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cu_x0y0n_L1_8__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0n_L1_8__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cu_x0y0s_L1_0 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cu_x0y0n_L1_8__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cu_x0y0s_L1_0__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0s_L1_0__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cu_x0y0s_L1_2 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cu_x0y0s_L1_0__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cu_x0y0s_L1_2__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0s_L1_2__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cu_x0y0s_L1_7 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cu_x0y0s_L1_2__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cu_x0y0s_L1_7__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0s_L1_7__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_cu_x0y0s_L1_8 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cu_x0y0s_L1_7__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_cu_x0y0s_L1_8__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_cu_x0y0s_L1_8__prog_data)
+        );
+    scanchain_delim i_scanchain_tail (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_cu_x0y0s_L1_8__prog_dout)
+        ,.prog_dout(_i_scanchain_tail__prog_dout)
+        ,.prog_we_o(_i_scanchain_tail__prog_we_o)
+        );
+        
+    assign cu_x0y0n_L1 = {bp_x0y0i0_out[1],
+        bp_x0y0i0_out[3:2],
+        _i_sw_cu_x0y0n_L1_8__o,
+        _i_sw_cu_x0y0n_L1_7__o,
+        bp_x0y0i0_out[0],
+        bp_x0y0i0_out[3],
+        bp_x0y0i0_out[1],
+        bp_x0y0i0_out[4],
+        _i_sw_cu_x0y0n_L1_2__o,
+        bp_x0y0i0_out[5],
+        _i_sw_cu_x0y0n_L1_0__o};
+    assign cu_x0y0s_L1 = {bp_x0y0i0_out[1],
+        bp_x0y0i0_out[3:2],
+        _i_sw_cu_x0y0s_L1_8__o,
+        _i_sw_cu_x0y0s_L1_7__o,
+        bp_x0y0i0_out[0],
+        bp_x0y0i0_out[3],
+        bp_x0y0i0_out[1],
+        bp_x0y0i0_out[4],
+        _i_sw_cu_x0y0s_L1_2__o,
+        bp_x0y0i0_out[5],
+        _i_sw_cu_x0y0s_L1_0__o};
+    assign prog_dout = _i_scanchain_tail__prog_dout;
+    assign prog_we_o = _i_scanchain_tail__prog_we_o;
+
+endmodule
+// Automatically generated by PRGA's RTL generator
+module cbox_tile_clb_w0 (
+    output wire [15:0] bp_x0y0i0_in
+    , input wire [11:0] bi_u1y0n_L1
+    , input wire [11:0] bi_u1y0s_L1
+    , input wire [0:0] prog_clk
+    , input wire [0:0] prog_rst
+    , input wire [0:0] prog_done
+    , input wire [0:0] prog_we
+    , input wire [0:0] prog_din
+    , output wire [0:0] prog_dout
+    , output wire [0:0] prog_we_o
+    );
+    
+        
+    wire [0:0] _i_sw_bp_x0y0i0_in_0__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_1__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_2__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_3__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_4__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_5__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_6__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_7__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_8__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_9__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_10__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_11__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_12__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_13__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_14__o;
+    wire [0:0] _i_sw_bp_x0y0i0_in_15__o;
+    wire [0:0] _i_buf_prog_rst_l0__Q;
+    wire [0:0] _i_buf_prog_done_l0__Q;
+    wire [0:0] _i_scanchain_head__prog_dout;
+    wire [0:0] _i_scanchain_head__prog_we_o;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_0__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_0__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_1__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_1__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_2__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_2__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_3__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_3__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_4__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_4__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_5__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_5__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_6__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_6__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_7__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_7__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_8__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_8__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_9__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_9__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_10__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_10__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_11__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_11__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_12__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_12__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_13__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_13__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_14__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_14__prog_data;
+    wire [0:0] _i_prog_data_i_sw_bp_x0y0i0_in_15__prog_dout;
+    wire [2:0] _i_prog_data_i_sw_bp_x0y0i0_in_15__prog_data;
+    wire [0:0] _i_scanchain_tail__prog_dout;
+    wire [0:0] _i_scanchain_tail__prog_we_o;
+        
+    sw6 i_sw_bp_x0y0i0_in_0 (
+        .i({bi_u1y0s_L1[8],
+            bi_u1y0n_L1[8],
+            bi_u1y0s_L1[4],
+            bi_u1y0n_L1[4],
+            bi_u1y0s_L1[0],
+            bi_u1y0n_L1[0]})
+        ,.o(_i_sw_bp_x0y0i0_in_0__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_0__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_1 (
+        .i({bi_u1y0s_L1[11],
+            bi_u1y0n_L1[11],
+            bi_u1y0s_L1[7],
+            bi_u1y0n_L1[7],
+            bi_u1y0s_L1[3],
+            bi_u1y0n_L1[3]})
+        ,.o(_i_sw_bp_x0y0i0_in_1__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_1__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_2 (
+        .i({bi_u1y0s_L1[10],
+            bi_u1y0n_L1[10],
+            bi_u1y0s_L1[6],
+            bi_u1y0n_L1[6],
+            bi_u1y0s_L1[2],
+            bi_u1y0n_L1[2]})
+        ,.o(_i_sw_bp_x0y0i0_in_2__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_2__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_3 (
+        .i({bi_u1y0s_L1[9],
+            bi_u1y0n_L1[9],
+            bi_u1y0s_L1[5],
+            bi_u1y0n_L1[5],
+            bi_u1y0s_L1[1],
+            bi_u1y0n_L1[1]})
+        ,.o(_i_sw_bp_x0y0i0_in_3__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_3__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_4 (
+        .i({bi_u1y0s_L1[9],
+            bi_u1y0n_L1[9],
+            bi_u1y0s_L1[4],
+            bi_u1y0n_L1[4],
+            bi_u1y0s_L1[1],
+            bi_u1y0n_L1[1]})
+        ,.o(_i_sw_bp_x0y0i0_in_4__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_4__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_5 (
+        .i({bi_u1y0s_L1[7],
+            bi_u1y0n_L1[7],
+            bi_u1y0s_L1[3],
+            bi_u1y0n_L1[3],
+            bi_u1y0s_L1[0],
+            bi_u1y0n_L1[0]})
+        ,.o(_i_sw_bp_x0y0i0_in_5__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_5__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_6 (
+        .i({bi_u1y0s_L1[11],
+            bi_u1y0n_L1[11],
+            bi_u1y0s_L1[8],
+            bi_u1y0n_L1[8],
+            bi_u1y0s_L1[5],
+            bi_u1y0n_L1[5]})
+        ,.o(_i_sw_bp_x0y0i0_in_6__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_6__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_7 (
+        .i({bi_u1y0s_L1[10],
+            bi_u1y0n_L1[10],
+            bi_u1y0s_L1[6],
+            bi_u1y0n_L1[6],
+            bi_u1y0s_L1[2],
+            bi_u1y0n_L1[2]})
+        ,.o(_i_sw_bp_x0y0i0_in_7__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_7__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_8 (
+        .i({bi_u1y0s_L1[10],
+            bi_u1y0n_L1[10],
+            bi_u1y0s_L1[5],
+            bi_u1y0n_L1[5],
+            bi_u1y0s_L1[2],
+            bi_u1y0n_L1[2]})
+        ,.o(_i_sw_bp_x0y0i0_in_8__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_8__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_9 (
+        .i({bi_u1y0s_L1[9],
+            bi_u1y0n_L1[9],
+            bi_u1y0s_L1[4],
+            bi_u1y0n_L1[4],
+            bi_u1y0s_L1[1],
+            bi_u1y0n_L1[1]})
+        ,.o(_i_sw_bp_x0y0i0_in_9__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_9__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_10 (
+        .i({bi_u1y0s_L1[7],
+            bi_u1y0n_L1[7],
+            bi_u1y0s_L1[3],
+            bi_u1y0n_L1[3],
+            bi_u1y0s_L1[0],
+            bi_u1y0n_L1[0]})
+        ,.o(_i_sw_bp_x0y0i0_in_10__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_10__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_11 (
+        .i({bi_u1y0s_L1[11],
+            bi_u1y0n_L1[11],
+            bi_u1y0s_L1[8],
+            bi_u1y0n_L1[8],
+            bi_u1y0s_L1[5],
+            bi_u1y0n_L1[5]})
+        ,.o(_i_sw_bp_x0y0i0_in_11__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_11__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_12 (
+        .i({bi_u1y0s_L1[11],
+            bi_u1y0n_L1[11],
+            bi_u1y0s_L1[6],
+            bi_u1y0n_L1[6],
+            bi_u1y0s_L1[3],
+            bi_u1y0n_L1[3]})
+        ,.o(_i_sw_bp_x0y0i0_in_12__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_12__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_13 (
+        .i({bi_u1y0s_L1[9],
+            bi_u1y0n_L1[9],
+            bi_u1y0s_L1[6],
+            bi_u1y0n_L1[6],
+            bi_u1y0s_L1[1],
+            bi_u1y0n_L1[1]})
+        ,.o(_i_sw_bp_x0y0i0_in_13__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_13__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_14 (
+        .i({bi_u1y0s_L1[4],
+            bi_u1y0n_L1[4],
+            bi_u1y0s_L1[2],
+            bi_u1y0n_L1[2],
+            bi_u1y0s_L1[0],
+            bi_u1y0n_L1[0]})
+        ,.o(_i_sw_bp_x0y0i0_in_14__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_14__prog_data)
+        );
+    sw6 i_sw_bp_x0y0i0_in_15 (
+        .i({bi_u1y0s_L1[10],
+            bi_u1y0n_L1[10],
+            bi_u1y0s_L1[8],
+            bi_u1y0n_L1[8],
+            bi_u1y0s_L1[7],
+            bi_u1y0n_L1[7]})
+        ,.o(_i_sw_bp_x0y0i0_in_15__o)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_15__prog_data)
+        );
+    prga_simple_buf i_buf_prog_rst_l0 (
+        .C(prog_clk)
+        ,.D(prog_rst)
+        ,.Q(_i_buf_prog_rst_l0__Q)
+        );
+    prga_simple_bufr i_buf_prog_done_l0 (
+        .C(prog_clk)
+        ,.R(_i_buf_prog_rst_l0__Q)
+        ,.D(prog_done)
+        ,.Q(_i_buf_prog_done_l0__Q)
+        );
+    scanchain_delim i_scanchain_head (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(prog_we)
+        ,.prog_din(prog_din)
+        ,.prog_dout(_i_scanchain_head__prog_dout)
+        ,.prog_we_o(_i_scanchain_head__prog_we_o)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_0 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_scanchain_head__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_0__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_0__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_1 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_0__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_1__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_1__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_2 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_1__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_2__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_2__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_3 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_2__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_3__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_3__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_4 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_3__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_4__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_4__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_5 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_4__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_5__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_5__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_6 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_5__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_6__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_6__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_7 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_6__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_7__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_7__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_8 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_7__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_8__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_8__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_9 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_8__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_9__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_9__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_10 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_9__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_10__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_10__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_11 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_10__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_11__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_11__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_12 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_11__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_12__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_12__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_13 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_12__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_13__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_13__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_14 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_13__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_14__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_14__prog_data)
+        );
+    scanchain_data_d3 i_prog_data_i_sw_bp_x0y0i0_in_15 (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_14__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_bp_x0y0i0_in_15__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_bp_x0y0i0_in_15__prog_data)
+        );
+    scanchain_delim i_scanchain_tail (
+        .prog_clk(prog_clk)
+        ,.prog_rst(_i_buf_prog_rst_l0__Q)
+        ,.prog_done(_i_buf_prog_done_l0__Q)
+        ,.prog_we(_i_scanchain_head__prog_we_o)
+        ,.prog_din(_i_prog_data_i_sw_bp_x0y0i0_in_15__prog_dout)
+        ,.prog_dout(_i_scanchain_tail__prog_dout)
+        ,.prog_we_o(_i_scanchain_tail__prog_we_o)
+        );
+        
+    assign bp_x0y0i0_in = {_i_sw_bp_x0y0i0_in_15__o,
+        _i_sw_bp_x0y0i0_in_14__o,
+        _i_sw_bp_x0y0i0_in_13__o,
+        _i_sw_bp_x0y0i0_in_12__o,
+        _i_sw_bp_x0y0i0_in_11__o,
+        _i_sw_bp_x0y0i0_in_10__o,
+        _i_sw_bp_x0y0i0_in_9__o,
+        _i_sw_bp_x0y0i0_in_8__o,
+        _i_sw_bp_x0y0i0_in_7__o,
+        _i_sw_bp_x0y0i0_in_6__o,
+        _i_sw_bp_x0y0i0_in_5__o,
+        _i_sw_bp_x0y0i0_in_4__o,
+        _i_sw_bp_x0y0i0_in_3__o,
+        _i_sw_bp_x0y0i0_in_2__o,
+        _i_sw_bp_x0y0i0_in_1__o,
+        _i_sw_bp_x0y0i0_in_0__o};
+    assign prog_dout = _i_scanchain_tail__prog_dout;
+    assign prog_we_o = _i_scanchain_tail__prog_we_o;
+
+endmodule
+module slice (
+    input wire [0:0] clk
+    , input wire [3:0] i
+    , output wire [0:0] o
+    , input wire [0:0] prog_clk
+    , input wire [0:0] prog_rst
+    , input wire [0:0] prog_done
+    , input wire [0:0] prog_we
+    , input wire [0:0] prog_din
+    , output wire [0:0] prog_dout
+    );
+    
+        
+    wire [0:0] _lut__out;
+    wire [0:0] _ff__Q;
+    wire [0:0] _i_sw_o__o;
+    wire [0:0] _i_prog_data_lut__prog_dout;
+    wire [16:0] _i_prog_data_lut__prog_data;
+    wire [0:0] _i_prog_data_ff__prog_dout;
+    wire [0:0] _i_prog_data_ff__prog_data;
+    wire [0:0] _i_prog_data_i_sw_o__prog_dout;
+    wire [1:0] _i_prog_data_i_sw_o__prog_data;
+        
+    lut4 lut (
+        .in(i)
+        ,.out(_lut__out)
+        ,.prog_done(prog_done)
+        ,.prog_data(_i_prog_data_lut__prog_data)
+        );
+    flipflop ff (
+        .clk(clk)
+        ,.D(_lut__out)
+        ,.Q(_ff__Q)
+        ,.prog_done(prog_done)
+        ,.prog_data(_i_prog_data_ff__prog_data)
+        );
+    sw2 i_sw_o (
+        .i({_ff__Q,
+            _lut__out})
+        ,.o(_i_sw_o__o)
+        ,.prog_done(prog_done)
+        ,.prog_data(_i_prog_data_i_sw_o__prog_data)
+        );
+    scanchain_data_d17 i_prog_data_lut (
+        .prog_clk(prog_clk)
+        ,.prog_rst(prog_rst)
+        ,.prog_done(prog_done)
+        ,.prog_we(prog_we)
+        ,.prog_din(prog_din)
+        ,.prog_dout(_i_prog_data_lut__prog_dout)
+        ,.prog_data(_i_prog_data_lut__prog_data)
+        );
+    scanchain_data_d1 i_prog_data_ff (
+        .prog_clk(prog_clk)
+        ,.prog_rst(prog_rst)
+        ,.prog_done(prog_done)
+        ,.prog_we(prog_we)
+        ,.prog_din(_i_prog_data_lut__prog_dout)
+        ,.prog_dout(_i_prog_data_ff__prog_dout)
+        ,.prog_data(_i_prog_data_ff__prog_data)
+        );
+    scanchain_data_d2 i_prog_data_i_sw_o (
+        .prog_clk(prog_clk)
+        ,.prog_rst(prog_rst)
+        ,.prog_done(prog_done)
+        ,.prog_we(prog_we)
+        ,.prog_din(_i_prog_data_ff__prog_dout)
+        ,.prog_dout(_i_prog_data_i_sw_o__prog_dout)
+        ,.prog_data(_i_prog_data_i_sw_o__prog_data)
+        );
+        
+    assign o = _i_sw_o__o;
+    assign prog_dout = _i_prog_data_i_sw_o__prog_dout;
+
+endmodule
+module sw6 (
+    input wire [5:0] i
+    , output reg [0:0] o
+
+    , input wire [0:0] prog_done
+    , input wire [2:0] prog_data
+    );
+
+    always @* begin
+        if (~prog_done) begin
+            o = 1'b0;
+        end else begin
+            o = 1'b0;   // if ``prog_data == 0`` or ``prog_data`` out of bound, output 0
+            case (prog_data)
+                3'd1: o = i[0];
+                3'd2: o = i[1];
+                3'd3: o = i[2];
+                3'd4: o = i[3];
+                3'd5: o = i[4];
+                3'd6: o = i[5];
+            endcase
+        end
+    end
+
+endmodule// Automatically generated by PRGA's RTL generator
+module lut4 (
+    input wire [3:0] in
+    , output reg [0:0] out
+
+    , input wire [0:0] prog_done
+    , input wire [16:0] prog_data
+        // prog_data[ 0 +: 15]: LUT content
+        // prog_data[16]: LUT enabled (not disabled)
+    );
+
+    localparam  IDX_LUT_ENABLE = 16;
+
+    always @* begin
+        if (~prog_done || ~prog_data[IDX_LUT_ENABLE]) begin
+            out = 1'b0;
+        end else begin
+            case (in)
+                4'd0: out = prog_data[0];
+                4'd1: out = prog_data[1];
+                4'd2: out = prog_data[2];
+                4'd3: out = prog_data[3];
+                4'd4: out = prog_data[4];
+                4'd5: out = prog_data[5];
+                4'd6: out = prog_data[6];
+                4'd7: out = prog_data[7];
+                4'd8: out = prog_data[8];
+                4'd9: out = prog_data[9];
+                4'd10: out = prog_data[10];
+                4'd11: out = prog_data[11];
+                4'd12: out = prog_data[12];
+                4'd13: out = prog_data[13];
+                4'd14: out = prog_data[14];
+                4'd15: out = prog_data[15];
+            endcase
+        end
+    end
+
+endmodule// Automatically generated by PRGA's RTL generator
+module flipflop (
+    input wire [0:0] clk
+    , input wire [0:0] D
+    , output reg [0:0] Q
+
+    , input wire [0:0] prog_done    // programming finished
+    , input wire [0:0] prog_data    // mode: enabled (not disabled)
+    );
+
+    always @(posedge clk) begin
+        if (~prog_done || ~prog_data) begin
+            Q <= 1'b0;
+        end else begin
+            Q <= D;
+        end
+    end
+
+endmodule// Automatically generated by PRGA's RTL generator
+module scanchain_data_d17 (
+    input wire [0:0] prog_clk
+    , input wire [0:0] prog_rst
+    , input wire [0:0] prog_done
+
+    , input wire [0:0] prog_we
+    , input wire [1 - 1:0] prog_din
+
+    , output reg [17 - 1:0] prog_data
+    , output wire [1 - 1:0] prog_dout
+    );
+
+    localparam CHAIN_BITCOUNT = 17;
+    localparam CHAIN_WIDTH = 1;
+
+    wire [CHAIN_BITCOUNT + CHAIN_WIDTH - 1:0] prog_data_next;
+    assign prog_data_next = {prog_data, prog_din};
+
+    always @(posedge prog_clk) begin
+        if (prog_rst) begin
+            prog_data <= {CHAIN_BITCOUNT{1'b0}};
+        end else if (~prog_done && prog_we) begin
+            prog_data <= prog_data_next[0 +: CHAIN_BITCOUNT];
+        end
+    end
+
+    assign prog_dout = prog_data_next[CHAIN_BITCOUNT +: CHAIN_WIDTH];
+
+endmodule// Automatically generated by PRGA's RTL generator