verilog/rtl/top.bb.v

// SPDX-FileCopyrightText: (c) 2022 Princeton University
// SPDX-License-Identifier: BSD-3-Clause
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// Automatically generated by PRGA's RTL generator
module top (
`ifdef USE_POWER_PINS
    inout vccd1,	// User area 1 1.8V supply
    inout vssd1,	// User area 1 digital ground
`endif
    input wire [0:0] ipin_x0y1_0
    , output wire [0:0] opin_x0y1_0
    , output wire [0:0] oe_x0y1_0
    , input wire [0:0] ipin_x0y1_1
    , output wire [0:0] opin_x0y1_1
    , output wire [0:0] oe_x0y1_1
    , input wire [0:0] ipin_x0y2_0
    , output wire [0:0] opin_x0y2_0
    , output wire [0:0] oe_x0y2_0
    , input wire [0:0] ipin_x0y2_1
    , output wire [0:0] opin_x0y2_1
    , output wire [0:0] oe_x0y2_1
    , input wire [0:0] ipin_x0y3_0
    , output wire [0:0] opin_x0y3_0
    , output wire [0:0] oe_x0y3_0
    , input wire [0:0] ipin_x0y3_1
    , output wire [0:0] opin_x0y3_1
    , output wire [0:0] oe_x0y3_1
    , input wire [0:0] ipin_x0y4_0
    , output wire [0:0] opin_x0y4_0
    , output wire [0:0] oe_x0y4_0
    , input wire [0:0] ipin_x0y4_1
    , output wire [0:0] opin_x0y4_1
    , output wire [0:0] oe_x0y4_1
    , input wire [0:0] ipin_x0y5_0
    , output wire [0:0] opin_x0y5_0
    , output wire [0:0] oe_x0y5_0
    , input wire [0:0] ipin_x0y5_1
    , output wire [0:0] opin_x0y5_1
    , output wire [0:0] oe_x0y5_1
    , input wire [0:0] ipin_x0y6_0
    , output wire [0:0] opin_x0y6_0
    , output wire [0:0] oe_x0y6_0
    , input wire [0:0] ipin_x0y6_1
    , output wire [0:0] opin_x0y6_1
    , output wire [0:0] oe_x0y6_1
    , input wire [0:0] ipin_x0y7_0
    , output wire [0:0] opin_x0y7_0
    , output wire [0:0] oe_x0y7_0
    , input wire [0:0] ipin_x0y7_1
    , output wire [0:0] opin_x0y7_1
    , output wire [0:0] oe_x0y7_1
    , input wire [0:0] ipin_x0y8_0
    , output wire [0:0] opin_x0y8_0
    , output wire [0:0] oe_x0y8_0
    , input wire [0:0] ipin_x0y8_1
    , output wire [0:0] opin_x0y8_1
    , output wire [0:0] oe_x0y8_1
    , input wire [0:0] ipin_x1y9_0
    , output wire [0:0] opin_x1y9_0
    , output wire [0:0] oe_x1y9_0
    , input wire [0:0] ipin_x1y9_1
    , output wire [0:0] opin_x1y9_1
    , output wire [0:0] oe_x1y9_1
    , input wire [0:0] ipin_x2y9_0
    , output wire [0:0] opin_x2y9_0
    , output wire [0:0] oe_x2y9_0
    , input wire [0:0] ipin_x2y9_1
    , output wire [0:0] opin_x2y9_1
    , output wire [0:0] oe_x2y9_1
    , input wire [0:0] ipin_x3y9_0
    , output wire [0:0] opin_x3y9_0
    , output wire [0:0] oe_x3y9_0
    , input wire [0:0] ipin_x3y9_1
    , output wire [0:0] opin_x3y9_1
    , output wire [0:0] oe_x3y9_1
    , input wire [0:0] ipin_x4y9_0
    , output wire [0:0] opin_x4y9_0
    , output wire [0:0] oe_x4y9_0
    , input wire [0:0] ipin_x4y9_1
    , output wire [0:0] opin_x4y9_1
    , output wire [0:0] oe_x4y9_1
    , input wire [0:0] ipin_x5y9_0
    , output wire [0:0] opin_x5y9_0
    , output wire [0:0] oe_x5y9_0
    , input wire [0:0] ipin_x5y9_1
    , output wire [0:0] opin_x5y9_1
    , output wire [0:0] oe_x5y9_1
    , input wire [0:0] ipin_x6y9_0
    , output wire [0:0] opin_x6y9_0
    , output wire [0:0] oe_x6y9_0
    , input wire [0:0] ipin_x6y9_1
    , output wire [0:0] opin_x6y9_1
    , output wire [0:0] oe_x6y9_1
    , input wire [0:0] ipin_x7y9_0
    , output wire [0:0] opin_x7y9_0
    , output wire [0:0] oe_x7y9_0
    , input wire [0:0] ipin_x7y9_1
    , output wire [0:0] opin_x7y9_1
    , output wire [0:0] oe_x7y9_1
    , input wire [0:0] ipin_x8y9_0
    , output wire [0:0] opin_x8y9_0
    , output wire [0:0] oe_x8y9_0
    , input wire [0:0] ipin_x8y9_1
    , output wire [0:0] opin_x8y9_1
    , output wire [0:0] oe_x8y9_1
    , input wire [0:0] ipin_x9y1_0
    , output wire [0:0] opin_x9y1_0
    , output wire [0:0] oe_x9y1_0
    , input wire [0:0] ipin_x9y1_1
    , output wire [0:0] opin_x9y1_1
    , output wire [0:0] oe_x9y1_1
    , input wire [0:0] ipin_x9y2_0
    , output wire [0:0] opin_x9y2_0
    , output wire [0:0] oe_x9y2_0
    , input wire [0:0] ipin_x9y2_1
    , output wire [0:0] opin_x9y2_1
    , output wire [0:0] oe_x9y2_1
    , input wire [0:0] ipin_x9y3_0
    , output wire [0:0] opin_x9y3_0
    , output wire [0:0] oe_x9y3_0
    , input wire [0:0] ipin_x9y3_1
    , output wire [0:0] opin_x9y3_1
    , output wire [0:0] oe_x9y3_1
    , input wire [0:0] ipin_x9y4_0
    , output wire [0:0] opin_x9y4_0
    , output wire [0:0] oe_x9y4_0
    , input wire [0:0] ipin_x9y4_1
    , output wire [0:0] opin_x9y4_1
    , output wire [0:0] oe_x9y4_1
    , input wire [0:0] ipin_x9y5_0
    , output wire [0:0] opin_x9y5_0
    , output wire [0:0] oe_x9y5_0
    , input wire [0:0] ipin_x9y5_1
    , output wire [0:0] opin_x9y5_1
    , output wire [0:0] oe_x9y5_1
    , input wire [0:0] ipin_x9y6_0
    , output wire [0:0] opin_x9y6_0
    , output wire [0:0] oe_x9y6_0
    , input wire [0:0] ipin_x9y6_1
    , output wire [0:0] opin_x9y6_1
    , output wire [0:0] oe_x9y6_1
    , input wire [0:0] ipin_x9y7_0
    , output wire [0:0] opin_x9y7_0
    , output wire [0:0] oe_x9y7_0
    , input wire [0:0] ipin_x9y7_1
    , output wire [0:0] opin_x9y7_1
    , output wire [0:0] oe_x9y7_1
    , input wire [0:0] ipin_x9y8_0
    , output wire [0:0] opin_x9y8_0
    , output wire [0:0] oe_x9y8_0
    , input wire [0:0] ipin_x9y8_1
    , output wire [0:0] opin_x9y8_1
    , output wire [0:0] oe_x9y8_1
    , input wire [0:0] prog_clk
    , input wire [0:0] prog_rst
    , input wire [0:0] prog_done
    , input wire [0:0] prog_we
    , input wire [0:0] prog_din
    , output wire [0:0] prog_dout
    , output wire [0:0] prog_we_o
    );
    
endmodule