)]}'
{
  "commit": "76666c6e64dac8992f26e4c42ce072723a00f975",
  "tree": "e5d9fd7c88b1f4ec8d5241616763d44a383200d6",
  "parents": [
    "7b76767c5624c3146d276fd80e37eaf25d3aaa80"
  ],
  "author": {
    "name": "duchungle",
    "email": "leduchung@gmail.com",
    "time": "Tue Jun 07 17:52:18 2022 +0700"
  },
  "committer": {
    "name": "duchungle",
    "email": "leduchung@gmail.com",
    "time": "Tue Jun 07 17:52:18 2022 +0700"
  },
  "message": "Add design files\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "10fd9fd6016970d782e4728228cb3d19feb909f8",
      "old_mode": 33188,
      "old_path": "def/user_project_wrapper.def",
      "new_id": "d449ff1bf40e7a444c9879d462400ecac37dc980",
      "new_mode": 33188,
      "new_path": "def/user_project_wrapper.def"
    },
    {
      "type": "modify",
      "old_id": "07ee6149be8c6544aa6d757b8d67f55c36af85eb",
      "old_mode": 33188,
      "old_path": "gds/user_project_wrapper.gds",
      "new_id": "a00e0694f90902d7c6bdd2de9d373abd9bcddcf1",
      "new_mode": 33188,
      "new_path": "gds/user_project_wrapper.gds"
    },
    {
      "type": "modify",
      "old_id": "d33076de4586befa35658ddab3d02fd5dccd50af",
      "old_mode": 33188,
      "old_path": "lef/user_project_wrapper.lef",
      "new_id": "355f7fbd2d16e8281412a209cf29fc43dbf13a71",
      "new_mode": 33188,
      "new_path": "lef/user_project_wrapper.lef"
    },
    {
      "type": "modify",
      "old_id": "acc3ede2bd65f42e2616885d913fc6614339e599",
      "old_mode": 33188,
      "old_path": "mag/user_project_wrapper.mag",
      "new_id": "487312639c6a0b84a31b2137d70822c710a1432e",
      "new_mode": 33188,
      "new_path": "mag/user_project_wrapper.mag"
    },
    {
      "type": "modify",
      "old_id": "f22c33c4278d77bc6c6e1d9f2eec8918f1c7afc7",
      "old_mode": 33188,
      "old_path": "maglef/user_project_wrapper.mag",
      "new_id": "3c956b921d3125a4d58eed6c260f6b97c30613a6",
      "new_mode": 33188,
      "new_path": "maglef/user_project_wrapper.mag"
    },
    {
      "type": "modify",
      "old_id": "41cfed6edda5d1799fd3ce9ded6429c3cb5446fb",
      "old_mode": 33261,
      "old_path": "openlane/user_project_wrapper/config.tcl",
      "new_id": "59d5b435710fba06d6401f697547058845336fd1",
      "new_mode": 33261,
      "new_path": "openlane/user_project_wrapper/config.tcl"
    },
    {
      "type": "modify",
      "old_id": "eeebedc3940b6a437ee814c1b6b07cd0affd5d81",
      "old_mode": 33188,
      "old_path": "sdf/user_project_wrapper.sdf",
      "new_id": "b4d33589196401725deeaa9d832b2eb5d05203ea",
      "new_mode": 33188,
      "new_path": "sdf/user_project_wrapper.sdf"
    },
    {
      "type": "modify",
      "old_id": "60339fdde6e4b31ae104d0ce4109ef5960c4ade9",
      "old_mode": 33188,
      "old_path": "signoff/user_project_wrapper/final_summary_report.csv",
      "new_id": "ae5b5c3684c93e27152f62dcbfada1ca7a823c02",
      "new_mode": 33188,
      "new_path": "signoff/user_project_wrapper/final_summary_report.csv"
    },
    {
      "type": "modify",
      "old_id": "c07ff8adb36cd8966d80d7cce1572e8c602ef3bb",
      "old_mode": 33188,
      "old_path": "spef/user_project_wrapper.spef",
      "new_id": "2ac34b4de96d9404de33cac1a3471070537dc9a3",
      "new_mode": 33188,
      "new_path": "spef/user_project_wrapper.spef"
    },
    {
      "type": "modify",
      "old_id": "3d40d3057e3999e3b2f4797df04e7e7760e2364e",
      "old_mode": 33188,
      "old_path": "spi/lvs/user_project_wrapper.spice",
      "new_id": "7545a101a208a2b789b38fcd38a93fd4464241bc",
      "new_mode": 33188,
      "new_path": "spi/lvs/user_project_wrapper.spice"
    },
    {
      "type": "delete",
      "old_id": "aacda1373619805e0b3ce2c39ef1f72fae5df8e2",
      "old_mode": 33188,
      "old_path": "verilog/gl/DCT_32P_TOP.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "d1486cb3b4adccf8d0ee7d022fa9c2afbe5d8cd0",
      "old_mode": 33188,
      "old_path": "verilog/gl/DCT_V32P_TOP.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "def2963ea237b883eb598d38058f87bd69690a08",
      "old_mode": 33188,
      "old_path": "verilog/gl/aes_128.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "d4b392858ec3dbab791f501acc2fcaad552c1f87",
      "old_mode": 33188,
      "old_path": "verilog/gl/chacha.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "cd4f0a5fdbde657eb1b0915e1a62dc9eac451fdf",
      "old_mode": 33188,
      "old_path": "verilog/gl/dct_v32p_wrapper.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "05fe1d7993de0d74b4292bff5743ab9a11cc3cd8",
      "old_mode": 33188,
      "old_path": "verilog/gl/prince.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "80a2b98812ecae8c672b4e936390488ac42518c9",
      "old_mode": 33188,
      "old_path": "verilog/gl/prince_wrapper.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "modify",
      "old_id": "c5c10cd6d22e1049ea55d1a8e77dd13d864403e0",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_project_wrapper.v",
      "new_id": "6c285b605a82764dee2e923fbb382416d255a4c1",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_project_wrapper.v"
    },
    {
      "type": "modify",
      "old_id": "2c0a0c7d37982b398b02988d899766a912730067",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "a4829be26f9c2b38d270332b8f51a8c01c64a68a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}
