diff --git a/caravel b/caravel
new file mode 160000
index 0000000..477c17f
--- /dev/null
+++ b/caravel
@@ -0,0 +1 @@
+Subproject commit 477c17fb986b0d3f7f3581e940095b68bd62422f
diff --git a/caravel_pico b/caravel_pico
new file mode 160000
index 0000000..1fc14b5
--- /dev/null
+++ b/caravel_pico
@@ -0,0 +1 @@
+Subproject commit 1fc14b5c9a25cd0f4e46cdd02b8017dc3eae0d05
diff --git a/mgmt_core_wrapper b/mgmt_core_wrapper
new file mode 160000
index 0000000..3fee299
--- /dev/null
+++ b/mgmt_core_wrapper
@@ -0,0 +1 @@
+Subproject commit 3fee299f8177cebf7919eb0e6da7f0f5ad7af31d
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
index 8797dcd..7293cef 120000
--- a/openlane/user_project_wrapper/pin_order.cfg
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -1 +1 @@
-../../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file
+pin_order.cfg
\ No newline at end of file
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 94d0ead..5927800 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -20,7 +20,7 @@
 .SILENT: clean all
 
 
-PATTERNS = nec_ir_receiver
+PATTERNS = pseudorandom nec_ir_receiver
 
 all:  ${PATTERNS}
 
diff --git a/verilog/dv/nec_ir_receiver/nec_ir_receiver.c b/verilog/dv/nec_ir_receiver/nec_ir_receiver.c
index 74c3958..e8e17ef 100644
--- a/verilog/dv/nec_ir_receiver/nec_ir_receiver.c
+++ b/verilog/dv/nec_ir_receiver/nec_ir_receiver.c
@@ -90,7 +90,7 @@
     reg_mprj_io_3  = GPIO_MODE_MGMT_STD_OUTPUT;
     reg_mprj_io_2  = GPIO_MODE_MGMT_STD_OUTPUT;
     reg_mprj_io_1  = GPIO_MODE_MGMT_STD_OUTPUT;
-    //reg_mprj_io_0  = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_0  = GPIO_MODE_MGMT_STD_OUTPUT;
     
     /* Config IR receiver */
     // 70 312,5ns / 25ns
@@ -111,6 +111,6 @@
   do {
      ir_data = reg_mprj_ir_data;
   } while ((ir_data & 0x80000000) != 0x80000000 );
-  reg_mprj_datal = 0xAB610000 | ((ir_data << 1) & 0x0000FFFE) ;
+  reg_mprj_datal = 0xAB610000 | (ir_data & 0x0000FFFF) ;
 
 }
diff --git a/verilog/dv/nec_ir_receiver/nec_ir_receiver_tb.v b/verilog/dv/nec_ir_receiver/nec_ir_receiver_tb.v
index 7b49d27..385d30f 100644
--- a/verilog/dv/nec_ir_receiver/nec_ir_receiver_tb.v
+++ b/verilog/dv/nec_ir_receiver/nec_ir_receiver_tb.v
@@ -17,7 +17,7 @@
 
 `timescale 1 ns / 1 ps
 
-module wb_port_tb;
+module nec_ir_receiver_tb;
   reg clock;
   reg RSTB;
   reg CSB;
@@ -35,10 +35,8 @@
   reg [7:0]  cmd_data;
 
   assign checkbits = mprj_io[31:16];
-  assign addrbits = {1'b0, mprj_io[15:9]};
-  assign databits = mprj_io[8:1];
-
-  //assign mprj_io[3] = 1'b1;
+  assign addrbits  = mprj_io[15:8];
+  assign databits  = mprj_io[7:0];
 
   // External clock is used by default.  Make this artificially fast for the
   // simulation.  Normally this would be a slow clock and the digital PLL
@@ -52,7 +50,7 @@
 
   initial begin
     $dumpfile("nec_ir_receiver.vcd");
-    $dumpvars(0, wb_port_tb);
+    $dumpvars(0, nec_ir_receiver_tb);
 
     // Repeat cycles of 1000 clock edges as needed to complete testbench
     repeat (7000) begin
@@ -78,20 +76,20 @@
     $display("Monitor: MPRJ-Logic WB Started");
     ir_drv.send_nec(cmd_addr, cmd_data);
     wait (checkbits == 16'hAB61);
-      if ((addrbits[6:0] == cmd_addr[6:0]) && (databits == cmd_data)) begin
-        `ifdef GL
-          $display("Monitor: Mega-Project WB (GL) Passed");
-        `else
-          $display("Monitor: Mega-Project WB (RTL) Passed");
-        `endif
-      end else begin
-        `ifdef GL
-          $display("Monitor: Mega-Project WB (GL) Failed [0x%h -> 0x%h]", addrbits, databits);
-        `else
-          $display("Monitor: Mega-Project WB (RTL) Failed [0x%h -> 0x%h]", addrbits, databits);
-        `endif
-      end
-      $finish;
+    if ((addrbits == cmd_addr) && (databits == cmd_data)) begin
+      `ifdef GL
+        $display("Monitor: Mega-Project WB (GL) Passed");
+      `else
+        $display("Monitor: Mega-Project WB (RTL) Passed");
+      `endif
+    end else begin
+      `ifdef GL
+        $display("Monitor: Mega-Project WB (GL) Failed [0x%h -> 0x%h]", addrbits, databits);
+      `else
+        $display("Monitor: Mega-Project WB (RTL) Failed [0x%h -> 0x%h]", addrbits, databits);
+      `endif
+    end
+    $finish;
   end
 
   initial begin
@@ -124,7 +122,7 @@
   wire VSS = 1'b0;
   
   ir_behavioral_driver ir_drv(
-    .ir_signal(mprj_io[0])
+    .ir_signal(mprj_io[37])
   );
 
   caravel uut (
diff --git a/verilog/dv/pseudorandom/Makefile b/verilog/dv/pseudorandom/Makefile
new file mode 100644
index 0000000..3fd0b56
--- /dev/null
+++ b/verilog/dv/pseudorandom/Makefile
@@ -0,0 +1,32 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+ 
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+
+
diff --git a/verilog/dv/pseudorandom/pseudorandom.c b/verilog/dv/pseudorandom/pseudorandom.c
new file mode 100644
index 0000000..6b82d38
--- /dev/null
+++ b/verilog/dv/pseudorandom/pseudorandom.c
@@ -0,0 +1,121 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+/*
+	Wishbone Test:
+		- Configures MPRJ lower 8-IO pins as outputs
+		- Checks counter value through the wishbone port
+*/
+
+#define reg_mprj_ir_cmd        (*(volatile uint32_t*)0x30000000)
+#define reg_mprj_ir_multiplier (*(volatile uint32_t*)0x30000004)
+#define reg_mprj_ir_divider    (*(volatile uint32_t*)0x30000008)
+#define reg_mprj_ir_data       (*(volatile uint32_t*)0x3000000C)
+
+#define reg_mprj_rand          (*(volatile uint32_t*)0x30010000)
+
+void main()
+{
+
+	/* 
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+	
+	 
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+	*/
+
+	/* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+    reg_spi_enable = 1;
+    reg_wb_enable = 1;
+	// reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_9  = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_8  = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_7  = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_5  = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_4  = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_3  = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_2  = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_1  = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_0  = GPIO_MODE_MGMT_STD_OUTPUT;
+
+  /* Apply configuration */
+  reg_mprj_xfer = 1;
+  while (reg_mprj_xfer == 1);
+
+  reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
+
+  // Flag start of the test
+  reg_mprj_datal = 0xAB600000;
+
+  int i, error, data, last_data;
+  error = 0;
+  last_data = 0x00000000;
+
+  for(i=0;i<4;i++) {
+    data = reg_mprj_rand;
+    if (data == 0x00000000) error++;
+    if (data == 0xFFFFFFFF) error++;
+    if (data == last_data ) error++;
+    last_data = data;
+  }
+  
+  // Flag end of the test
+  reg_mprj_datal = 0xAB610000 | (error & 0x0000FFFF);
+
+}
diff --git a/verilog/dv/pseudorandom/pseudorandom_tb.v b/verilog/dv/pseudorandom/pseudorandom_tb.v
new file mode 100644
index 0000000..c32c9b8
--- /dev/null
+++ b/verilog/dv/pseudorandom/pseudorandom_tb.v
@@ -0,0 +1,159 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+module pseudorandom_tb;
+  reg clock;
+  reg RSTB;
+  reg CSB;
+  reg power1, power2;
+  reg power3, power4;
+
+  wire gpio;
+  wire [37:0] mprj_io;
+  wire [7:0] mprj_io_0;
+  wire [15:0] checkbits;
+  wire [15:0] errorbits;
+  
+  reg [7:0]  cmd_addr;
+  reg [7:0]  cmd_data;
+
+  assign checkbits = mprj_io[31:16];
+  assign errorbits = mprj_io[15:0];
+
+  // External clock is used by default.  Make this artificially fast for the
+  // simulation.  Normally this would be a slow clock and the digital PLL
+  // would be the fast clock.
+
+  always #12.5 clock <= (clock === 1'b0);
+
+  initial begin
+    clock = 0;
+  end
+
+  initial begin
+    $dumpfile("pseudorandom.vcd");
+    $dumpvars(0, pseudorandom_tb);
+
+    // Repeat cycles of 1000 clock edges as needed to complete testbench
+    repeat (7000) begin
+      repeat (1000) @(posedge clock);
+      // $display("+1000 cycles");
+    end
+    $display("%c[1;31m",27);
+    `ifdef GL
+      $display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
+    `else
+      $display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");
+    `endif
+    $display("%c[0m",27);
+    $finish;
+  end
+
+  initial begin
+
+    wait(checkbits == 16'hAB60);
+    $display("Monitor: MPRJ-Logic WB Started");
+    wait (checkbits == 16'hAB61);
+    if (errorbits == 16'h0000) begin
+      `ifdef GL
+        $display("Monitor: Mega-Project WB (GL) Passed");
+      `else
+        $display("Monitor: Mega-Project WB (RTL) Passed");
+      `endif
+    end else begin
+      `ifdef GL
+        $display("Monitor: Mega-Project WB (GL) Failed [0x%h errors]", errorbits);
+      `else
+        $display("Monitor: Mega-Project WB (RTL) Failed [0x%h errors]", errorbits);
+      `endif
+    end
+    $finish;
+  end
+
+  initial begin
+    RSTB <= 1'b0;
+    CSB  <= 1'b1;    // Force CSB high
+    #2000;
+    RSTB <= 1'b1;        // Release reset
+    #100000;
+    CSB = 1'b0;    // CSB can be released
+  end
+
+  initial begin    // Power-up sequence
+    power1 <= 1'b0;
+    power2 <= 1'b0;
+    #200;
+    power1 <= 1'b1;
+    #200;
+    power2 <= 1'b1;
+  end
+
+  wire flash_csb;
+  wire flash_clk;
+  wire flash_io0;
+  wire flash_io1;
+
+  wire VDD3V3 = power1;
+  wire VDD1V8 = power2;
+  wire USER_VDD3V3 = power3;
+  wire USER_VDD1V8 = power4;
+  wire VSS = 1'b0;
+
+  caravel uut (
+    .vddio    (VDD3V3),
+    .vddio_2  (VDD3V3),
+    .vssio    (VSS),
+    .vssio_2  (VSS),
+    .vdda    (VDD3V3),
+    .vssa    (VSS),
+    .vccd    (VDD1V8),
+    .vssd    (VSS),
+    .vdda1    (VDD3V3),
+    .vdda1_2  (VDD3V3),
+    .vdda2    (VDD3V3),
+    .vssa1    (VSS),
+    .vssa1_2  (VSS),
+    .vssa2    (VSS),
+    .vccd1    (VDD1V8),
+    .vccd2    (VDD1V8),
+    .vssd1    (VSS),
+    .vssd2    (VSS),
+    .clock    (clock),
+    .gpio     (gpio),
+    .mprj_io  (mprj_io),
+    .flash_csb(flash_csb),
+    .flash_clk(flash_clk),
+    .flash_io0(flash_io0),
+    .flash_io1(flash_io1),
+    .resetb    (RSTB)
+  );
+
+  spiflash #(
+    .FILENAME("pseudorandom.hex")
+  ) spiflash (
+    .csb(flash_csb),
+    .clk(flash_clk),
+    .io0(flash_io0),
+    .io1(flash_io1),
+    .io2(),      // not used
+    .io3()      // not used
+  );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 7f8d973..039a4cd 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,7 +1,9 @@
 # Caravel user project includes
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
 -v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
+-v $(USER_PROJECT_VERILOG)/rtl/wishbone_1mst_to_8slv.v
 -v $(USER_PROJECT_VERILOG)/rtl/simple_fifo.v
 -v $(USER_PROJECT_VERILOG)/rtl/nec_ir_receiver.v
+-v $(USER_PROJECT_VERILOG)/rtl/pseudorandom.v
 -v $(USER_PROJECT_VERILOG)/beh/ir_behavioral_driver.v
  
diff --git a/verilog/rtl/nec_ir_receiver.v b/verilog/rtl/nec_ir_receiver.v
index f04e892..f1df164 100644
--- a/verilog/rtl/nec_ir_receiver.v
+++ b/verilog/rtl/nec_ir_receiver.v
@@ -672,11 +672,17 @@
           end
           status_reg_addr : begin
             wbs_dat_o[31]    <= frame_available;
-            wbs_dat_o[30]    <= frame_repeat;
-            wbs_dat_o[29]    <= frame_lost;
-            wbs_dat_o[28:16] <= 13'b0;
-            wbs_dat_o[15:8]  <= frame_addr;
-            wbs_dat_o[7:0]   <= frame_data;
+            
+            if (frame_available == 1'b1) begin
+              wbs_dat_o[31]    <= 1'b1;
+              wbs_dat_o[30]    <= frame_repeat;
+              wbs_dat_o[29]    <= frame_lost;
+              wbs_dat_o[28:16] <= 13'b0;
+              wbs_dat_o[15:8]  <= frame_addr;
+              wbs_dat_o[7:0]   <= frame_data;
+            end else begin
+              wbs_dat_o        <= 32'h00000000;
+            end
           end
         endcase
 
diff --git a/verilog/rtl/pseudorandom.v b/verilog/rtl/pseudorandom.v
new file mode 100644
index 0000000..72f205a
--- /dev/null
+++ b/verilog/rtl/pseudorandom.v
@@ -0,0 +1,96 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , Julien OURY                       
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+//
+////////////////////////////////////////////////////////////////////////////
+
+module pseudorandom (
+  input  wire        rst_n     , // Asynchronous reset (active low)
+  input  wire        clk       , // Clock (rising edge)
+
+  // Wishbone bus
+  input  wire        wbs_cyc_i , // Wishbone strobe/request
+  input  wire        wbs_stb_i , // Wishbone strobe/request
+  input  wire [31:0] wbs_adr_i , // Wishbone address
+  input  wire        wbs_we_i  , // Wishbone write (1:write, 0:read)
+  input  wire [31:0] wbs_dat_i , // Wishbone data output
+  input  wire [3:0]  wbs_sel_i , // Wishbone byte enable
+  output reg  [31:0] wbs_dat_o , // Wishbone data input
+  output wire        wbs_ack_o   // Wishbone acknowlegement
+);
+  reg ready;
+  wire [31:0] rand_data;
+
+  always @(negedge rst_n or posedge clk) begin
+    if (rst_n == 1'b0) begin
+      wbs_dat_o <= 32'h00000000;
+      ready     <= 1'b0;
+    end else begin
+      if (wbs_cyc_i && wbs_stb_i && ~wbs_we_i && ~ready) begin
+        wbs_dat_o <= rand_data;
+        ready     <= 1'b1;
+      end else begin
+        ready     <= 1'b0;
+      end
+    end
+  end
+
+  xoroshiro_64_plus_plus i_xoroshiro_64_plus_plus(
+    .rst_n (rst_n    ),
+    .clk   (clk      ),
+    .next  (ready    ),
+    .random(rand_data)
+  );
+  
+  assign wbs_ack_o = ready;
+
+endmodule
+
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Xoroshiro64++
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+module xoroshiro_64_plus_plus (
+  input  wire        rst_n     , // Asynchronous reset (active low)
+  input  wire        clk       , // Clock (rising edge)
+  input  wire        next      , // Request next value
+  output wire [31:0] random      // Random value
+);
+  reg  [31:0] s0;
+  reg  [31:0] s1;
+  wire [31:0] n0;
+  wire [31:0] n1;
+  wire [31:0] s1_xor_s0;
+  wire [31:0] n1_plus_n0;
+
+  assign s1_xor_s0 = (s1 ^ s0);
+  assign n1_plus_n0 = (n0 + n1);
+  assign n0 = (({s0[5:0],s0[31:6]} ^ s1_xor_s0) ^ (s1_xor_s0 <<< 9));
+  assign n1 = {s1_xor_s0[18:0],s1_xor_s0[31:19]};
+  assign random = ({n1_plus_n0[14:0],n1_plus_n0[31 : 15]} + n0);
+  
+  always @(negedge rst_n or posedge clk) begin
+    if (rst_n == 1'b0) begin
+      s0 <= (32'h00000001);
+      s1 <= (32'h00000000);
+    end else begin
+      if (next == 1'b1) begin
+        s0 <= n0;
+        s1 <= n1;
+      end
+    end
+  end
+
+endmodule
diff --git a/verilog/rtl/simple_fifo.v b/verilog/rtl/simple_fifo.v
index 26b8429..aa11bc1 100644
--- a/verilog/rtl/simple_fifo.v
+++ b/verilog/rtl/simple_fifo.v
@@ -63,15 +63,9 @@
   end
 
   // Write operation
-  always @(negedge rst_n or posedge clk) begin
-    if (rst_n == 1'b0) begin
-      for (i = 0; i < (2**ASIZE); i = i + 1) begin
-        memory[i] <= {DSIZE{1'b0}};
-      end
-    end else begin
-      if (wr_valid && wr_ready) begin
-        memory[wr_ptr] <= wr_data;
-      end
+  always @(posedge clk) begin
+    if (wr_valid && wr_ready) begin
+      memory[wr_ptr] <= wr_data;
     end
   end
 
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 62241d0..2d55d6e 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -25,6 +25,8 @@
 `else
     `include "user_project_wrapper.v"
     `include "user_proj_example.v"
+	`include "wishbone_1mst_to_8slv.v"
     `include "simple_fifo.v"
     `include "nec_ir_receiver.v"
+	`include "pseudorandom.v"
 `endif
\ No newline at end of file
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index c76f860..7f8a672 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -1,5 +1,6 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , Julien OURY                       
+// 
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
@@ -12,67 +13,124 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-/*
- *-------------------------------------------------------------
- *
- * user_proj_example
- *
- * This is an example of a (trivially simple) user project,
- * showing how the user project can connect to the logic
- * analyzer, the wishbone bus, and the I/O pads.
- *
- * This project generates an integer count, which is output
- * on the user area GPIO pads (digital output only).  The
- * wishbone connection allows the project to be controlled
- * (start and stop) from the management SoC program.
- *
- * See the testbenches in directory "mprj_counter" for the
- * example programs that drive this user project.  The three
- * testbenches are "io_ports", "la_test1", and "la_test2".
- *
- *-------------------------------------------------------------
- */
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+//
+////////////////////////////////////////////////////////////////////////////
 
 module user_proj_example(
 
 `ifdef USE_POWER_PINS
-    inout vccd1,	// User area 1 1.8V supply
-    inout vssd1,	// User area 1 digital ground
+    inout  wire vccd1,	// User area 1 1.8V supply
+    inout  wire vssd1,	// User area 1 digital ground
 `endif
 
     // Wishbone Slave ports (WB MI A)
-    input wb_clk_i,
-    input wb_rst_i,
-    input wbs_stb_i,
-    input wbs_cyc_i,
-    input wbs_we_i,
-    input [3:0] wbs_sel_i,
-    input [31:0] wbs_dat_i,
-    input [31:0] wbs_adr_i,
-    output wbs_ack_o,
-    output [31:0] wbs_dat_o,
+    input  wire         wb_clk_i,
+    input  wire         wb_rst_i,
+    input  wire         wbs_stb_i,
+    input  wire         wbs_cyc_i,
+    input  wire         wbs_we_i,
+    input  wire [3:0]   wbs_sel_i,
+    input  wire [31:0]  wbs_dat_i,
+    input  wire [31:0]  wbs_adr_i,
+    output wire         wbs_ack_o,
+    output wire [31:0]  wbs_dat_o,
 
     // Logic Analyzer Signals
-    input  [127:0] la_data_in,
-    output [127:0] la_data_out,
-    input  [127:0] la_oenb,
+    input  wire [127:0] la_data_in,
+    output wire [127:0] la_data_out,
+    input  wire [127:0] la_oenb,
 
     // IOs
-    input  [`MPRJ_IO_PADS-1:0] io_in,
-    output [`MPRJ_IO_PADS-1:0] io_out,
-    output [`MPRJ_IO_PADS-1:0] io_oeb,
+    input  wire [`MPRJ_IO_PADS-1:0] io_in,
+    output wire [`MPRJ_IO_PADS-1:0] io_out,
+    output wire [`MPRJ_IO_PADS-1:0] io_oeb,
 
     // IRQ
-    output [2:0] irq
+    output wire [2:0] irq
 );
 
     wire rst_n;
-
-    wire [`MPRJ_IO_PADS-1:0] io_in;
-    wire [`MPRJ_IO_PADS-1:0] io_out;
-    wire [`MPRJ_IO_PADS-1:0] io_oeb;
+    
+    // Wishbone SLV 0 interface
+    wire           wbs_s0_cyc_o ;
+    wire           wbs_s0_stb_o ;
+    wire [31:0]    wbs_s0_adr_o ;
+    wire           wbs_s0_we_o  ;
+    wire [31:0]    wbs_s0_dat_o ;
+    wire [3:0]     wbs_s0_sel_o ;
+    wire [31:0]    wbs_s0_dat_i ;
+    wire           wbs_s0_ack_i ;
+    
+    // Wishbone SLV 1 interface
+    wire           wbs_s1_cyc_o ;
+    wire           wbs_s1_stb_o ;
+    wire [31:0]    wbs_s1_adr_o ;
+    wire           wbs_s1_we_o  ;
+    wire [31:0]    wbs_s1_dat_o ;
+    wire [3:0]     wbs_s1_sel_o ;
+    wire [31:0]    wbs_s1_dat_i ;
+    wire           wbs_s1_ack_i ;
+    
+    // Wishbone SLV 2 interface
+    wire           wbs_s2_cyc_o ;
+    wire           wbs_s2_stb_o ;
+    wire [31:0]    wbs_s2_adr_o ;
+    wire           wbs_s2_we_o  ;
+    wire [31:0]    wbs_s2_dat_o ;
+    wire [3:0]     wbs_s2_sel_o ;
+    wire [31:0]    wbs_s2_dat_i ;
+    wire           wbs_s2_ack_i ;
+    
+    // Wishbone SLV 3 interface
+    wire           wbs_s3_cyc_o ;
+    wire           wbs_s3_stb_o ;
+    wire [31:0]    wbs_s3_adr_o ;
+    wire           wbs_s3_we_o  ;
+    wire [31:0]    wbs_s3_dat_o ;
+    wire [3:0]     wbs_s3_sel_o ;
+    wire [31:0]    wbs_s3_dat_i ;
+    wire           wbs_s3_ack_i ;
+    
+    // Wishbone SLV 4 interface
+    wire           wbs_s4_cyc_o ;
+    wire           wbs_s4_stb_o ;
+    wire [31:0]    wbs_s4_adr_o ;
+    wire           wbs_s4_we_o  ;
+    wire [31:0]    wbs_s4_dat_o ;
+    wire [3:0]     wbs_s4_sel_o ;
+    wire [31:0]    wbs_s4_dat_i ;
+    wire           wbs_s4_ack_i ;
+    
+    // Wishbone SLV 5 interface
+    wire           wbs_s5_cyc_o ;
+    wire           wbs_s5_stb_o ;
+    wire [31:0]    wbs_s5_adr_o ;
+    wire           wbs_s5_we_o  ;
+    wire [31:0]    wbs_s5_dat_o ;
+    wire [3:0]     wbs_s5_sel_o ;
+    wire [31:0]    wbs_s5_dat_i ;
+    wire           wbs_s5_ack_i ;
+    
+    // Wishbone SLV 6 interface
+    wire           wbs_s6_cyc_o ;
+    wire           wbs_s6_stb_o ;
+    wire [31:0]    wbs_s6_adr_o ;
+    wire           wbs_s6_we_o  ;
+    wire [31:0]    wbs_s6_dat_o ;
+    wire [3:0]     wbs_s6_sel_o ;
+    wire [31:0]    wbs_s6_dat_i ;
+    wire           wbs_s6_ack_i ;
+    
+    // Wishbone SLV 7 interface
+    wire           wbs_s7_cyc_o ;
+    wire           wbs_s7_stb_o ;
+    wire [31:0]    wbs_s7_adr_o ;
+    wire           wbs_s7_we_o  ;
+    wire [31:0]    wbs_s7_dat_o ;
+    wire [3:0]     wbs_s7_sel_o ;
+    wire [31:0]    wbs_s7_dat_i ;
+    wire           wbs_s7_ack_i ;
 
     // IO
     assign io_out = {(`MPRJ_IO_PADS){1'b0}};
@@ -86,26 +144,163 @@
 
     assign rst_n = ~wb_rst_i;
 	
+	wishbone_1mst_to_8slv #(
+      .ADDR_S0(32'h30000000), // Base address of Wishbone SLV 0
+      .MASK_S0(32'hFFFF0000), // Mask address of Wishbone SLV 0
+      .ADDR_S1(32'h30010000), // Base address of Wishbone SLV 1
+      .MASK_S1(32'hFFFF0000), // Mask address of Wishbone SLV 1
+      .ADDR_S2(32'h30020000), // Base address of Wishbone SLV 2
+      .MASK_S2(32'hFFFF0000), // Mask address of Wishbone SLV 2
+      .ADDR_S3(32'h30030000), // Base address of Wishbone SLV 3
+      .MASK_S3(32'hFFFF0000), // Mask address of Wishbone SLV 3
+      .ADDR_S4(32'h30040000), // Base address of Wishbone SLV 4
+      .MASK_S4(32'hFFFF0000), // Mask address of Wishbone SLV 4
+      .ADDR_S5(32'h30050000), // Base address of Wishbone SLV 5
+      .MASK_S5(32'hFFFF0000), // Mask address of Wishbone SLV 5
+      .ADDR_S6(32'h30060000), // Base address of Wishbone SLV 6
+      .MASK_S6(32'hFFFF0000), // Mask address of Wishbone SLV 6
+      .ADDR_S7(32'h30070000), // Base address of Wishbone SLV 7
+      .MASK_S7(32'hFFFF0000)  // Mask address of Wishbone SLV 7
+    ) i_wishbone_1mst_to_8slv (
+    
+      // Wishbone MST interface
+      .wbs_m_cyc_i(wbs_cyc_i),
+      .wbs_m_stb_i(wbs_stb_i),
+      .wbs_m_adr_i(wbs_adr_i),
+      .wbs_m_we_i (wbs_we_i ),
+      .wbs_m_dat_i(wbs_dat_i),
+      .wbs_m_sel_i(wbs_sel_i),
+      .wbs_m_dat_o(wbs_dat_o),
+      .wbs_m_ack_o(wbs_ack_o),
+    
+      // Wishbone SLV 0 interface
+      .wbs_s0_cyc_o(wbs_s0_cyc_o),
+      .wbs_s0_stb_o(wbs_s0_stb_o),
+      .wbs_s0_adr_o(wbs_s0_adr_o),
+      .wbs_s0_we_o (wbs_s0_we_o ),
+      .wbs_s0_dat_o(wbs_s0_dat_o),
+      .wbs_s0_sel_o(wbs_s0_sel_o),
+      .wbs_s0_dat_i(wbs_s0_dat_i),
+      .wbs_s0_ack_i(wbs_s0_ack_i),
+    
+      // Wishbone SLV 1 interface
+      .wbs_s1_cyc_o(wbs_s1_cyc_o),
+      .wbs_s1_stb_o(wbs_s1_stb_o),
+      .wbs_s1_adr_o(wbs_s1_adr_o),
+      .wbs_s1_we_o (wbs_s1_we_o ),
+      .wbs_s1_dat_o(wbs_s1_dat_o),
+      .wbs_s1_sel_o(wbs_s1_sel_o),
+      .wbs_s1_dat_i(wbs_s1_dat_i),
+      .wbs_s1_ack_i(wbs_s1_ack_i),
+    
+      // Wishbone SLV 2 interface
+      .wbs_s2_cyc_o(wbs_s2_cyc_o),
+      .wbs_s2_stb_o(wbs_s2_stb_o),
+      .wbs_s2_adr_o(wbs_s2_adr_o),
+      .wbs_s2_we_o (wbs_s2_we_o ),
+      .wbs_s2_dat_o(wbs_s2_dat_o),
+      .wbs_s2_sel_o(wbs_s2_sel_o),
+      .wbs_s2_dat_i(wbs_s2_dat_i),
+      .wbs_s2_ack_i(wbs_s2_ack_i),
+    
+      // Wishbone SLV 3 interface
+      .wbs_s3_cyc_o(wbs_s3_cyc_o),
+      .wbs_s3_stb_o(wbs_s3_stb_o),
+      .wbs_s3_adr_o(wbs_s3_adr_o),
+      .wbs_s3_we_o (wbs_s3_we_o ),
+      .wbs_s3_dat_o(wbs_s3_dat_o),
+      .wbs_s3_sel_o(wbs_s3_sel_o),
+      .wbs_s3_dat_i(wbs_s3_dat_i),
+      .wbs_s3_ack_i(wbs_s3_ack_i),
+    
+      // Wishbone SLV 4 interface
+      .wbs_s4_cyc_o(wbs_s4_cyc_o),
+      .wbs_s4_stb_o(wbs_s4_stb_o),
+      .wbs_s4_adr_o(wbs_s4_adr_o),
+      .wbs_s4_we_o (wbs_s4_we_o ),
+      .wbs_s4_dat_o(wbs_s4_dat_o),
+      .wbs_s4_sel_o(wbs_s4_sel_o),
+      .wbs_s4_dat_i(wbs_s4_dat_i),
+      .wbs_s4_ack_i(wbs_s4_ack_i),
+    
+      // Wishbone SLV 5 interface
+      .wbs_s5_cyc_o(wbs_s5_cyc_o),
+      .wbs_s5_stb_o(wbs_s5_stb_o),
+      .wbs_s5_adr_o(wbs_s5_adr_o),
+      .wbs_s5_we_o (wbs_s5_we_o ),
+      .wbs_s5_dat_o(wbs_s5_dat_o),
+      .wbs_s5_sel_o(wbs_s5_sel_o),
+      .wbs_s5_dat_i(wbs_s5_dat_i),
+      .wbs_s5_ack_i(wbs_s5_ack_i),
+    
+      // Wishbone SLV 6 interface
+      .wbs_s6_cyc_o(wbs_s6_cyc_o),
+      .wbs_s6_stb_o(wbs_s6_stb_o),
+      .wbs_s6_adr_o(wbs_s6_adr_o),
+      .wbs_s6_we_o (wbs_s6_we_o ),
+      .wbs_s6_dat_o(wbs_s6_dat_o),
+      .wbs_s6_sel_o(wbs_s6_sel_o),
+      .wbs_s6_dat_i(wbs_s6_dat_i),
+      .wbs_s6_ack_i(wbs_s6_ack_i),
+    
+      // Wishbone SLV 7 interface
+      .wbs_s7_cyc_o(wbs_s7_cyc_o),
+      .wbs_s7_stb_o(wbs_s7_stb_o),
+      .wbs_s7_adr_o(wbs_s7_adr_o),
+      .wbs_s7_we_o (wbs_s7_we_o ),
+      .wbs_s7_dat_o(wbs_s7_dat_o),
+      .wbs_s7_sel_o(wbs_s7_sel_o),
+      .wbs_s7_dat_i(wbs_s7_dat_i),
+      .wbs_s7_ack_i(wbs_s7_ack_i)
+    
+    );
+	
     nec_ir_receiver #(
       .NB_STAGES (10),
       .PSIZE     (20),
       .DSIZE     (11),
-      .ASIZE     ( 2)
-    ) nec_ir_receiver (
-      .rst_n(rst_n),
-      .clk  (wb_clk_i),
-      .wbs_cyc_i(wbs_cyc_i) ,
-      .wbs_stb_i(wbs_stb_i),
-      .wbs_adr_i(wbs_adr_i),
-      .wbs_we_i (wbs_we_i),
-      .wbs_dat_i(wbs_dat_i),
-      .wbs_sel_i(wbs_sel_i),
-      .wbs_dat_o(wbs_dat_o),
-      .wbs_ack_o(wbs_ack_o),
-      .ir_in(io_in[0]),
-      .irq(irq[0])
+      .ASIZE     ( 4)
+    ) i_nec_ir_receiver (
+      .rst_n    (rst_n       ),
+      .clk      (wb_clk_i    ),
+      .wbs_cyc_i(wbs_s0_cyc_o),
+      .wbs_stb_i(wbs_s0_stb_o),
+      .wbs_adr_i(wbs_s0_adr_o),
+      .wbs_we_i (wbs_s0_we_o ),
+      .wbs_dat_i(wbs_s0_dat_o),
+      .wbs_sel_i(wbs_s0_sel_o),
+      .wbs_dat_o(wbs_s0_dat_i),
+      .wbs_ack_o(wbs_s0_ack_i),
+      .ir_in    (io_in[37]   ),
+      .irq      (irq[0]      )
     );
+	
+	pseudorandom i_pseudorandom (
+      .rst_n     (rst_n       ),
+      .clk       (wb_clk_i    ),
+
+      // Wishbone bus
+      .wbs_cyc_i (wbs_s1_cyc_o),
+      .wbs_stb_i (wbs_s1_stb_o),
+      .wbs_adr_i (wbs_s1_adr_o),
+      .wbs_we_i  (wbs_s1_we_o ),
+      .wbs_dat_i (wbs_s1_dat_o),
+      .wbs_sel_i (wbs_s1_sel_o),
+      .wbs_dat_o (wbs_s1_dat_i),
+      .wbs_ack_o (wbs_s1_ack_i) 
+    );
+	
+    assign wbs_s2_dat_i = 32'h00000000;
+    assign wbs_s3_dat_i = 32'h00000000;
+    assign wbs_s4_dat_i = 32'h00000000;
+    assign wbs_s5_dat_i = 32'h00000000;
+    assign wbs_s6_dat_i = 32'h00000000;
+    assign wbs_s7_dat_i = 32'h00000000;
+    assign wbs_s2_ack_i = wbs_s2_stb_o;
+    assign wbs_s3_ack_i = wbs_s3_stb_o;
+    assign wbs_s4_ack_i = wbs_s4_stb_o;
+    assign wbs_s5_ack_i = wbs_s5_stb_o;
+    assign wbs_s6_ack_i = wbs_s6_stb_o;
+    assign wbs_s7_ack_i = wbs_s7_stb_o;
 
 endmodule
-
-`default_nettype wire
diff --git a/verilog/rtl/wishbone_1mst_to_8slv.v b/verilog/rtl/wishbone_1mst_to_8slv.v
new file mode 100644
index 0000000..f879c42
--- /dev/null
+++ b/verilog/rtl/wishbone_1mst_to_8slv.v
@@ -0,0 +1,233 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , Julien OURY                       
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+//
+////////////////////////////////////////////////////////////////////////////
+
+module wishbone_1mst_to_8slv #(
+  parameter [31:0] ADDR_S0 = 32'h00000000 , // Base address of Wishbone SLV 0
+  parameter [31:0] MASK_S0 = 32'hFFFFFFFF , // Mask address of Wishbone SLV 0
+  parameter [31:0] ADDR_S1 = 32'h00000000 , // Base address of Wishbone SLV 1
+  parameter [31:0] MASK_S1 = 32'hFFFFFFFF , // Mask address of Wishbone SLV 1
+  parameter [31:0] ADDR_S2 = 32'h00000000 , // Base address of Wishbone SLV 2
+  parameter [31:0] MASK_S2 = 32'hFFFFFFFF , // Mask address of Wishbone SLV 2
+  parameter [31:0] ADDR_S3 = 32'h00000000 , // Base address of Wishbone SLV 3
+  parameter [31:0] MASK_S3 = 32'hFFFFFFFF , // Mask address of Wishbone SLV 3
+  parameter [31:0] ADDR_S4 = 32'h00000000 , // Base address of Wishbone SLV 4
+  parameter [31:0] MASK_S4 = 32'hFFFFFFFF , // Mask address of Wishbone SLV 4
+  parameter [31:0] ADDR_S5 = 32'h00000000 , // Base address of Wishbone SLV 5
+  parameter [31:0] MASK_S5 = 32'hFFFFFFFF , // Mask address of Wishbone SLV 5
+  parameter [31:0] ADDR_S6 = 32'h00000000 , // Base address of Wishbone SLV 6
+  parameter [31:0] MASK_S6 = 32'hFFFFFFFF , // Mask address of Wishbone SLV 6
+  parameter [31:0] ADDR_S7 = 32'h00000000 , // Base address of Wishbone SLV 7
+  parameter [31:0] MASK_S7 = 32'hFFFFFFFF   // Mask address of Wishbone SLV 7
+)(
+  
+  // Wishbone MST interface
+  input  wire           wbs_m_cyc_i  , // Wishbone MST strobe/request
+  input  wire           wbs_m_stb_i  , // Wishbone MST strobe/request
+  input  wire [31:0]    wbs_m_adr_i  , // Wishbone MST address
+  input  wire           wbs_m_we_i   , // Wishbone MST write (1:write, 0:read)
+  input  wire [31:0]    wbs_m_dat_i  , // Wishbone MST data output
+  input  wire [3:0]     wbs_m_sel_i  , // Wishbone MST byte enable
+  output reg  [31:0]    wbs_m_dat_o  , // Wishbone MST data input
+  output reg            wbs_m_ack_o  , // Wishbone MST acknowlegement
+
+  // Wishbone SLV 0 interface
+  output wire           wbs_s0_cyc_o , // Wishbone SLV 0 strobe/request
+  output wire           wbs_s0_stb_o , // Wishbone SLV 0 strobe/request
+  output wire [31:0]    wbs_s0_adr_o , // Wishbone SLV 0 address
+  output wire           wbs_s0_we_o  , // Wishbone SLV 0 write (1:write, 0:read)
+  output wire [31:0]    wbs_s0_dat_o , // Wishbone SLV 0 data output
+  output wire [3:0]     wbs_s0_sel_o , // Wishbone SLV 0 byte enable
+  input  wire [31:0]    wbs_s0_dat_i , // Wishbone SLV 0 data input
+  input  wire           wbs_s0_ack_i , // Wishbone SLV 0 acknowlegement
+
+  // Wishbone SLV 1 interface
+  output wire           wbs_s1_cyc_o , // Wishbone SLV 1 strobe/request
+  output wire           wbs_s1_stb_o , // Wishbone SLV 1 strobe/request
+  output wire [31:0]    wbs_s1_adr_o , // Wishbone SLV 1 address
+  output wire           wbs_s1_we_o  , // Wishbone SLV 1 write (1:write, 0:read)
+  output wire [31:0]    wbs_s1_dat_o , // Wishbone SLV 1 data output
+  output wire [3:0]     wbs_s1_sel_o , // Wishbone SLV 1 byte enable
+  input  wire [31:0]    wbs_s1_dat_i , // Wishbone SLV 1 data input
+  input  wire           wbs_s1_ack_i , // Wishbone SLV 1 acknowlegement
+
+  // Wishbone SLV 2 interface
+  output wire           wbs_s2_cyc_o , // Wishbone SLV 2 strobe/request
+  output wire           wbs_s2_stb_o , // Wishbone SLV 2 strobe/request
+  output wire [31:0]    wbs_s2_adr_o , // Wishbone SLV 2 address
+  output wire           wbs_s2_we_o  , // Wishbone SLV 2 write (1:write, 0:read)
+  output wire [31:0]    wbs_s2_dat_o , // Wishbone SLV 2 data output
+  output wire [3:0]     wbs_s2_sel_o , // Wishbone SLV 2 byte enable
+  input  wire [31:0]    wbs_s2_dat_i , // Wishbone SLV 2 data input
+  input  wire           wbs_s2_ack_i , // Wishbone SLV 2 acknowlegement
+
+  // Wishbone SLV 3 interface
+  output wire           wbs_s3_cyc_o , // Wishbone SLV 3 strobe/request
+  output wire           wbs_s3_stb_o , // Wishbone SLV 3 strobe/request
+  output wire [31:0]    wbs_s3_adr_o , // Wishbone SLV 3 address
+  output wire           wbs_s3_we_o  , // Wishbone SLV 3 write (1:write, 0:read)
+  output wire [31:0]    wbs_s3_dat_o , // Wishbone SLV 3 data output
+  output wire [3:0]     wbs_s3_sel_o , // Wishbone SLV 3 byte enable
+  input  wire [31:0]    wbs_s3_dat_i , // Wishbone SLV 3 data input
+  input  wire           wbs_s3_ack_i , // Wishbone SLV 3 acknowlegement
+
+  // Wishbone SLV 4 interface
+  output wire           wbs_s4_cyc_o , // Wishbone SLV 4 strobe/request
+  output wire           wbs_s4_stb_o , // Wishbone SLV 4 strobe/request
+  output wire [31:0]    wbs_s4_adr_o , // Wishbone SLV 4 address
+  output wire           wbs_s4_we_o  , // Wishbone SLV 4 write (1:write, 0:read)
+  output wire [31:0]    wbs_s4_dat_o , // Wishbone SLV 4 data output
+  output wire [3:0]     wbs_s4_sel_o , // Wishbone SLV 4 byte enable
+  input  wire [31:0]    wbs_s4_dat_i , // Wishbone SLV 4 data input
+  input  wire           wbs_s4_ack_i , // Wishbone SLV 4 acknowlegement
+
+  // Wishbone SLV 5 interface
+  output wire           wbs_s5_cyc_o , // Wishbone SLV 5 strobe/request
+  output wire           wbs_s5_stb_o , // Wishbone SLV 5 strobe/request
+  output wire [31:0]    wbs_s5_adr_o , // Wishbone SLV 5 address
+  output wire           wbs_s5_we_o  , // Wishbone SLV 5 write (1:write, 0:read)
+  output wire [31:0]    wbs_s5_dat_o , // Wishbone SLV 5 data output
+  output wire [3:0]     wbs_s5_sel_o , // Wishbone SLV 5 byte enable
+  input  wire [31:0]    wbs_s5_dat_i , // Wishbone SLV 5 data input
+  input  wire           wbs_s5_ack_i , // Wishbone SLV 5 acknowlegement
+
+  // Wishbone SLV 6 interface
+  output wire           wbs_s6_cyc_o , // Wishbone SLV 6 strobe/request
+  output wire           wbs_s6_stb_o , // Wishbone SLV 6 strobe/request
+  output wire [31:0]    wbs_s6_adr_o , // Wishbone SLV 6 address
+  output wire           wbs_s6_we_o  , // Wishbone SLV 6 write (1:write, 0:read)
+  output wire [31:0]    wbs_s6_dat_o , // Wishbone SLV 6 data output
+  output wire [3:0]     wbs_s6_sel_o , // Wishbone SLV 6 byte enable
+  input  wire [31:0]    wbs_s6_dat_i , // Wishbone SLV 6 data input
+  input  wire           wbs_s6_ack_i , // Wishbone SLV 6 acknowlegement
+
+  // Wishbone SLV 7 interface
+  output wire           wbs_s7_cyc_o , // Wishbone SLV 7 strobe/request
+  output wire           wbs_s7_stb_o , // Wishbone SLV 7 strobe/request
+  output wire [31:0]    wbs_s7_adr_o , // Wishbone SLV 7 address
+  output wire           wbs_s7_we_o  , // Wishbone SLV 7 write (1:write, 0:read)
+  output wire [31:0]    wbs_s7_dat_o , // Wishbone SLV 7 data output
+  output wire [3:0]     wbs_s7_sel_o , // Wishbone SLV 7 byte enable
+  input  wire [31:0]    wbs_s7_dat_i , // Wishbone SLV 7 data input
+  input  wire           wbs_s7_ack_i   // Wishbone SLV 7 acknowlegement
+
+);
+
+  wire [7:0] selected;
+
+  assign selected[0] = ((wbs_m_adr_i & MASK_S0) == (ADDR_S0 & MASK_S0)) ? 1'b1 : 1'b0;
+  assign selected[1] = ((wbs_m_adr_i & MASK_S1) == (ADDR_S1 & MASK_S1)) ? 1'b1 : 1'b0;
+  assign selected[2] = ((wbs_m_adr_i & MASK_S2) == (ADDR_S2 & MASK_S2)) ? 1'b1 : 1'b0;
+  assign selected[3] = ((wbs_m_adr_i & MASK_S3) == (ADDR_S3 & MASK_S3)) ? 1'b1 : 1'b0;
+  assign selected[4] = ((wbs_m_adr_i & MASK_S4) == (ADDR_S4 & MASK_S4)) ? 1'b1 : 1'b0;
+  assign selected[5] = ((wbs_m_adr_i & MASK_S5) == (ADDR_S5 & MASK_S5)) ? 1'b1 : 1'b0;
+  assign selected[6] = ((wbs_m_adr_i & MASK_S6) == (ADDR_S6 & MASK_S6)) ? 1'b1 : 1'b0;
+  assign selected[7] = ((wbs_m_adr_i & MASK_S7) == (ADDR_S7 & MASK_S7)) ? 1'b1 : 1'b0;
+
+  assign wbs_s0_cyc_o = (selected[0] == 1'b1) ? wbs_m_cyc_i : 1'b0;
+  assign wbs_s1_cyc_o = (selected[1] == 1'b1) ? wbs_m_cyc_i : 1'b0;
+  assign wbs_s2_cyc_o = (selected[2] == 1'b1) ? wbs_m_cyc_i : 1'b0;
+  assign wbs_s3_cyc_o = (selected[3] == 1'b1) ? wbs_m_cyc_i : 1'b0;
+  assign wbs_s4_cyc_o = (selected[4] == 1'b1) ? wbs_m_cyc_i : 1'b0;
+  assign wbs_s5_cyc_o = (selected[5] == 1'b1) ? wbs_m_cyc_i : 1'b0;
+  assign wbs_s6_cyc_o = (selected[6] == 1'b1) ? wbs_m_cyc_i : 1'b0;
+  assign wbs_s7_cyc_o = (selected[7] == 1'b1) ? wbs_m_cyc_i : 1'b0;
+  
+  assign wbs_s0_stb_o = (selected[0] == 1'b1) ? wbs_m_stb_i : 1'b0;
+  assign wbs_s1_stb_o = (selected[1] == 1'b1) ? wbs_m_stb_i : 1'b0;
+  assign wbs_s2_stb_o = (selected[2] == 1'b1) ? wbs_m_stb_i : 1'b0;
+  assign wbs_s3_stb_o = (selected[3] == 1'b1) ? wbs_m_stb_i : 1'b0;
+  assign wbs_s4_stb_o = (selected[4] == 1'b1) ? wbs_m_stb_i : 1'b0;
+  assign wbs_s5_stb_o = (selected[5] == 1'b1) ? wbs_m_stb_i : 1'b0;
+  assign wbs_s6_stb_o = (selected[6] == 1'b1) ? wbs_m_stb_i : 1'b0;
+  assign wbs_s7_stb_o = (selected[7] == 1'b1) ? wbs_m_stb_i : 1'b0;
+  
+  assign wbs_s0_adr_o = wbs_m_adr_i;
+  assign wbs_s1_adr_o = wbs_m_adr_i;
+  assign wbs_s2_adr_o = wbs_m_adr_i;
+  assign wbs_s3_adr_o = wbs_m_adr_i;
+  assign wbs_s4_adr_o = wbs_m_adr_i;
+  assign wbs_s5_adr_o = wbs_m_adr_i;
+  assign wbs_s6_adr_o = wbs_m_adr_i;
+  assign wbs_s7_adr_o = wbs_m_adr_i;
+  
+  assign wbs_s0_we_o = wbs_m_we_i;
+  assign wbs_s1_we_o = wbs_m_we_i;
+  assign wbs_s2_we_o = wbs_m_we_i;
+  assign wbs_s3_we_o = wbs_m_we_i;
+  assign wbs_s4_we_o = wbs_m_we_i;
+  assign wbs_s5_we_o = wbs_m_we_i;
+  assign wbs_s6_we_o = wbs_m_we_i;
+  assign wbs_s7_we_o = wbs_m_we_i;
+  
+  assign wbs_s0_dat_o = wbs_m_dat_i;
+  assign wbs_s1_dat_o = wbs_m_dat_i;
+  assign wbs_s2_dat_o = wbs_m_dat_i;
+  assign wbs_s3_dat_o = wbs_m_dat_i;
+  assign wbs_s4_dat_o = wbs_m_dat_i;
+  assign wbs_s5_dat_o = wbs_m_dat_i;
+  assign wbs_s6_dat_o = wbs_m_dat_i;
+  assign wbs_s7_dat_o = wbs_m_dat_i;
+  
+  assign wbs_s0_sel_o = wbs_m_sel_i;
+  assign wbs_s1_sel_o = wbs_m_sel_i;
+  assign wbs_s2_sel_o = wbs_m_sel_i;
+  assign wbs_s3_sel_o = wbs_m_sel_i;
+  assign wbs_s4_sel_o = wbs_m_sel_i;
+  assign wbs_s5_sel_o = wbs_m_sel_i;
+  assign wbs_s6_sel_o = wbs_m_sel_i;
+  assign wbs_s7_sel_o = wbs_m_sel_i;
+
+  always @(*) begin
+      case (selected)
+      8'b10000000 : begin
+        wbs_m_dat_o  <= wbs_s7_dat_i;
+        wbs_m_ack_o  <= wbs_s7_ack_i;
+      end
+      8'b01000000 : begin
+        wbs_m_dat_o  <= wbs_s6_dat_i;
+        wbs_m_ack_o  <= wbs_s6_ack_i;
+      end
+      8'b00100000 : begin
+        wbs_m_dat_o  <= wbs_s5_dat_i;
+        wbs_m_ack_o  <= wbs_s5_ack_i;
+      end
+      8'b00010000 : begin
+        wbs_m_dat_o  <= wbs_s4_dat_i;
+        wbs_m_ack_o  <= wbs_s4_ack_i;
+      end
+      8'b00001000 : begin
+        wbs_m_dat_o  <= wbs_s3_dat_i;
+        wbs_m_ack_o  <= wbs_s3_ack_i;
+      end
+      8'b00000100 : begin
+        wbs_m_dat_o  <= wbs_s2_dat_i;
+        wbs_m_ack_o  <= wbs_s2_ack_i;
+      end
+      8'b00000010 : begin
+        wbs_m_dat_o  <= wbs_s1_dat_i;
+        wbs_m_ack_o  <= wbs_s1_ack_i;
+      end
+      default : begin
+        wbs_m_dat_o  <= wbs_s0_dat_i;
+        wbs_m_ack_o  <= wbs_s0_ack_i;
+      end
+    endcase
+  end
+
+endmodule
\ No newline at end of file