)]}'
{
  "commit": "7f85918749d1495b17e7d51f9868c3f8b410aa78",
  "tree": "0e82bce5a02635a76cc0a93f3259b2930597d068",
  "parents": [
    "ed7bb6beef4ec18b5b2067ce0b141e999dcad586"
  ],
  "author": {
    "name": "JulienOury",
    "email": "julien.oury@outlook.fr",
    "time": "Thu Mar 17 08:25:03 2022 +0100"
  },
  "committer": {
    "name": "JulienOury",
    "email": "julien.oury@outlook.fr",
    "time": "Thu Mar 17 08:25:03 2022 +0100"
  },
  "message": "Add step motor controller\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0809b0ecb7e6b404a6d49d89de05f838a1bcbabd",
      "old_mode": 33261,
      "old_path": "openlane/user_proj_example/config.tcl",
      "new_id": "3d46eded1eebd414ca3c00c2eaa38f21391edbda",
      "new_mode": 33261,
      "new_path": "openlane/user_proj_example/config.tcl"
    },
    {
      "type": "modify",
      "old_id": "039a4cdb94ff735595c72a65b169304a9d4bcb69",
      "old_mode": 33188,
      "old_path": "verilog/includes/includes.rtl.caravel_user_project",
      "new_id": "eb04dc0090c8915d689e9c50e53ad026302c7cd5",
      "new_mode": 33188,
      "new_path": "verilog/includes/includes.rtl.caravel_user_project"
    },
    {
      "type": "modify",
      "old_id": "f1df164726818d17b2aa7bcf399846a0462a52d2",
      "old_mode": 33188,
      "old_path": "verilog/rtl/nec_ir_receiver.v",
      "new_id": "26d3f9284e4bf6e34b7d3c858a4ce6ab7fba40f6",
      "new_mode": 33188,
      "new_path": "verilog/rtl/nec_ir_receiver.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "333f18ea6e499db36f7e2a154729d4da1c863ec9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/prescaler.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "71a0c5094b5c7c1a9e4a4acc636a41b14b13606c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/step_motor_controller.v"
    },
    {
      "type": "modify",
      "old_id": "2d55d6e39a0b882533709b4eb7a63eb0c40f2a65",
      "old_mode": 33188,
      "old_path": "verilog/rtl/uprj_netlists.v",
      "new_id": "b8676ada6a8e683aaf8a80df91dd9938e2feef55",
      "new_mode": 33188,
      "new_path": "verilog/rtl/uprj_netlists.v"
    },
    {
      "type": "modify",
      "old_id": "7f8a6728903651c0b06b593755ee07a5374b42ee",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_proj_example.v",
      "new_id": "5c5299bc812382b3d9e2f3b47d0932bee6ada5f4",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_proj_example.v"
    }
  ]
}