diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 0809b0e..3d46ede 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -24,9 +24,11 @@
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
 	$script_dir/../../verilog/rtl/user_proj_example.v \
 	$script_dir/../../verilog/rtl/wishbone_1mst_to_8slv.v \
+	$script_dir/../../verilog/rtl/prescaler.v \
 	$script_dir/../../verilog/rtl/simple_fifo.v \
 	$script_dir/../../verilog/rtl/nec_ir_receiver.v \
-	$script_dir/../../verilog/rtl/pseudorandom.v"
+	$script_dir/../../verilog/rtl/pseudorandom.v \
+	$script_dir/../../verilog/rtl/step_motor_controller.v"
 
 set ::env(DESIGN_IS_CORE) 0
 
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 039a4cd..eb04dc0 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -2,8 +2,10 @@
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
 -v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
 -v $(USER_PROJECT_VERILOG)/rtl/wishbone_1mst_to_8slv.v
+-v $(USER_PROJECT_VERILOG)/rtl/prescaler.v
 -v $(USER_PROJECT_VERILOG)/rtl/simple_fifo.v
 -v $(USER_PROJECT_VERILOG)/rtl/nec_ir_receiver.v
 -v $(USER_PROJECT_VERILOG)/rtl/pseudorandom.v
+-v $(USER_PROJECT_VERILOG)/rtl/step_motor_controller.v
 -v $(USER_PROJECT_VERILOG)/beh/ir_behavioral_driver.v
  
diff --git a/verilog/rtl/nec_ir_receiver.v b/verilog/rtl/nec_ir_receiver.v
index f1df164..26d3f92 100644
--- a/verilog/rtl/nec_ir_receiver.v
+++ b/verilog/rtl/nec_ir_receiver.v
@@ -156,10 +156,10 @@
     .rd_ready(frame_read     )
   );
 
-  registers #(
+  nec_ir_receiver_registers #(
     .PSIZE(PSIZE),
     .DSIZE(DSIZE)
-  ) i_registers (
+  ) i_nec_ir_receiver_registers (
     .rst_n   (rst_n),
     .clk     (clk  ),
 
@@ -199,50 +199,6 @@
 endmodule
 
 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// Prescaler
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-module prescaler #(
-  parameter BITS = 32
-)(
-  input  wire            rst_n      , // Asynchronous reset (active low)
-  input  wire            clk        , // Clock (rising edge)
-  input  wire            clear_n  , // Synchronous reset (active low)
-
-  input  wire [BITS-1:0] multiplier , // frequency multiplier
-  input  wire [BITS-1:0] divider    , // frequency divider
-
-  output reg             tick         // output clock [Ftick=Fclk*(multiplier/divider)] with multiplier <= divider
-
-);
-
-  wire [BITS-1:0] next_counter;
-  reg  [BITS-1:0] counter;
-
-  assign next_counter = counter + multiplier;
-
-  always @(negedge rst_n or posedge clk) begin
-    if (rst_n == 1'b0) begin
-      counter <= 1'b0;
-      tick    <= 1'b0;
-    end else begin
-      if (clear_n == 1'b0) begin
-        counter <= 1'b0;
-        tick    <= 1'b0;
-      end else begin
-        if (next_counter > divider) begin
-          counter <= next_counter - divider;
-          tick    <= 1'b1;
-        end else begin
-          counter <= next_counter;
-          tick    <= 1'b0;
-        end
-      end
-    end
-  end
-
-endmodule
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // Metastability filter
 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 module metastability_filter #(
@@ -559,7 +515,7 @@
 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // Registers
 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-module registers #(
+module nec_ir_receiver_registers #(
   parameter PSIZE = 32          , // Size of prescaler counter(bits)
   parameter DSIZE = 11            // Size of delay counter (bits)
 )(
diff --git a/verilog/rtl/prescaler.v b/verilog/rtl/prescaler.v
new file mode 100644
index 0000000..333f18e
--- /dev/null
+++ b/verilog/rtl/prescaler.v
@@ -0,0 +1,59 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , Julien OURY                       
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+//
+////////////////////////////////////////////////////////////////////////////
+
+module prescaler #(
+  parameter BITS = 32
+)(
+  input  wire            rst_n      , // Asynchronous reset (active low)
+  input  wire            clk        , // Clock (rising edge)
+  input  wire            clear_n  , // Synchronous reset (active low)
+
+  input  wire [BITS-1:0] multiplier , // frequency multiplier
+  input  wire [BITS-1:0] divider    , // frequency divider
+
+  output reg             tick         // output clock [Ftick=Fclk*(multiplier/divider)] with multiplier <= divider
+
+);
+
+  wire [BITS-1:0] next_counter;
+  reg  [BITS-1:0] counter;
+
+  assign next_counter = counter + multiplier;
+
+  always @(negedge rst_n or posedge clk) begin
+    if (rst_n == 1'b0) begin
+      counter <= 1'b0;
+      tick    <= 1'b0;
+    end else begin
+      if (clear_n == 1'b0) begin
+        counter <= 1'b0;
+        tick    <= 1'b0;
+      end else begin
+        if (next_counter > divider) begin
+          counter <= next_counter - divider;
+          tick    <= 1'b1;
+        end else begin
+          counter <= next_counter;
+          tick    <= 1'b0;
+        end
+      end
+    end
+  end
+
+endmodule
diff --git a/verilog/rtl/step_motor_controller.v b/verilog/rtl/step_motor_controller.v
new file mode 100644
index 0000000..71a0c50
--- /dev/null
+++ b/verilog/rtl/step_motor_controller.v
@@ -0,0 +1,437 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , Julien OURY                       
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+//
+////////////////////////////////////////////////////////////////////////////
+
+module step_motor_controller #(
+  parameter PSIZE     = 32     , // Size of prescaler counter(bits)
+  parameter DSIZE     = 16       // Size of delay counter (bits)
+)(
+
+  input  wire        rst_n     , // Asynchronous reset (active low)
+  input  wire        clk       , // Clock (rising edge)
+
+  // Wishbone bus
+  input  wire        wbs_cyc_i , // Wishbone strobe/request
+  input  wire        wbs_stb_i , // Wishbone strobe/request
+  input  wire [31:0] wbs_adr_i , // Wishbone address
+  input  wire        wbs_we_i  , // Wishbone write (1:write, 0:read)
+  input  wire [31:0] wbs_dat_i , // Wishbone data output
+  input  wire [3:0]  wbs_sel_i , // Wishbone byte enable
+  output wire [31:0] wbs_dat_o , // Wishbone data input
+  output wire        wbs_ack_o , // Wishbone acknowlegement
+
+  // Motor outputs
+  output wire        motor_a1  ,  // A1 moto output
+  output wire        motor_a2  ,  // A2 moto output
+  output wire        motor_b1  ,  // B1 moto output
+  output wire        motor_b2     // B2 moto output
+
+);
+
+  wire             controller_en   ;
+  wire [PSIZE-1:0] multiplier      ;
+  wire [PSIZE-1:0] divider         ;
+  wire             tick            ;
+  wire [7:0]       duty_cycle      ;
+  wire             start           ;
+  wire             pwm             ;
+  wire             ptype           ;
+  wire             mode            ;
+  wire             direction       ;
+  wire [DSIZE-1:0] period          ;
+  wire             run             ;
+  wire             step_strobe     ;
+
+  prescaler #(
+    .BITS(PSIZE)
+  ) i_prescaler (
+    .rst_n      (rst_n         ),
+    .clk        (clk           ),
+    .clear_n    (controller_en ),
+    .multiplier (multiplier    ),
+    .divider    (divider       ),
+    .tick       (tick          )
+  );
+  
+  pwm_generator i_pwm_generator (
+    .rst_n      (rst_n         ),
+    .clk        (clk           ),
+    .clear_n    (controller_en ),
+    .duty_cycle (duty_cycle    ),
+    .tick       (tick          ),
+    .start      (start         ),
+    .pwm        (pwm           )
+  );
+  
+  motor_sequencer #(
+    .DSIZE(DSIZE)
+  )i_motor_sequencer (
+    .rst_n      (rst_n         ),
+    .clk        (clk           ),
+    .clear_n    (controller_en ),
+    .ptype      (ptype         ),
+    .mode       (mode          ),
+    .direction  (direction     ),
+    .period     (period        ),
+    .run        (run           ),
+    .step_strobe(step_strobe   ),
+    .start      (start         ),
+    .pwm        (pwm           ),
+    .motor_a1   (motor_a1      ),
+    .motor_a2   (motor_a2      ),
+    .motor_b1   (motor_b1      ),
+    .motor_b2   (motor_b2      )
+  );
+  
+  step_motor_controller_registers #(
+    .PSIZE(PSIZE),
+    .DSIZE(DSIZE)
+  ) i_step_motor_controller_registers (
+    .rst_n        (rst_n        ),
+    .clk          (clk          ),
+    .controller_en(controller_en),
+    .multiplier   (multiplier   ),
+    .divider      (divider      ),
+    .duty_cycle   (duty_cycle   ),
+    .ptype        (ptype        ),
+    .mode         (mode         ),
+    .direction    (direction    ),
+    .period       (period       ),
+    .run          (run          ),
+    .step_strobe  (step_strobe  ),
+    .wbs_cyc_i    (wbs_cyc_i    ),
+    .wbs_stb_i    (wbs_stb_i    ),
+    .wbs_adr_i    (wbs_adr_i    ),
+    .wbs_we_i     (wbs_we_i     ),
+    .wbs_dat_i    (wbs_dat_i    ),
+    .wbs_sel_i    (wbs_sel_i    ),
+    .wbs_dat_o    (wbs_dat_o    ),
+    .wbs_ack_o    (wbs_ack_o    )
+  );
+
+endmodule
+
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// PWM generator
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+module pwm_generator (
+  input  wire        rst_n      , // Asynchronous reset (active low)
+  input  wire        clk        , // Clock (rising edge)
+  input  wire        clear_n    , // Synchronous reset (active low)
+  input  wire [7:0]  duty_cycle , // PWM duty cycle
+  input  wire        tick       , // Input tick (PWM resolution)
+  output reg         start      , // Start strobe (One clk pulse at start of PWM period)
+  output reg         pwm          // PWM signal
+);
+
+  wire [7:0] next_counter;
+  reg  [7:0] counter;
+
+  assign next_counter = counter + 1'b1;
+
+  always @(negedge rst_n or posedge clk) begin
+    if (rst_n == 1'b0) begin
+      counter <= 8'h00;
+      start   <= 1'b0;
+      pwm     <= 1'b0;
+    end else begin
+      if (clear_n == 1'b0) begin
+        counter <= 8'h00;
+        start   <= 1'b0;
+        pwm     <= 1'b0;
+      end else begin
+        if (tick == 1'b1) begin
+          counter <= next_counter;
+        end
+        if ((tick == 1'b1) && (counter[7] == 1'b1) && (next_counter[7] == 1'b0)) begin
+          start <= 1'b1;
+        end else begin
+          start <= 1'b0;
+        end
+        if (counter <= duty_cycle) begin
+          pwm <= 1'b1;
+        end else begin
+          pwm <= 1'b0;
+        end
+      end
+    end
+  end
+
+endmodule
+
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Motor_sequencer
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+module motor_sequencer #(
+  parameter DSIZE = 16 // Number of bits of delay counter
+)(
+  input  wire             rst_n         , // Asynchronous reset (active low)
+  input  wire             clk           , // Clock (rising edge)
+  input  wire             clear_n       , // Synchronous reset (active low)
+  input  wire             ptype         , // Type of motor (1'b0:Unipolar, 1'b1:Bipolar)
+  input  wire             mode          , // Mode of drive (1'b0:FullStep, 1'b1:HalfStep)
+  input  wire             direction     , // Direction of motor
+  input  wire [DSIZE-1:0] period        , // Period of each motor step
+  input  wire             run           , // Motor run
+  output reg              step_strobe   , // Motor step strobe (one clk pulse by step)
+
+  // PWM input
+  input  wire             start         , // Start strobe (One clk pulse at start of PWM period)
+  input  wire             pwm           , // PWM signal
+
+  // Motor outputs
+  output reg              motor_a1      , // A1 motor output
+  output reg              motor_a2      , // A2 motor output
+  output reg              motor_b1      , // B1 motor output
+  output reg              motor_b2        // B2 motor output
+);
+
+  reg  [2:0]       motor_state;
+  reg  [DSIZE-1:0] counter;
+  reg              pwmo;
+  
+  wire [DSIZE-1:0] next_counter;
+  wire [3:0]       motor_values[7:0];
+  
+  assign next_counter = counter + 1'b1;
+  assign motor_values[0] = 4'b1_0_0_1; // b2 b1 a2 a1
+  assign motor_values[1] = 4'b0_0_0_1; // b2 b1 a2 a1
+  assign motor_values[2] = 4'b0_0_1_1; // b2 b1 a2 a1
+  assign motor_values[3] = 4'b0_0_1_0; // b2 b1 a2 a1
+  assign motor_values[4] = 4'b0_1_1_0; // b2 b1 a2 a1
+  assign motor_values[5] = 4'b0_1_0_0; // b2 b1 a2 a1
+  assign motor_values[6] = 4'b1_1_0_0; // b2 b1 a2 a1
+  assign motor_values[7] = 4'b1_0_0_0; // b2 b1 a2 a1
+
+
+  // Frame decoder
+  always @(negedge rst_n or posedge clk) begin
+    if (rst_n == 1'b0) begin
+      counter     <= {(DSIZE){1'b0}};
+      step_strobe <= 1'b0;
+      pwmo        <= 1'b0;
+      motor_state <= 3'b000;
+      motor_a1    <= 1'b0;
+      motor_a2    <= 1'b0;
+      motor_b1    <= 1'b0;
+      motor_b2    <= 1'b0;
+    end else begin
+
+      if (clear_n == 1'b0) begin
+        counter     <= {(DSIZE){1'b0}};
+        step_strobe <= 1'b0;
+        pwmo        <= 1'b0;
+        motor_state <= 3'b000;
+        motor_a1    <= 1'b0;
+        motor_a2    <= 1'b0;
+        motor_b1    <= 1'b0;
+        motor_b2    <= 1'b0;
+      end else begin
+      
+        if (run == 1'b0) begin
+          counter <= {(DSIZE){1'b0}};
+        end else if (start == 1'b1) begin
+          if (counter < period) begin
+            counter <= next_counter;
+          end else begin
+            counter <= {(DSIZE){1'b0}};
+            if (direction == 1'b0) begin
+              motor_state <= motor_state + 1'b1;
+            end else begin
+              motor_state <= motor_state - 1'b1;
+            end
+          end
+        end
+        
+        if ((run == 1'b1) && (start == 1'b1) && (counter >= period)) begin
+          step_strobe <= 1'b1;
+        end else begin
+          step_strobe <= 1'b0;
+        end
+        
+        pwmo <= pwm;
+
+        if (ptype == 1'b0) begin // Unipolar
+          motor_a1 <= motor_values[motor_state & {2'b11, mode}][0] & pwmo ;
+          motor_a2 <= motor_values[motor_state & {2'b11, mode}][1] & pwmo ;
+          motor_b1 <= motor_values[motor_state & {2'b11, mode}][2] & pwmo ;
+          motor_b2 <= motor_values[motor_state & {2'b11, mode}][3] & pwmo ;
+        end else begin // Bipolar
+          motor_a1 <= motor_values[motor_state & {2'b11, mode}][0] & pwmo ;
+          motor_a2 <= motor_values[motor_state & {2'b11, mode}][2] & pwmo ;
+          motor_b1 <= motor_values[motor_state & {2'b11, mode}][1] & pwmo ;
+          motor_b2 <= motor_values[motor_state & {2'b11, mode}][3] & pwmo ;
+        end
+
+      end
+    end
+  end
+
+endmodule
+
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Registers
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+module step_motor_controller_registers #(
+  parameter PSIZE = 32          , // Size of prescaler counter(bits)
+  parameter DSIZE = 16            // Size of delay counter (bits)
+)(
+
+  input                   rst_n           , // Asynchronous reset (active low)
+  input                   clk             , // Clock (rising edge)
+
+  // Configuration
+  output reg              controller_en   , // Controller enable (active high)
+  output reg  [PSIZE-1:0] multiplier      , // frequency multiplier
+  output reg  [PSIZE-1:0] divider         , // frequency divider
+  output reg  [7:0]       duty_cycle      , // PWM duty cycle
+  output reg              ptype           , // Type of motor (1'b0:Unipolar, 1'b1:Bipolar)
+  output reg              mode            , // Mode of drive (1'b0:FullStep, 1'b1:HalfStep)
+  output reg              direction       , // Direction of motor
+  output reg  [DSIZE-1:0] period          , // Period of each motor step
+  output reg              run             , // Motor run
+  input  wire             step_strobe     , // Motor step strobe (one clk pulse by step)
+
+  // Wishbone bus
+  input  wire             wbs_cyc_i       , // Wishbone strobe/request
+  input  wire             wbs_stb_i       , // Wishbone strobe/request
+  input  wire [31:0]      wbs_adr_i       , // Wishbone address
+  input  wire             wbs_we_i        , // Wishbone write (1:write, 0:read)
+  input  wire [31:0]      wbs_dat_i       , // Wishbone data output
+  input  wire [ 3:0]      wbs_sel_i       , // Wishbone byte enable
+  output reg  [31:0]      wbs_dat_o       , // Wishbone data input
+  output wire             wbs_ack_o         // Wishbone acknowlegement
+
+ );
+
+  localparam
+    config_reg_addr     = 3'b000,
+    multiplier_reg_addr = 3'b001,
+    divider_reg_addr    = 3'b010,
+    period_reg_addr     = 3'b011,
+    step_reg_addr       = 3'b100;
+
+  wire        valid;
+  wire [31:0] wstrb;
+  wire [2:0]  addr;
+  wire [23:0] next_cycles;
+
+  reg         free;
+  reg         ready;
+  reg  [23:0] cycles;
+
+  integer i = 0;
+
+  assign valid     = wbs_cyc_i && wbs_stb_i;
+  assign wstrb     = {{8{wbs_sel_i[3]}}, {8{wbs_sel_i[2]}}, {8{wbs_sel_i[1]}}, {8{wbs_sel_i[0]}}} & {32{wbs_we_i}};
+  assign addr      = wbs_adr_i[4:2];
+  assign wbs_ack_o = ready;
+  
+  assign next_cycles = cycles - 1'b1;
+
+  always @(negedge rst_n or posedge clk) begin
+    if (rst_n == 1'b0) begin
+      ready         <= 1'b0;
+      wbs_dat_o     <= 32'h00000000;
+      controller_en <= 1'b0;
+      ptype         <= 1'b0;
+      mode          <= 1'b0;
+      duty_cycle    <= 8'h00;
+      multiplier    <= {PSIZE{1'b0}};
+      divider       <= {PSIZE{1'b0}};
+      period        <= {DSIZE{1'b0}};
+      run           <= 1'b0;
+      direction     <= 1'b0;
+      free          <= 1'b0;
+      cycles        <= 24'h000000;
+    end else begin
+
+      if (valid && !ready) begin
+
+        //Write
+        case (addr)
+          config_reg_addr : begin
+            wbs_dat_o[31] <= controller_en; if (wstrb[31]) controller_en <= wbs_dat_i[31];
+            wbs_dat_o[30] <= ptype        ; if (wstrb[30]) ptype         <= wbs_dat_i[30];
+            wbs_dat_o[29] <= mode         ; if (wstrb[29]) mode          <= wbs_dat_i[29];
+            wbs_dat_o[ 7] <= duty_cycle[7]; if (wstrb[ 7]) duty_cycle[7] <= wbs_dat_i[ 7];
+            wbs_dat_o[ 6] <= duty_cycle[6]; if (wstrb[ 6]) duty_cycle[6] <= wbs_dat_i[ 6];
+            wbs_dat_o[ 5] <= duty_cycle[5]; if (wstrb[ 5]) duty_cycle[5] <= wbs_dat_i[ 5];
+            wbs_dat_o[ 4] <= duty_cycle[4]; if (wstrb[ 4]) duty_cycle[4] <= wbs_dat_i[ 4];
+            wbs_dat_o[ 3] <= duty_cycle[3]; if (wstrb[ 3]) duty_cycle[3] <= wbs_dat_i[ 3];
+            wbs_dat_o[ 2] <= duty_cycle[2]; if (wstrb[ 2]) duty_cycle[2] <= wbs_dat_i[ 2];
+            wbs_dat_o[ 1] <= duty_cycle[1]; if (wstrb[ 1]) duty_cycle[1] <= wbs_dat_i[ 1];
+            wbs_dat_o[ 0] <= duty_cycle[0]; if (wstrb[ 0]) duty_cycle[0] <= wbs_dat_i[ 0];
+          end
+          multiplier_reg_addr : begin
+            for (i = 0; i < 32; i = i + 1) begin
+              if (i >= PSIZE) begin
+                wbs_dat_o[i] <= 1'b0 ;
+              end else begin
+                wbs_dat_o[i] <= multiplier[i] ; if (wstrb[i]) multiplier[i] <= wbs_dat_i[i];
+              end
+            end
+          end
+          divider_reg_addr : begin
+            for (i = 0; i < 32; i = i + 1) begin
+              if (i >= PSIZE) begin
+                wbs_dat_o[i] <= 1'b0 ;
+              end else begin
+                wbs_dat_o[i] <= divider[i] ; if (wstrb[i]) divider[i] <= wbs_dat_i[i];
+              end
+            end
+          end
+          period_reg_addr : begin
+            for (i = 0; i < 32; i = i + 1) begin
+              if (i >= DSIZE) begin
+                wbs_dat_o[i] <= 1'b0 ;
+              end else begin
+                wbs_dat_o[i] <= period[i] ; if (wstrb[i]) period[i] <= wbs_dat_i[i];
+              end
+            end
+          end
+          step_reg_addr : begin
+            wbs_dat_o[30]   <= direction    ; if (wstrb[30]) direction     <= wbs_dat_i[30];
+            wbs_dat_o[29]   <= free         ; if (wstrb[29]) free          <= wbs_dat_i[29];
+            wbs_dat_o[23:0] <= cycles;
+          end
+        endcase
+
+        ready <= 1'b1;
+      end else begin
+        ready <= 1'b0;
+      end
+      
+      if (valid && !ready && (addr == step_reg_addr) && wstrb[31]) begin
+        run <= wbs_dat_i[31];
+      end else if ((free == 1'b0) && (step_strobe == 1'b1) && (cycles == 24'h000000)) begin
+        run <= 1'b0;
+      end
+      
+      for (i = 0; i < 24; i = i + 1) begin
+        if (valid && !ready && (addr == step_reg_addr) && wstrb[i] && wbs_dat_i[i]) begin
+          cycles[i] <= wbs_dat_i[i];
+        end else if ((run == 1'b1) && (step_strobe == 1'b1) && (cycles != 24'h000000)) begin
+          cycles[i] <= next_cycles[i];
+        end
+      end
+
+    end
+  end
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 2d55d6e..b8676ad 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -25,8 +25,10 @@
 `else
     `include "user_project_wrapper.v"
     `include "user_proj_example.v"
-	`include "wishbone_1mst_to_8slv.v"
+    `include "wishbone_1mst_to_8slv.v"
+    `include "prescaler.v"
     `include "simple_fifo.v"
     `include "nec_ir_receiver.v"
-	`include "pseudorandom.v"
+    `include "pseudorandom.v"
+    `include "step_motor_controller.v"
 `endif
\ No newline at end of file
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 7f8a672..5c5299b 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -20,8 +20,8 @@
 module user_proj_example(
 
 `ifdef USE_POWER_PINS
-    inout  wire vccd1,	// User area 1 1.8V supply
-    inout  wire vssd1,	// User area 1 digital ground
+    inout  wire vccd1,  // User area 1 1.8V supply
+    inout  wire vssd1,  // User area 1 digital ground
 `endif
 
     // Wishbone Slave ports (WB MI A)
@@ -50,257 +50,307 @@
     output wire [2:0] irq
 );
 
-    wire rst_n;
-    
+  wire rst_n;
+  
+  // Wishbone SLV 0 interface
+  wire           wbs_s0_cyc_o ;
+  wire           wbs_s0_stb_o ;
+  wire [31:0]    wbs_s0_adr_o ;
+  wire           wbs_s0_we_o  ;
+  wire [31:0]    wbs_s0_dat_o ;
+  wire [3:0]     wbs_s0_sel_o ;
+  wire [31:0]    wbs_s0_dat_i ;
+  wire           wbs_s0_ack_i ;
+  
+  // Wishbone SLV 1 interface
+  wire           wbs_s1_cyc_o ;
+  wire           wbs_s1_stb_o ;
+  wire [31:0]    wbs_s1_adr_o ;
+  wire           wbs_s1_we_o  ;
+  wire [31:0]    wbs_s1_dat_o ;
+  wire [3:0]     wbs_s1_sel_o ;
+  wire [31:0]    wbs_s1_dat_i ;
+  wire           wbs_s1_ack_i ;
+  
+  // Wishbone SLV 2 interface
+  wire           wbs_s2_cyc_o ;
+  wire           wbs_s2_stb_o ;
+  wire [31:0]    wbs_s2_adr_o ;
+  wire           wbs_s2_we_o  ;
+  wire [31:0]    wbs_s2_dat_o ;
+  wire [3:0]     wbs_s2_sel_o ;
+  wire [31:0]    wbs_s2_dat_i ;
+  wire           wbs_s2_ack_i ;
+  
+  // Wishbone SLV 3 interface
+  wire           wbs_s3_cyc_o ;
+  wire           wbs_s3_stb_o ;
+  wire [31:0]    wbs_s3_adr_o ;
+  wire           wbs_s3_we_o  ;
+  wire [31:0]    wbs_s3_dat_o ;
+  wire [3:0]     wbs_s3_sel_o ;
+  wire [31:0]    wbs_s3_dat_i ;
+  wire           wbs_s3_ack_i ;
+  
+  // Wishbone SLV 4 interface
+  wire           wbs_s4_cyc_o ;
+  wire           wbs_s4_stb_o ;
+  wire [31:0]    wbs_s4_adr_o ;
+  wire           wbs_s4_we_o  ;
+  wire [31:0]    wbs_s4_dat_o ;
+  wire [3:0]     wbs_s4_sel_o ;
+  wire [31:0]    wbs_s4_dat_i ;
+  wire           wbs_s4_ack_i ;
+  
+  // Wishbone SLV 5 interface
+  wire           wbs_s5_cyc_o ;
+  wire           wbs_s5_stb_o ;
+  wire [31:0]    wbs_s5_adr_o ;
+  wire           wbs_s5_we_o  ;
+  wire [31:0]    wbs_s5_dat_o ;
+  wire [3:0]     wbs_s5_sel_o ;
+  wire [31:0]    wbs_s5_dat_i ;
+  wire           wbs_s5_ack_i ;
+  
+  // Wishbone SLV 6 interface
+  wire           wbs_s6_cyc_o ;
+  wire           wbs_s6_stb_o ;
+  wire [31:0]    wbs_s6_adr_o ;
+  wire           wbs_s6_we_o  ;
+  wire [31:0]    wbs_s6_dat_o ;
+  wire [3:0]     wbs_s6_sel_o ;
+  wire [31:0]    wbs_s6_dat_i ;
+  wire           wbs_s6_ack_i ;
+  
+  // Wishbone SLV 7 interface
+  wire           wbs_s7_cyc_o ;
+  wire           wbs_s7_stb_o ;
+  wire [31:0]    wbs_s7_adr_o ;
+  wire           wbs_s7_we_o  ;
+  wire [31:0]    wbs_s7_dat_o ;
+  wire [3:0]     wbs_s7_sel_o ;
+  wire [31:0]    wbs_s7_dat_i ;
+  wire           wbs_s7_ack_i ;
+  
+  // IO
+  assign io_oeb[37:32] = {( 6){1'b0}};
+  assign io_oeb[27: 0] = {(28){1'b0}};
+
+  assign io_oeb[37:32] = {( 6){1'b1}};
+  assign io_oeb[31:28] = {( 4){1'b0}}; // MOTOR outputs
+  assign io_oeb[27: 0] = {(28){1'b1}};
+  
+  // IRQ
+  assign irq[2:1] = 2'b00;  // Unused
+  
+  // LA
+  assign la_data_out = {(128){1'b0}};
+  
+  assign rst_n = ~wb_rst_i;
+  
+  wishbone_1mst_to_8slv #(
+    .ADDR_S0(32'h30000000), // Base address of Wishbone SLV 0
+    .MASK_S0(32'hFFFF0000), // Mask address of Wishbone SLV 0
+    .ADDR_S1(32'h30010000), // Base address of Wishbone SLV 1
+    .MASK_S1(32'hFFFF0000), // Mask address of Wishbone SLV 1
+    .ADDR_S2(32'h30020000), // Base address of Wishbone SLV 2
+    .MASK_S2(32'hFFFF0000), // Mask address of Wishbone SLV 2
+    .ADDR_S3(32'h30030000), // Base address of Wishbone SLV 3
+    .MASK_S3(32'hFFFF0000), // Mask address of Wishbone SLV 3
+    .ADDR_S4(32'h30040000), // Base address of Wishbone SLV 4
+    .MASK_S4(32'hFFFF0000), // Mask address of Wishbone SLV 4
+    .ADDR_S5(32'h30050000), // Base address of Wishbone SLV 5
+    .MASK_S5(32'hFFFF0000), // Mask address of Wishbone SLV 5
+    .ADDR_S6(32'h30060000), // Base address of Wishbone SLV 6
+    .MASK_S6(32'hFFFF0000), // Mask address of Wishbone SLV 6
+    .ADDR_S7(32'h30070000), // Base address of Wishbone SLV 7
+    .MASK_S7(32'hFFFF0000)  // Mask address of Wishbone SLV 7
+  ) i_wishbone_1mst_to_8slv (
+  
+    // Wishbone MST interface
+    .wbs_m_cyc_i(wbs_cyc_i),
+    .wbs_m_stb_i(wbs_stb_i),
+    .wbs_m_adr_i(wbs_adr_i),
+    .wbs_m_we_i (wbs_we_i ),
+    .wbs_m_dat_i(wbs_dat_i),
+    .wbs_m_sel_i(wbs_sel_i),
+    .wbs_m_dat_o(wbs_dat_o),
+    .wbs_m_ack_o(wbs_ack_o),
+  
     // Wishbone SLV 0 interface
-    wire           wbs_s0_cyc_o ;
-    wire           wbs_s0_stb_o ;
-    wire [31:0]    wbs_s0_adr_o ;
-    wire           wbs_s0_we_o  ;
-    wire [31:0]    wbs_s0_dat_o ;
-    wire [3:0]     wbs_s0_sel_o ;
-    wire [31:0]    wbs_s0_dat_i ;
-    wire           wbs_s0_ack_i ;
-    
+    .wbs_s0_cyc_o(wbs_s0_cyc_o),
+    .wbs_s0_stb_o(wbs_s0_stb_o),
+    .wbs_s0_adr_o(wbs_s0_adr_o),
+    .wbs_s0_we_o (wbs_s0_we_o ),
+    .wbs_s0_dat_o(wbs_s0_dat_o),
+    .wbs_s0_sel_o(wbs_s0_sel_o),
+    .wbs_s0_dat_i(wbs_s0_dat_i),
+    .wbs_s0_ack_i(wbs_s0_ack_i),
+  
     // Wishbone SLV 1 interface
-    wire           wbs_s1_cyc_o ;
-    wire           wbs_s1_stb_o ;
-    wire [31:0]    wbs_s1_adr_o ;
-    wire           wbs_s1_we_o  ;
-    wire [31:0]    wbs_s1_dat_o ;
-    wire [3:0]     wbs_s1_sel_o ;
-    wire [31:0]    wbs_s1_dat_i ;
-    wire           wbs_s1_ack_i ;
-    
+    .wbs_s1_cyc_o(wbs_s1_cyc_o),
+    .wbs_s1_stb_o(wbs_s1_stb_o),
+    .wbs_s1_adr_o(wbs_s1_adr_o),
+    .wbs_s1_we_o (wbs_s1_we_o ),
+    .wbs_s1_dat_o(wbs_s1_dat_o),
+    .wbs_s1_sel_o(wbs_s1_sel_o),
+    .wbs_s1_dat_i(wbs_s1_dat_i),
+    .wbs_s1_ack_i(wbs_s1_ack_i),
+  
     // Wishbone SLV 2 interface
-    wire           wbs_s2_cyc_o ;
-    wire           wbs_s2_stb_o ;
-    wire [31:0]    wbs_s2_adr_o ;
-    wire           wbs_s2_we_o  ;
-    wire [31:0]    wbs_s2_dat_o ;
-    wire [3:0]     wbs_s2_sel_o ;
-    wire [31:0]    wbs_s2_dat_i ;
-    wire           wbs_s2_ack_i ;
-    
+    .wbs_s2_cyc_o(wbs_s2_cyc_o),
+    .wbs_s2_stb_o(wbs_s2_stb_o),
+    .wbs_s2_adr_o(wbs_s2_adr_o),
+    .wbs_s2_we_o (wbs_s2_we_o ),
+    .wbs_s2_dat_o(wbs_s2_dat_o),
+    .wbs_s2_sel_o(wbs_s2_sel_o),
+    .wbs_s2_dat_i(wbs_s2_dat_i),
+    .wbs_s2_ack_i(wbs_s2_ack_i),
+  
     // Wishbone SLV 3 interface
-    wire           wbs_s3_cyc_o ;
-    wire           wbs_s3_stb_o ;
-    wire [31:0]    wbs_s3_adr_o ;
-    wire           wbs_s3_we_o  ;
-    wire [31:0]    wbs_s3_dat_o ;
-    wire [3:0]     wbs_s3_sel_o ;
-    wire [31:0]    wbs_s3_dat_i ;
-    wire           wbs_s3_ack_i ;
-    
+    .wbs_s3_cyc_o(wbs_s3_cyc_o),
+    .wbs_s3_stb_o(wbs_s3_stb_o),
+    .wbs_s3_adr_o(wbs_s3_adr_o),
+    .wbs_s3_we_o (wbs_s3_we_o ),
+    .wbs_s3_dat_o(wbs_s3_dat_o),
+    .wbs_s3_sel_o(wbs_s3_sel_o),
+    .wbs_s3_dat_i(wbs_s3_dat_i),
+    .wbs_s3_ack_i(wbs_s3_ack_i),
+  
     // Wishbone SLV 4 interface
-    wire           wbs_s4_cyc_o ;
-    wire           wbs_s4_stb_o ;
-    wire [31:0]    wbs_s4_adr_o ;
-    wire           wbs_s4_we_o  ;
-    wire [31:0]    wbs_s4_dat_o ;
-    wire [3:0]     wbs_s4_sel_o ;
-    wire [31:0]    wbs_s4_dat_i ;
-    wire           wbs_s4_ack_i ;
-    
+    .wbs_s4_cyc_o(wbs_s4_cyc_o),
+    .wbs_s4_stb_o(wbs_s4_stb_o),
+    .wbs_s4_adr_o(wbs_s4_adr_o),
+    .wbs_s4_we_o (wbs_s4_we_o ),
+    .wbs_s4_dat_o(wbs_s4_dat_o),
+    .wbs_s4_sel_o(wbs_s4_sel_o),
+    .wbs_s4_dat_i(wbs_s4_dat_i),
+    .wbs_s4_ack_i(wbs_s4_ack_i),
+  
     // Wishbone SLV 5 interface
-    wire           wbs_s5_cyc_o ;
-    wire           wbs_s5_stb_o ;
-    wire [31:0]    wbs_s5_adr_o ;
-    wire           wbs_s5_we_o  ;
-    wire [31:0]    wbs_s5_dat_o ;
-    wire [3:0]     wbs_s5_sel_o ;
-    wire [31:0]    wbs_s5_dat_i ;
-    wire           wbs_s5_ack_i ;
-    
+    .wbs_s5_cyc_o(wbs_s5_cyc_o),
+    .wbs_s5_stb_o(wbs_s5_stb_o),
+    .wbs_s5_adr_o(wbs_s5_adr_o),
+    .wbs_s5_we_o (wbs_s5_we_o ),
+    .wbs_s5_dat_o(wbs_s5_dat_o),
+    .wbs_s5_sel_o(wbs_s5_sel_o),
+    .wbs_s5_dat_i(wbs_s5_dat_i),
+    .wbs_s5_ack_i(wbs_s5_ack_i),
+  
     // Wishbone SLV 6 interface
-    wire           wbs_s6_cyc_o ;
-    wire           wbs_s6_stb_o ;
-    wire [31:0]    wbs_s6_adr_o ;
-    wire           wbs_s6_we_o  ;
-    wire [31:0]    wbs_s6_dat_o ;
-    wire [3:0]     wbs_s6_sel_o ;
-    wire [31:0]    wbs_s6_dat_i ;
-    wire           wbs_s6_ack_i ;
-    
+    .wbs_s6_cyc_o(wbs_s6_cyc_o),
+    .wbs_s6_stb_o(wbs_s6_stb_o),
+    .wbs_s6_adr_o(wbs_s6_adr_o),
+    .wbs_s6_we_o (wbs_s6_we_o ),
+    .wbs_s6_dat_o(wbs_s6_dat_o),
+    .wbs_s6_sel_o(wbs_s6_sel_o),
+    .wbs_s6_dat_i(wbs_s6_dat_i),
+    .wbs_s6_ack_i(wbs_s6_ack_i),
+  
     // Wishbone SLV 7 interface
-    wire           wbs_s7_cyc_o ;
-    wire           wbs_s7_stb_o ;
-    wire [31:0]    wbs_s7_adr_o ;
-    wire           wbs_s7_we_o  ;
-    wire [31:0]    wbs_s7_dat_o ;
-    wire [3:0]     wbs_s7_sel_o ;
-    wire [31:0]    wbs_s7_dat_i ;
-    wire           wbs_s7_ack_i ;
+    .wbs_s7_cyc_o(wbs_s7_cyc_o),
+    .wbs_s7_stb_o(wbs_s7_stb_o),
+    .wbs_s7_adr_o(wbs_s7_adr_o),
+    .wbs_s7_we_o (wbs_s7_we_o ),
+    .wbs_s7_dat_o(wbs_s7_dat_o),
+    .wbs_s7_sel_o(wbs_s7_sel_o),
+    .wbs_s7_dat_i(wbs_s7_dat_i),
+    .wbs_s7_ack_i(wbs_s7_ack_i)
+  
+  );
+  
+  nec_ir_receiver #(
+    .NB_STAGES (10),
+    .PSIZE     (20),
+    .DSIZE     (11),
+    .ASIZE     ( 4)
+  ) i_nec_ir_receiver (
+    .rst_n    (rst_n       ),
+    .clk      (wb_clk_i    ),
+    .wbs_cyc_i(wbs_s0_cyc_o),
+    .wbs_stb_i(wbs_s0_stb_o),
+    .wbs_adr_i(wbs_s0_adr_o),
+    .wbs_we_i (wbs_s0_we_o ),
+    .wbs_dat_i(wbs_s0_dat_o),
+    .wbs_sel_i(wbs_s0_sel_o),
+    .wbs_dat_o(wbs_s0_dat_i),
+    .wbs_ack_o(wbs_s0_ack_i),
+    .ir_in    (io_in[37]   ),
+    .irq      (irq[0]      )
+  );
+  
+  pseudorandom i_pseudorandom (
+    .rst_n     (rst_n       ),
+    .clk       (wb_clk_i    ),
 
-    // IO
-    assign io_out = {(`MPRJ_IO_PADS){1'b0}};
-    assign io_oeb = {(`MPRJ_IO_PADS){1'b1}};
+    // Wishbone bus
+    .wbs_cyc_i (wbs_s1_cyc_o),
+    .wbs_stb_i (wbs_s1_stb_o),
+    .wbs_adr_i (wbs_s1_adr_o),
+    .wbs_we_i  (wbs_s1_we_o ),
+    .wbs_dat_i (wbs_s1_dat_o),
+    .wbs_sel_i (wbs_s1_sel_o),
+    .wbs_dat_o (wbs_s1_dat_i),
+    .wbs_ack_o (wbs_s1_ack_i) 
+  );
+  
+  step_motor_controller #(
+    .PSIZE(16),
+    .DSIZE(16)
+  ) i_step_motor_controller (
+  
+  	.rst_n(rst_n),
+  	.clk(clk),
+  
+    // Wishbone bus
+    .wbs_cyc_i (wbs_s2_cyc_o),
+    .wbs_stb_i (wbs_s2_stb_o),
+    .wbs_adr_i (wbs_s2_adr_o),
+    .wbs_we_i  (wbs_s2_we_o ),
+    .wbs_dat_i (wbs_s2_dat_o),
+    .wbs_sel_i (wbs_s2_sel_o),
+    .wbs_dat_o (wbs_s2_dat_i),
+    .wbs_ack_o (wbs_s2_ack_i),
+  
+    // Motor outputs
+    .motor_a1  (io_out[31]),
+    .motor_a2  (io_out[30]),
+    .motor_b1  (io_out[29]),
+    .motor_b2  (io_out[28])
+  );
+  
+  step_motor_controller #(
+    .PSIZE(16),
+    .DSIZE(16)
+  ) i_step_motor_controller (
+  
+  	.rst_n(rst_n),
+  	.clk(clk),
+  
+    // Wishbone bus
+    .wbs_cyc_i (wbs_s3_cyc_o),
+    .wbs_stb_i (wbs_s3_stb_o),
+    .wbs_adr_i (wbs_s3_adr_o),
+    .wbs_we_i  (wbs_s3_we_o ),
+    .wbs_dat_i (wbs_s3_dat_o),
+    .wbs_sel_i (wbs_s3_sel_o),
+    .wbs_dat_o (wbs_s3_dat_i),
+    .wbs_ack_o (wbs_s3_ack_i),
+  
+    // Motor outputs
+    .motor_a1  (io_out[27]),
+    .motor_a2  (io_out[26]),
+    .motor_b1  (io_out[25]),
+    .motor_b2  (io_out[24])
+  );
 
-    // IRQ
-    assign irq[2:1] = 2'b00;	// Unused
-
-    // LA
-    assign la_data_out = {(128){1'b0}};
-
-    assign rst_n = ~wb_rst_i;
-	
-	wishbone_1mst_to_8slv #(
-      .ADDR_S0(32'h30000000), // Base address of Wishbone SLV 0
-      .MASK_S0(32'hFFFF0000), // Mask address of Wishbone SLV 0
-      .ADDR_S1(32'h30010000), // Base address of Wishbone SLV 1
-      .MASK_S1(32'hFFFF0000), // Mask address of Wishbone SLV 1
-      .ADDR_S2(32'h30020000), // Base address of Wishbone SLV 2
-      .MASK_S2(32'hFFFF0000), // Mask address of Wishbone SLV 2
-      .ADDR_S3(32'h30030000), // Base address of Wishbone SLV 3
-      .MASK_S3(32'hFFFF0000), // Mask address of Wishbone SLV 3
-      .ADDR_S4(32'h30040000), // Base address of Wishbone SLV 4
-      .MASK_S4(32'hFFFF0000), // Mask address of Wishbone SLV 4
-      .ADDR_S5(32'h30050000), // Base address of Wishbone SLV 5
-      .MASK_S5(32'hFFFF0000), // Mask address of Wishbone SLV 5
-      .ADDR_S6(32'h30060000), // Base address of Wishbone SLV 6
-      .MASK_S6(32'hFFFF0000), // Mask address of Wishbone SLV 6
-      .ADDR_S7(32'h30070000), // Base address of Wishbone SLV 7
-      .MASK_S7(32'hFFFF0000)  // Mask address of Wishbone SLV 7
-    ) i_wishbone_1mst_to_8slv (
-    
-      // Wishbone MST interface
-      .wbs_m_cyc_i(wbs_cyc_i),
-      .wbs_m_stb_i(wbs_stb_i),
-      .wbs_m_adr_i(wbs_adr_i),
-      .wbs_m_we_i (wbs_we_i ),
-      .wbs_m_dat_i(wbs_dat_i),
-      .wbs_m_sel_i(wbs_sel_i),
-      .wbs_m_dat_o(wbs_dat_o),
-      .wbs_m_ack_o(wbs_ack_o),
-    
-      // Wishbone SLV 0 interface
-      .wbs_s0_cyc_o(wbs_s0_cyc_o),
-      .wbs_s0_stb_o(wbs_s0_stb_o),
-      .wbs_s0_adr_o(wbs_s0_adr_o),
-      .wbs_s0_we_o (wbs_s0_we_o ),
-      .wbs_s0_dat_o(wbs_s0_dat_o),
-      .wbs_s0_sel_o(wbs_s0_sel_o),
-      .wbs_s0_dat_i(wbs_s0_dat_i),
-      .wbs_s0_ack_i(wbs_s0_ack_i),
-    
-      // Wishbone SLV 1 interface
-      .wbs_s1_cyc_o(wbs_s1_cyc_o),
-      .wbs_s1_stb_o(wbs_s1_stb_o),
-      .wbs_s1_adr_o(wbs_s1_adr_o),
-      .wbs_s1_we_o (wbs_s1_we_o ),
-      .wbs_s1_dat_o(wbs_s1_dat_o),
-      .wbs_s1_sel_o(wbs_s1_sel_o),
-      .wbs_s1_dat_i(wbs_s1_dat_i),
-      .wbs_s1_ack_i(wbs_s1_ack_i),
-    
-      // Wishbone SLV 2 interface
-      .wbs_s2_cyc_o(wbs_s2_cyc_o),
-      .wbs_s2_stb_o(wbs_s2_stb_o),
-      .wbs_s2_adr_o(wbs_s2_adr_o),
-      .wbs_s2_we_o (wbs_s2_we_o ),
-      .wbs_s2_dat_o(wbs_s2_dat_o),
-      .wbs_s2_sel_o(wbs_s2_sel_o),
-      .wbs_s2_dat_i(wbs_s2_dat_i),
-      .wbs_s2_ack_i(wbs_s2_ack_i),
-    
-      // Wishbone SLV 3 interface
-      .wbs_s3_cyc_o(wbs_s3_cyc_o),
-      .wbs_s3_stb_o(wbs_s3_stb_o),
-      .wbs_s3_adr_o(wbs_s3_adr_o),
-      .wbs_s3_we_o (wbs_s3_we_o ),
-      .wbs_s3_dat_o(wbs_s3_dat_o),
-      .wbs_s3_sel_o(wbs_s3_sel_o),
-      .wbs_s3_dat_i(wbs_s3_dat_i),
-      .wbs_s3_ack_i(wbs_s3_ack_i),
-    
-      // Wishbone SLV 4 interface
-      .wbs_s4_cyc_o(wbs_s4_cyc_o),
-      .wbs_s4_stb_o(wbs_s4_stb_o),
-      .wbs_s4_adr_o(wbs_s4_adr_o),
-      .wbs_s4_we_o (wbs_s4_we_o ),
-      .wbs_s4_dat_o(wbs_s4_dat_o),
-      .wbs_s4_sel_o(wbs_s4_sel_o),
-      .wbs_s4_dat_i(wbs_s4_dat_i),
-      .wbs_s4_ack_i(wbs_s4_ack_i),
-    
-      // Wishbone SLV 5 interface
-      .wbs_s5_cyc_o(wbs_s5_cyc_o),
-      .wbs_s5_stb_o(wbs_s5_stb_o),
-      .wbs_s5_adr_o(wbs_s5_adr_o),
-      .wbs_s5_we_o (wbs_s5_we_o ),
-      .wbs_s5_dat_o(wbs_s5_dat_o),
-      .wbs_s5_sel_o(wbs_s5_sel_o),
-      .wbs_s5_dat_i(wbs_s5_dat_i),
-      .wbs_s5_ack_i(wbs_s5_ack_i),
-    
-      // Wishbone SLV 6 interface
-      .wbs_s6_cyc_o(wbs_s6_cyc_o),
-      .wbs_s6_stb_o(wbs_s6_stb_o),
-      .wbs_s6_adr_o(wbs_s6_adr_o),
-      .wbs_s6_we_o (wbs_s6_we_o ),
-      .wbs_s6_dat_o(wbs_s6_dat_o),
-      .wbs_s6_sel_o(wbs_s6_sel_o),
-      .wbs_s6_dat_i(wbs_s6_dat_i),
-      .wbs_s6_ack_i(wbs_s6_ack_i),
-    
-      // Wishbone SLV 7 interface
-      .wbs_s7_cyc_o(wbs_s7_cyc_o),
-      .wbs_s7_stb_o(wbs_s7_stb_o),
-      .wbs_s7_adr_o(wbs_s7_adr_o),
-      .wbs_s7_we_o (wbs_s7_we_o ),
-      .wbs_s7_dat_o(wbs_s7_dat_o),
-      .wbs_s7_sel_o(wbs_s7_sel_o),
-      .wbs_s7_dat_i(wbs_s7_dat_i),
-      .wbs_s7_ack_i(wbs_s7_ack_i)
-    
-    );
-	
-    nec_ir_receiver #(
-      .NB_STAGES (10),
-      .PSIZE     (20),
-      .DSIZE     (11),
-      .ASIZE     ( 4)
-    ) i_nec_ir_receiver (
-      .rst_n    (rst_n       ),
-      .clk      (wb_clk_i    ),
-      .wbs_cyc_i(wbs_s0_cyc_o),
-      .wbs_stb_i(wbs_s0_stb_o),
-      .wbs_adr_i(wbs_s0_adr_o),
-      .wbs_we_i (wbs_s0_we_o ),
-      .wbs_dat_i(wbs_s0_dat_o),
-      .wbs_sel_i(wbs_s0_sel_o),
-      .wbs_dat_o(wbs_s0_dat_i),
-      .wbs_ack_o(wbs_s0_ack_i),
-      .ir_in    (io_in[37]   ),
-      .irq      (irq[0]      )
-    );
-	
-	pseudorandom i_pseudorandom (
-      .rst_n     (rst_n       ),
-      .clk       (wb_clk_i    ),
-
-      // Wishbone bus
-      .wbs_cyc_i (wbs_s1_cyc_o),
-      .wbs_stb_i (wbs_s1_stb_o),
-      .wbs_adr_i (wbs_s1_adr_o),
-      .wbs_we_i  (wbs_s1_we_o ),
-      .wbs_dat_i (wbs_s1_dat_o),
-      .wbs_sel_i (wbs_s1_sel_o),
-      .wbs_dat_o (wbs_s1_dat_i),
-      .wbs_ack_o (wbs_s1_ack_i) 
-    );
-	
-    assign wbs_s2_dat_i = 32'h00000000;
-    assign wbs_s3_dat_i = 32'h00000000;
-    assign wbs_s4_dat_i = 32'h00000000;
-    assign wbs_s5_dat_i = 32'h00000000;
-    assign wbs_s6_dat_i = 32'h00000000;
-    assign wbs_s7_dat_i = 32'h00000000;
-    assign wbs_s2_ack_i = wbs_s2_stb_o;
-    assign wbs_s3_ack_i = wbs_s3_stb_o;
-    assign wbs_s4_ack_i = wbs_s4_stb_o;
-    assign wbs_s5_ack_i = wbs_s5_stb_o;
-    assign wbs_s6_ack_i = wbs_s6_stb_o;
-    assign wbs_s7_ack_i = wbs_s7_stb_o;
+  assign wbs_s4_dat_i = 32'h00000000;
+  assign wbs_s5_dat_i = 32'h00000000;
+  assign wbs_s6_dat_i = 32'h00000000;
+  assign wbs_s7_dat_i = 32'h00000000;
+  assign wbs_s4_ack_i = wbs_s4_stb_o;
+  assign wbs_s5_ack_i = wbs_s5_stb_o;
+  assign wbs_s6_ack_i = wbs_s6_stb_o;
+  assign wbs_s7_ack_i = wbs_s7_stb_o;
 
 endmodule