diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 5c5299b..dac836e 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -297,7 +297,7 @@
   step_motor_controller #(
     .PSIZE(16),
     .DSIZE(16)
-  ) i_step_motor_controller (
+  ) i_step_motor_controller_0 (
   
   	.rst_n(rst_n),
   	.clk(clk),
@@ -322,7 +322,7 @@
   step_motor_controller #(
     .PSIZE(16),
     .DSIZE(16)
-  ) i_step_motor_controller (
+  ) i_step_motor_controller_1 (
   
   	.rst_n(rst_n),
   	.clk(clk),