# Caravel user project includes

-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	 
-v $(USER_PROJECT_VERILOG)/rtl/fifo.v
-v $(USER_PROJECT_VERILOG)/rtl/Modbus_CRC16.v
-v $(USER_PROJECT_VERILOG)/rtl/Modbus_Top.v
-v $(USER_PROJECT_VERILOG)/rtl/Modbus_UART_Controller.v
-v $(USER_PROJECT_VERILOG)/rtl/Modbus_w_RegSpace_Controller.v
-v $(USER_PROJECT_VERILOG)/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
-v $(USER_PROJECT_VERILOG)/rtl/uart_rx.v
-v $(USER_PROJECT_VERILOG)/rtl/uart_tx.v