2022-06-07 15:27:54 - [INFO] - {{Project Git Info}} Repository: https://github.com/yongatek/caravel_yonga-modbus-controller.git | Branch: yonga-mpw-6c | Commit: bd31973431fca2cb722789001c86c69e2f3eb946
2022-06-07 15:27:54 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: yonga-modbus_controller
2022-06-07 15:27:54 - [INFO] - {{Project Type Info}} digital
2022-06-07 15:27:54 - [INFO] - {{Project GDS Info}} user_project_wrapper: ac0695f13e54def395b0f75268a484797e8f6119
2022-06-07 15:27:54 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
2022-06-07 15:27:54 - [INFO] - {{PDKs Info}} Open PDKs: 27ecf1c16911f7dd4428ffab96f62c1fb876ea70 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
2022-06-07 15:27:54 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'yonga-modbus_controller/jobs/mpw_precheck/0b6c97ee-bbb7-472e-bc76-67d636bcfd45/logs'
2022-06-07 15:27:54 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
2022-06-07 15:27:54 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
2022-06-07 15:27:55 - [INFO] - An approved LICENSE (Apache-2.0) was found in yonga-modbus_controller.
2022-06-07 15:27:55 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2022-06-07 15:27:56 - [INFO] - An approved LICENSE (Apache-2.0) was found in yonga-modbus_controller.
2022-06-07 15:27:56 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2022-06-07 15:27:56 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in yonga-modbus_controller/openlane/Makefile
2022-06-07 15:27:56 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 46 non-compliant file(s) with the SPDX Standard.
2022-06-07 15:27:56 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['yonga-modbus_controller/Makefile', 'yonga-modbus_controller/docs/Makefile', 'yonga-modbus_controller/docs/environment.yml', 'yonga-modbus_controller/docs/source/conf.py', 'yonga-modbus_controller/docs/source/index.rst', 'yonga-modbus_controller/docs/source/quickstart.rst', 'yonga-modbus_controller/openlane/user_proj_example/config.json', 'yonga-modbus_controller/openlane/user_proj_example/config.tcl', 'yonga-modbus_controller/openlane/user_project_wrapper/config.json', 'yonga-modbus_controller/openlane/user_project_wrapper/config.tcl', 'yonga-modbus_controller/sdc/user_project_wrapper.sdc', 'yonga-modbus_controller/sdf/user_project_wrapper.sdf', 'yonga-modbus_controller/spef/user_project_wrapper.spef', 'yonga-modbus_controller/verilog/dv/Makefile', 'yonga-modbus_controller/verilog/dv/io_ports/Makefile']
2022-06-07 15:27:56 - [INFO] - For the full SPDX compliance report check: yonga-modbus_controller/jobs/mpw_precheck/0b6c97ee-bbb7-472e-bc76-67d636bcfd45/logs/spdx_compliance_report.log
2022-06-07 15:27:56 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
2022-06-07 15:27:56 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2022-06-07 15:27:56 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
2022-06-07 15:27:56 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2022-06-07 15:27:57 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2022-06-07 15:27:57 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
2022-06-07 15:27:57 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2022-06-07 15:27:57 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
2022-06-07 15:28:02 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. 
2022-06-07 15:28:02 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances). 
2022-06-07 15:28:02 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
2022-06-07 15:28:02 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
2022-06-07 15:28:02 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
2022-06-07 15:28:02 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
2022-06-07 15:28:02 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
2022-06-07 15:28:02 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (2 instances). 
2022-06-07 15:28:02 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
2022-06-07 15:28:02 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
2022-06-07 15:28:02 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
2022-06-07 15:28:02 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
2022-06-07 15:28:02 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
2022-06-07 15:28:02 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2022-06-07 15:28:02 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
2022-06-07 15:28:29 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view yonga-modbus_controller/jobs/mpw_precheck/0b6c97ee-bbb7-472e-bc76-67d636bcfd45/outputs/user_project_wrapper.xor.gds
2022-06-07 15:28:29 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2022-06-07 15:28:29 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
2022-06-07 15:31:12 - [ERROR] - Violation Message "Metal3 > 3um spacing to unrelated m3 < 0.4um (met3.3d) "found 15 Times.
2022-06-07 15:31:12 - [ERROR] - 15 DRC violations
2022-06-07 15:31:12 - [WARNING] - {{MAGIC DRC CHECK FAILED}} The GDS file, user_project_wrapper.gds, has DRC violations.
2022-06-07 15:31:12 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
2022-06-07 15:31:41 - [INFO] - No DRC Violations found
2022-06-07 15:31:41 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-06-07 15:31:41 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
2022-06-07 15:34:55 - [INFO] - No DRC Violations found
2022-06-07 15:34:55 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-06-07 15:34:55 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
2022-06-07 15:35:24 - [INFO] - No DRC Violations found
2022-06-07 15:35:24 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-06-07 15:35:24 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
2022-06-07 15:35:38 - [INFO] - No DRC Violations found
2022-06-07 15:35:38 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-06-07 15:35:38 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
2022-06-07 15:35:48 - [INFO] - No DRC Violations found
2022-06-07 15:35:48 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-06-07 15:35:48 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
2022-06-07 15:35:51 - [INFO] - No DRC Violations found
2022-06-07 15:35:51 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-06-07 15:35:51 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'yonga-modbus_controller/jobs/mpw_precheck/0b6c97ee-bbb7-472e-bc76-67d636bcfd45/logs'
2022-06-07 15:35:51 - [INFO] - {{SUCCESS}} All Checks Passed !!!