diff --git a/verilog/dv/README.md b/verilog/dv/README.md
index 1a834f7..806781b 100644
--- a/verilog/dv/README.md
+++ b/verilog/dv/README.md
@@ -128,7 +128,7 @@
 
 # User Project Example DV
 
-The directory includes four tests for the counter user-project example: 
+The directory includes five tests for the counter user-project example: 
 
 ### IO Ports Test 
 
@@ -168,6 +168,13 @@
 	reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
 	.....
 	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+	
+	reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+        .....
+        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+	
+	reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
 
 	reg_mprj_xfer = 1;
 	while (reg_mprj_xfer == 1);
@@ -187,23 +194,27 @@
 
  
 	```c
-	reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0] inputs to mgmt_soc
-	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32] outputs from mgmt_soc
+	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]
+	reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0x00000000;    // [127:96]
 	```
 
 * Then, the firmware writes an initial value to the counter through the LA1 data register. Afte writing the counter value, the LA probes are disabled to prevent the counter write signal from being always set to one. 
 
 	```c
 	reg_la1_data = 0x00000000;     // Write zero to count register
-	reg_la1_oenb  = reg_la1_iena = 0xFFFFFFFF;     // Disable probes
+	reg_la1_oenb = reg_la1_iena = 0x00000000;     // Disable probes
 	```
 
 * The firmware then waits until the count value exceeds 500 and flags the success of the test by writing `0xAB41` to pads 16 to 31.  The firmware reads the count value through the logic analyzer probes `[31:0]` 
 
 	```c
-	if (reg_la0_data > 0x1F4) {	     // Read current count value through LA
-		reg_mprj_datal = 0xAB410000; // Flag success of the test
-		break;
+	while (1) {
+		if (reg_la0_data > 0x1F4) {	     // Read current count value through LA
+			reg_mprj_datal = 0xAB410000; // Flag success of the test
+			break;
+		}
 	}
 	```
   
@@ -212,7 +223,10 @@
 * This test is meant to verify that we can drive the clock and reset signals for the user project example through the logic analyzer. In the [user_proj_example](verilog/rtl/user_proj_example.v) RTL, the clock can either be supplied from the `wb_clk_i` or from the logic analyzer through bit `[64]`. Similarly, the reset signal can be supplied from the `wb_rst_i` or through `LA[65]`.  The firmware configures the clk and reset LA probes as outputs from the management SoC by writing to the LA2 enable register. 
 
 	```c
-	reg_la2_oenb  = reg_la2_iena = 0xFFFFFFFC; 	// Configure LA[64] LA[65] as outputs from the cpu
+	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]
+	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0x00000000;    // [127:96]
 	```
 
 * Then, the firmware supplies both clock reset signals through LA2 data register. First, both are set to one. Then, reset is driven to zero and the clock is toggled for 6 clock cycles. 
@@ -226,11 +240,45 @@
 	```
 * The testbench success criteria is that the firmware reads a count value of five through the LA probes. 
 	```c
-	if (reg_la0_data == 0x05) {
-		reg_mprj_datal = 0xAB610000;   // FLag success of the test
+	while (1){
+		if (reg_la0_data == 0x05) {
+			reg_mprj_datal = 0xAB610000;   // FLag success of the test
+		}
 	}
 	```
 	
+### MPRJ_stimulus
+
+* This test is meant to verify that we can read data generated from the user project on the gpio outputs. This is done by configuring the LA probes as inputs to the cpu, except for LA probes [63:32] as output from the cpu
+
+	```c
+	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]
+	reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0x00000000;    // [127:96]
+	```
+* Then tests the ability to force data on the gpio through channel 37
+
+	```c
+	reg_mprj_datah = 0x0f0f0fc0;
+	reg_mprj_datah = 0x00000000;
+	reg_mprj_datah = 0x0f0f0fca;
+	reg_mprj_datah = 0x0000000a;
+	reg_mprj_datah = 0x0f0f0fc0;
+	reg_mprj_datah = 0x00000000;
+	reg_mprj_datah = 0x0f0f0fc5;
+	reg_mprj_datah = 0x00000005;
+	```
+* It then tests the ability to read back the data generated by the user project on the gpio
+
+	```c
+	testval = reg_mprj_datal;
+	reg_mprj_datal = (testval << 16);
+	testval = reg_mprj_datal;
+	reg_mprj_datal = (testval << 16);
+	```
+
+	
 ### Wishbone Test
 
-* This test is meant to verify that we can read and write to the count register through the wishbone port. The firmware writes a value of `0x2710` to the count register, then reads back the count value after some time. The read and write transactions happen through the management SoC wishbone bus and are initiated by either writing or reading from the user project address on the wishbone bus. 
+* This test is meant to verify that we can read and write to the count register through the wishbone port. The firmware writes a value of `0x2710` to the count register, then reads back the count value after some time. The read and write transactions happen through the management SoC wishbone bus and are initiated by either writing or reading from the user project address on the wishbone bus. The ``reg_wb_enable`` needs to be set to 1 in order to enable the wishbone bus.