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      "message": "Fixing spurious via placement\n\nThis hopefully fixes the XOR precheck error.\n"
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      "message": "XOR fix cnt\u0027d\n\nNow update the netlist to match the used signals in the subcell.\n"
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      "message": "Add pin layer on top pins.\n"
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        "time": "Mon Mar 21 16:16:17 2022 +0100"
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      "message": "Consistency pt.3\n\nStory continues...\n"
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      "message": "Consistency pt.2\n\nVerilog files.\n"
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        "time": "Mon Mar 21 14:55:11 2022 +0100"
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      "message": "Consistency check hack.\n"
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        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Mar 21 12:29:26 2022 +0100"
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      "message": "Place SRAM block on grid.\n"
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      "message": "First version with unconnected SRAM block\n"
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        "time": "Sun Mar 20 19:39:00 2022 +0100"
      },
      "message": "README\n\nStart of README.\n"
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        "email": "staf@fibraservi.eu",
        "time": "Sun Mar 20 19:38:08 2022 +0100"
      },
      "message": "Empty top cell template\n\nThis was based on code from mpw4 io test at state of tape-out with\nupdate fram pin locations.\n"
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        "email": "staf@fibraservi.eu",
        "time": "Sun Mar 20 16:44:00 2022 +0100"
      },
      "message": "Merge branch \u0027caravel_user_project_analog\u0027 into main\n"
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    {
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        "time": "Sat Mar 19 14:08:00 2022 -0700"
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        "time": "Sat Mar 19 14:08:00 2022 -0700"
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      "message": "Merge pull request #19 from efabless/jeffdi-patch-1\n\nFix tag to mpw-5c"
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        "time": "Sat Mar 19 11:06:20 2022 -0700"
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        "time": "Sat Mar 19 11:06:20 2022 -0700"
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      "message": "Fix tag to mpw-5c"
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        "time": "Wed Mar 09 14:50:07 2022 +0000"
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        "time": "Thu Feb 10 09:51:42 2022 -0800"
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        "time": "Thu Feb 10 09:51:42 2022 -0800"
      },
      "message": "Merge pull request #18 from efabless/EFIC-233\n\nEFIC-233"
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        "name": "Ahmed El Omla",
        "email": "ahmed.el-omla@efabless.com",
        "time": "Tue Feb 08 16:15:27 2022 +0200"
      },
      "committer": {
        "name": "Ahmed El Omla",
        "email": "ahmed.el-omla@efabless.com",
        "time": "Tue Feb 08 16:15:27 2022 +0200"
      },
      "message": "EFIC-233 - Update CI\n"
    },
    {
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        "time": "Thu Feb 03 10:31:51 2022 -0800"
      },
      "message": "Merge pull request #17 from efabless/ol_fix\n\nUpdate Caravel to `mpw-5a`"
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        "time": "Thu Feb 03 20:29:50 2022 +0200"
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      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Thu Feb 03 20:29:50 2022 +0200"
      },
      "message": "Update index.rst"
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    {
      "commit": "d7b4222140137f95651637ffa1e0ab513393c8ea",
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      "author": {
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        "time": "Thu Feb 03 18:28:36 2022 +0000"
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      "committer": {
        "name": "Donn",
        "email": "me@donn.website",
        "time": "Thu Feb 03 18:28:36 2022 +0000"
      },
      "message": "Update Caravel to `mpw-5a`\n\nAlso remove `make pdk-nonnative`.\n"
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    {
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        "time": "Fri Jan 28 12:40:31 2022 -0800"
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        "time": "Fri Jan 28 12:40:31 2022 -0800"
      },
      "message": "Merge pull request #16 from efabless/EFIC-232\n\nEFIC-232 - Makefile Updates"
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    {
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        "time": "Fri Jan 28 19:56:44 2022 +0200"
      },
      "message": "Makefile Updates\n\nUpdates to \u0027Makefile\u0027 reflected appropriate mpw-5 shuttle tags and updated precheck instructions"
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      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sun Dec 19 17:03:41 2021 -0500"
      },
      "message": "Modified the xschem schematics so that the wrapper level correctly\nrepresents the metal resistors that were added to the layout to\nmaintain all the pins on isolated nets.  The LVS with the xschem\nnetlist is now correct with the modified layout.  The verilog\nnetlist has not yet been updated.\n"
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    {
      "commit": "ea5ff7d937a3422c805b506215ae5242935638b2",
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        "email": "tim@opencircuitdesign.com",
        "time": "Sat Dec 18 10:44:16 2021 -0500"
      },
      "message": "Updated the layout to properly use the metal resistors in front of\npins that are connected to the same net.  Updated the GDS with this\nchange, and also to properly generate hierarchical layers, which\napparently had not been done previously.  Verilog and schematic\nhave not yet been updated with the metal resistor change, and so\nwill fail LVS until they are.\n"
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      },
      "committer": {
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        "time": "Fri Dec 17 13:40:01 2021 -0800"
      },
      "message": "Update Makefile"
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    {
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        "time": "Fri Dec 17 13:38:25 2021 -0800"
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        "time": "Fri Dec 17 13:38:25 2021 -0800"
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      "message": "Merge pull request #13 from efabless/caravel_openframe\n\nremove submodule"
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      "committer": {
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        "time": "Fri Dec 17 13:36:23 2021 -0800"
      },
      "message": "Update user_project_ci.yml"
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    {
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      "committer": {
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        "time": "Fri Dec 17 13:35:46 2021 -0800"
      },
      "message": "Update caravan_build.yml"
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    {
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      "committer": {
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        "time": "Fri Dec 17 13:33:34 2021 -0800"
      },
      "message": "Update run-truck.sh"
    },
    {
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        "time": "Fri Dec 17 13:33:15 2021 -0800"
      },
      "message": "Update run-set-id.sh"
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    {
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      "committer": {
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        "time": "Fri Dec 17 13:32:55 2021 -0800"
      },
      "message": "Update user_project_ci.yml"
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    {
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      "committer": {
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        "email": "noreply@github.com",
        "time": "Fri Dec 17 13:32:23 2021 -0800"
      },
      "message": "Update caravan_build.yml"
    },
    {
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      "committer": {
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        "time": "Fri Dec 17 13:31:34 2021 -0800"
      },
      "message": "Delete auto_update_submodule.yml"
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    {
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        "time": "Thu Dec 16 12:07:52 2021 -0800"
      },
      "committer": {
        "name": "jeffdi",
        "email": "jeffdi@efabless.com",
        "time": "Thu Dec 16 12:07:52 2021 -0800"
      },
      "message": "remove submodule\n"
    },
    {
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        "email": "42048757+jeffdi@users.noreply.github.com",
        "time": "Wed Oct 27 11:57:38 2021 -0700"
      },
      "committer": {
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        "email": "noreply@github.com",
        "time": "Wed Oct 27 11:57:38 2021 -0700"
      },
      "message": "Merge pull request #12 from Manarabdelaty/update_gds\n\nUpdate gds view to match the mag view"
    },
    {
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        "email": "manarabdelatty@aucegypt.edu",
        "time": "Wed Oct 27 20:43:58 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Wed Oct 27 20:43:58 2021 +0200"
      },
      "message": "Update gds view to match the mag view\n"
    },
    {
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        "email": "42048757+jeffdi@users.noreply.github.com",
        "time": "Mon Oct 25 12:12:33 2021 -0700"
      },
      "committer": {
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        "email": "noreply@github.com",
        "time": "Mon Oct 25 12:12:33 2021 -0700"
      },
      "message": "Delete info.yaml"
    },
    {
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        "email": "42048757+jeffdi@users.noreply.github.com",
        "time": "Sun Oct 24 10:08:46 2021 -0700"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Sun Oct 24 10:08:46 2021 -0700"
      },
      "message": "Update index.rst\n\nAdd\\ checklist item for spice netlist"
    },
    {
      "commit": "f4d92bf2d5dbda8fe5d04d051879691524dcebd0",
      "tree": "68f876891a7484bdfc6d109398c74461ed6d0bfa",
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      "author": {
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        "email": "tim@opencircuitdesign.com",
        "time": "Tue Oct 12 15:49:11 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Tue Oct 12 15:49:11 2021 -0400"
      },
      "message": "Additional corrections to the analog wrapper testbench schematic to\nproperly quote net names with brackets, and to name a net that is\nreferenced in the plot command but hadn\u0027t been named in the\nschematic.\n"
    },
    {
      "commit": "00336fefcbe85ba1859b311b66fa1b68f7d2bf46",
      "tree": "46197294e2a37b6789841ba058e6b437825d56a8",
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      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Mon Oct 11 21:43:55 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Mon Oct 11 21:43:55 2021 -0400"
      },
      "message": "Modified the xschem files to reflect the handling of Tcl variables\nthat was implemented since this repository was first created.  This\nmakes use of xschemrc to define PDKPATH and to allow it to be\noverridden from the local OS environment.\n"
    },
    {
      "commit": "ab6ba9c30b06bc7e68d9478afca6f676c7e4c1ff",
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      "author": {
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        "email": "tim@opencircuitdesign.com",
        "time": "Tue Sep 28 10:50:49 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Tue Sep 28 10:50:49 2021 -0400"
      },
      "message": "Modified the user_analog_project_wrapper layouts (empty and example)\nto add the metal4 and metal5 layers on io_analog[6:4] that are part\nof the top level layout.  This will show users where the layers are\nso that they do not route close enough to create DRC violations where\nthey cannot see them.\n"
    },
    {
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        "time": "Tue Sep 21 07:45:19 2021 -0700"
      },
      "committer": {
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        "email": "noreply@github.com",
        "time": "Tue Sep 21 07:45:19 2021 -0700"
      },
      "message": "Merge pull request #7 from Manarabdelaty/update_spice\n\nUpdate spice netlist to pass the precheck, documentation updates, and minor CI update"
    },
    {
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        "email": "manarabdelatty@aucegypt.edu",
        "time": "Tue Sep 21 01:42:33 2021 +0200"
      },
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        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Tue Sep 21 01:42:33 2021 +0200"
      },
      "message": "Merge branch \u0027update_spice\u0027 of https://github.com/Manarabdelaty/caravel_user_project_analog into update_spice\n"
    },
    {
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        "email": "manarabdelatty@aucegypt.edu",
        "time": "Tue Sep 21 01:41:51 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Tue Sep 21 01:41:51 2021 +0200"
      },
      "message": "[CI] Run jobs on workflow dispatch\n"
    },
    {
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      ],
      "author": {
        "name": "Manar",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Tue Sep 21 01:41:29 2021 +0200"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Tue Sep 21 01:41:29 2021 +0200"
      },
      "message": "EFIC-170 Update documentation to include a note about spice extraction"
    },
    {
      "commit": "5afa59116361fa3d66cc6e8786eca819a8c8e88c",
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