)]}'
{
  "commit": "3d1a8113d97907c87f94efb81c43218be12f79b2",
  "tree": "e60269e194b4eb74dfe8b0e0e9897fc0ccb26e10",
  "parents": [
    "49bdb7d6eccfb2d45ed9e6ca2e2fcbb38c399351"
  ],
  "author": {
    "name": "Staf Verhaegen",
    "email": "staf@fibraservi.eu",
    "time": "Mon Mar 21 16:00:16 2022 +0100"
  },
  "committer": {
    "name": "Staf Verhaegen",
    "email": "staf@fibraservi.eu",
    "time": "Mon Mar 21 16:00:16 2022 +0100"
  },
  "message": "Consistency pt.2\n\nVerilog files.\n",
  "tree_diff": [
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "verilog/rtl/blocks.v",
      "new_id": "c4db2d6f02a89b107df9a50c248620cabcf6ec91",
      "new_mode": 33188,
      "new_path": "verilog/rtl/blocks.v"
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    {
      "type": "modify",
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}