diff --git a/docs/source/quickstart.rst b/docs/source/quickstart.rst
index 6fc01c5..d24f663 100644
--- a/docs/source/quickstart.rst
+++ b/docs/source/quickstart.rst
@@ -108,7 +108,7 @@
 
 	make user_project_wrapper
 	
-6. To run simulation on your design
+8. To run simulation on your design
 
 You need to include your rtl files in ``verilog/includes/includes.<rtl/gl/gl+sdf>.caravel_user_project``. Then run the simulation using these commands
 
@@ -128,14 +128,14 @@
 	# for example
 	make verify-io_ports
 	
-7. To run the precheck locally 
+9. To run the precheck locally 
 
 .. code:: bash
 	
 	make precheck
 	make run-precheck
 	
-17. You are done! now go to www.efabless.com to submit your project!
+10. You are done! now go to www.efabless.com to submit your project!
    
    
 .. |License| image:: https://img.shields.io/badge/License-Apache%202.0-blue.svg