diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index c0a3582..86fc231 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h16m18s,-1,46012.12121212122,0.2475,23006.06060606061,27.04,722.42,5694,0,0,0,0,0,0,-1,1,0,-1,-1,420199,60746,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,309991900.0,4.36,42.79,33.18,10.07,0.41,-1,3565,8555,538,5527,0,0,0,4197,0,0,0,0,0,0,0,4,1341,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h16m7s,-1,46012.12121212122,0.2475,23006.06060606061,27.04,716.55,5694,0,0,0,0,0,0,-1,1,0,-1,-1,421256,61213,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,310056895.0,4.48,43.44,33.22,9.4,0.43,-1,3565,8555,538,5527,0,0,0,4197,0,0,0,0,0,0,0,4,1341,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 860d0c6..22fcfa7 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h39m19s,-1,2.529576587795766,10.2784,1.264788293897883,-1,530.35,13,0,0,0,0,0,0,-1,0,0,-1,-1,1176061,8078,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.36,3.16,3.63,0.42,0.67,-1,271,2532,271,2532,0,0,0,13,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,90,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h40m44s,-1,2.529576587795766,10.2784,1.264788293897883,-1,530.43,13,0,0,0,0,0,0,-1,0,0,-1,-1,1176232,8172,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.36,3.16,3.63,0.42,0.66,-1,271,2532,271,2532,0,0,0,13,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,90,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 5da5134..fae4e84 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h9m32s,-1,49450.0,0.2,24725.0,28.76,669.94,4945,0,0,0,0,0,0,0,5,0,0,-1,347600,49741,0.0,0.0,-1,-0.03,-1,0.0,0.0,-1,-0.04,-1,290549721.0,0.48,55.89,17.29,18.18,0.0,-1,3296,5967,883,3410,0,0,0,3733,0,0,0,0,0,0,0,4,1227,1542,17,166,2592,0,2758,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.33,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h9m8s,-1,41500.0,0.2,20750.0,27.14,656.0,4150,0,0,0,0,0,0,0,2,0,0,-1,339728,47338,0.0,-0.73,-1,-0.52,-1,0.0,-124.0,-1,-1.44,-1,276222913.0,0.16,54.59,17.5,16.78,0.0,-1,3443,6114,1023,3550,0,0,0,3745,0,0,0,0,0,0,0,4,1231,1200,17,166,2592,0,2758,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.33,0.0,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/agents/uart_agent.v b/verilog/dv/agents/uart_agent.v
index 7c99b46..2ed5686 100644
--- a/verilog/dv/agents/uart_agent.v
+++ b/verilog/dv/agents/uart_agent.v
@@ -63,13 +63,13 @@
 always @(posedge mclk)
 begin
    if (clk_count == 'h0) begin
-      uart_clk = ~uart_clk;
-      clk_count = control_setup.divisor;	
+      uart_clk <= ~uart_clk;
+      clk_count <= control_setup.divisor;	
    end else begin
-      clk_count = clk_count - 1;	
+      clk_count <= clk_count - 1;	
    end
 end
-assign uart_rx_clk = ~uart_clk;
+assign uart_rx_clk = uart_clk;
 
 always @(posedge mclk)
 begin
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index f00f3bb..48e54f0 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c
@@ -169,6 +169,10 @@
     reg_mprj_xfer = 1;
     while (reg_mprj_xfer == 1);
 
+    reg_la0_data = 0x000;
+    reg_la0_data = 0x001; // Remove Soft Reset
+
+
     // Remove Wishbone Reset
     reg_mprj_wbhost_reg0 = 0x1;
 
diff --git a/verilog/dv/uart_master/uart_master.c b/verilog/dv/uart_master/uart_master.c
index 1776e93..1f5912a 100644
--- a/verilog/dv/uart_master/uart_master.c
+++ b/verilog/dv/uart_master/uart_master.c
@@ -92,7 +92,6 @@
     reg_mprj_datal = 0xAB600000;
 
     reg_la0_oenb = reg_la0_iena =  0x0000000;
-    reg_la0_data = 0x000;
 
     //-----------------------------------------------------
     // Start of User Functionality and take over the GPIO Pins
@@ -141,14 +140,16 @@
     reg_mprj_xfer = 1;
     while (reg_mprj_xfer == 1);
 
-    //uart_cfg = 0x000;
-    //uart_cfg |= 0x1; // bit[0] - Enable Transmit Path
-    //uart_cfg |= 0x2; // bit[1] - Enable Receive Path
-    //uart_cfg |= 0x4; // bit[2] - Set 2 Stop Bit
-    //uart_cfg |= 0x0; // bit[15:4] - 16x Baud Clock
-    //uart_cfg |= 0x0; // bit[17:16] - Priority mode = 0
-    uart_cfg = 0x007;
-    reg_la0_data = uart_cfg;
+    reg_la0_data = 0x000;
+    //reg_la0_data = 0x000;
+    //reg_la0_data |= 0x1; // bit[0] - Remove Software Reset
+    //reg_la0_data |= 0x1; // bit[1] - Enable Transmit Path
+    //reg_la0_data |= 0x2; // bit[2] - Enable Receive Path
+    //reg_la0_data |= 0x4; // bit[3] - Set 2 Stop Bit
+    //reg_la0_data |= 0x0; // bit[15:4] - 16x Baud Clock
+    //reg_la0_data |= 0x0; // bit[17:16] - Priority mode = 0
+    reg_la0_data = 0x001;
+    reg_la0_data = 0x00F;
 
 
 
diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master/uart_master_tb.v
index c9c6604..8a7f66e 100644
--- a/verilog/dv/uart_master/uart_master_tb.v
+++ b/verilog/dv/uart_master/uart_master_tb.v
@@ -78,6 +78,8 @@
 		$dumpvars(1, uart_master_tb.uut);
 		$dumpvars(1, uart_master_tb.uut.mprj);
 		$dumpvars(1, uart_master_tb.uut.mprj.u_wb_host);
+		$dumpvars(1, uart_master_tb.uut.mprj.u_wb_host.u_uart2wb);
+		$dumpvars(1, uart_master_tb.tb_master_uart);
 		//$dumpvars(2, uart_master_tb.uut.mprj.u_pinmux);
 	end
        `endif
@@ -85,7 +87,7 @@
 	initial begin
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (30) begin
+		repeat (400) begin
 			repeat (1000) @(posedge clock);
 			// $display("+1000 cycles");
 		end
@@ -117,7 +119,7 @@
 	   wait(checkbits == 16'h AB60);
 		$display("Monitor: UART Master Test Started");
 
-           repeat (1000) @(posedge clock);
+           repeat (4000) @(posedge clock);
            //$write ("\n(%t)Response:\n",$time);
            flag = 0;
            while(flag == 0)
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 49482e0..e959a8e 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -242,8 +242,8 @@
          wb_user_core_write('h3080_0000,'h1);
 
 	 wb_user_core_read_check(32'h30020058,read_data,32'h8273_8343);
-	 wb_user_core_read_check(32'h3002005C,read_data,32'h2012_2021);
-	 wb_user_core_read_check(32'h30020060,read_data,32'h0002_2000);
+	 wb_user_core_read_check(32'h3002005C,read_data,32'h0101_2022);
+	 wb_user_core_read_check(32'h30020060,read_data,32'h0002_3000);
 
       end
    
@@ -301,7 +301,7 @@
 
  
     // Logic Analyzer Signals
-    .la_data_in      ('0) ,
+    .la_data_in      ('1) ,
     .la_data_out     (),
     .la_oenb         ('0),
  
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index 1299479..07e2bf9 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -329,7 +329,7 @@
 
  
     // Logic Analyzer Signals
-    .la_data_in      ('0) ,
+    .la_data_in      ('1) ,
     .la_data_out     (),
     .la_oenb         ('0),
  
diff --git a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
index 5fe3ae9..9637b3c 100644
--- a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
+++ b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
@@ -768,7 +768,7 @@
 
  
     // Logic Analyzer Signals
-    .la_data_in      ('0) ,
+    .la_data_in      ('1) ,
     .la_data_out     (),
     .la_oenb         ('0),
  
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index aba5643..ab96410 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -230,7 +230,7 @@
 
  
     // Logic Analyzer Signals
-    .la_data_in      ('0) ,
+    .la_data_in      ('1) ,
     .la_data_out     (),
     .la_oenb         ('0),
  
diff --git a/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v b/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v
index e748da4..dcf85c6 100644
--- a/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v
+++ b/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v
@@ -244,7 +244,7 @@
 
  
     // Logic Analyzer Signals
-    .la_data_in      ('0) ,
+    .la_data_in      ('1) ,
     .la_data_out     (),
     .la_oenb         ('0),
  
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index 0e662bf..9693439 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -1107,7 +1107,7 @@
 
  
     // Logic Analyzer Signals
-    .la_data_in      ('0) ,
+    .la_data_in      ('1) ,
     .la_data_out     (),
     .la_oenb         ('0),
  
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index c459f5d..edda128 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -273,7 +273,7 @@
 
  
     // Logic Analyzer Signals
-    .la_data_in      ('0) ,
+    .la_data_in      ('1) ,
     .la_data_out     (),
     .la_oenb         ('0),
  
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v
index 174bb5a..d41ff59 100644
--- a/verilog/dv/user_uart_master/user_uart_master_tb.v
+++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -133,7 +133,7 @@
 
 	initial begin
 		clock = 0;
-		la_data_in = 0;
+		la_data_in = 1;
 	end
 
 	`ifdef WFDUMP
@@ -165,9 +165,9 @@
    uart_fifo_enable        = 0;	// fifo mode disable
 
    // UPDATE the RTL UART MASTER
-   la_data_in[0] = 1; //  Enable Transmit Path
-   la_data_in[1] = 1; //  Enable Received Path
+   la_data_in[1] = 1; //  Enable Transmit Path
    la_data_in[2] = 1; //  Enable Received Path
+   la_data_in[3] = 1; //  Enable Received Path
    la_data_in[15:4] = ((uart_divisor+1)/16)-1; //  Divisor value
    la_data_in[17:16] = 2'b00; //  priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
 
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index cecab07..2649c67 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -110,7 +110,9 @@
     reg_mprj_xfer = 1;
     while (reg_mprj_xfer == 1);
 
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    reg_la0_data = 0x000;
+    reg_la0_data = 0x001; // Remove Soft Reset
 
     // Flag start of the test
 	reg_mprj_datal = 0xAB600000;
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 1e1addb..b568991 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -668,7 +668,7 @@
 //-----------------------------------------
 // Software Reg-2, Release date: <DAY><MONTH><YEAR>
 // ----------------------------------------
-gen_32b_reg  #(32'h2412_2021) u_reg_23	(
+gen_32b_reg  #(32'h0101_2022) u_reg_23	(
 	      //List of Inputs
 	      .reset_n    (h_reset_n     ),
 	      .clk        (mclk          ),
@@ -681,7 +681,7 @@
 	      );
 
 //-----------------------------------------
-// Software Reg-3: Poject Revison 2.1 = 0002300
+// Software Reg-3: Poject Revison 2.4 = 0002400
 // ----------------------------------------
 gen_32b_reg  #(32'h0002_3000) u_reg_24	(
 	      //List of Inputs
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 8c699ef..8ef66fd 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -141,6 +141,8 @@
 ////      2. Full chip Timing and Transition clean-up             ////                   
 ////    2.3  Dec 24, 2021, Dinesh A                               ////
 ////      UART Master added with message handler at wb_host       ////
+////    2.4  Jan 01, 2022, Dinesh A                               ////
+////       LA[0] is added as soft reset option at wb_port         ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 7cead10..4cf0005 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -189,8 +189,6 @@
 logic               wb_ack_int            ; // acknowlegement
 logic               wb_err_int            ; // error
 
-assign wbm_rst_n = !wbm_rst_i;
-assign wbs_rst_n = !wbm_rst_i;
 
 ctech_buf u_buf_wb_rst        (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n));
 ctech_buf u_buf_cpu_rst       (.A(cfg_glb_ctrl[1]),.X(cpu_rst_n));
@@ -201,17 +199,35 @@
 ctech_buf u_buf_usb_rst       (.A(cfg_glb_ctrl[6]),.X(usb_rst_n));
 ctech_buf u_buf_bist_rst      (.A(cfg_glb_ctrl[7]),.X(bist_rst_n));
 
+//--------------------------------------------------------------------------------
+// Look like wishbone reset removed early than user Power up sequence
+// To control the reset phase, we have added additional control through la[0]
+// ------------------------------------------------------------------------------
+wire    arst_n = !wbm_rst_i & la_data_in[0];
+reset_sync  u_wbm_rst (
+	      .scan_mode  (1'b0           ),
+              .dclk       (wbm_clk_i      ), // Destination clock domain
+	      .arst_n     (arst_n         ), // active low async reset
+              .srst_n     (wbm_rst_n      )
+          );
+
+reset_sync  u_wbs_rst (
+	      .scan_mode  (1'b0           ),
+              .dclk       (wbs_clk_i      ), // Destination clock domain
+	      .arst_n     (arst_n         ), // active low async reset
+              .srst_n     (wbs_rst_n      )
+          );
 
 // UART Master
 uart2wb u_uart2wb (  
-        .arst_n          (wbm_rst_n          ), //  sync reset
-        .app_clk         (wbm_clk_i          ), //  sys clock    
+        .arst_n          (wbm_rst_n         ), //  sync reset
+        .app_clk         (wbm_clk_i         ), //  sys clock    
 
 	// configuration control
-       .cfg_tx_enable    (la_data_in[0]      ), // Enable Transmit Path
-       .cfg_rx_enable    (la_data_in[1]      ), // Enable Received Path
-       .cfg_stop_bit     (la_data_in[2]    ), // 0 -> 1 Start , 1 -> 2 Stop Bits
-       .cfg_baud_16x     (la_data_in[15:4]   ), // 16x Baud clock generation
+       .cfg_tx_enable    (la_data_in[1]     ), // Enable Transmit Path
+       .cfg_rx_enable    (la_data_in[2]     ), // Enable Received Path
+       .cfg_stop_bit     (la_data_in[3]     ), // 0 -> 1 Start , 1 -> 2 Stop Bits
+       .cfg_baud_16x     (la_data_in[15:4]  ), // 16x Baud clock generation
        .cfg_pri_mod      (la_data_in[17:16] ), // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
 
     // Master Port