diff --git a/openlane/sdram/base.sdc b/openlane/sdram/base.sdc
deleted file mode 100644
index a64cf51..0000000
--- a/openlane/sdram/base.sdc
+++ /dev/null
@@ -1,170 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-
-set_units -time ns
-set ::env(WB_CLOCK_PERIOD) "10"
-set ::env(WB_CLOCK_PORT)   "wb_clk_i"
-set ::env(WB_CLOCK_NAME)   "wb_clk"
-
-set ::env(SDRAM_CLOCK_PERIOD) "20"
-set ::env(SDRAM_CLOCK_PORT)   "sdram_clk"
-set ::env(SDRAM_CLOCK_NAME)   "sdram_clk"
-
-set ::env(PAD_SDRAM_CLOCK_PERIOD) "20"
-set ::env(PAD_SDRAM_CLOCK_PORT)   "io_in\[29\]"
-set ::env(PAD_SDRAM_CLOCK_NAME)   "pad_sdram_clk"
-######################################
-# WB Clock domain input output
-######################################
-create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_NAME)  -period $::env(WB_CLOCK_PERIOD)
-set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
-set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
-puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
-puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
-
-
-set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_NAME)] {wb_rst_n}
-
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_stb_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_addr_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_we_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_dat_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_sel_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_cyc_i*]
-
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_tras_d*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_trp_d*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_trcd_d*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_en*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_req_depth*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_mode_reg*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_cas*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_trcar_d*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_twr_d*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_rfsh*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_rfmax*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_colbits*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_width*]
-
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_dat_o*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_ack_o*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port sdr_init_done*]
-
-######################################
-# SDRAM Clock domain input output
-######################################
-create_clock [get_ports $::env(SDRAM_CLOCK_PORT)]  -name $::env(SDRAM_CLOCK_NAME)  -period $::env(SDRAM_CLOCK_PERIOD)
-set sdram_input_delay_value [expr $::env(SDRAM_CLOCK_PERIOD) * 0.6]
-set sdram_output_delay_value [expr $::env(SDRAM_CLOCK_PERIOD) * 0.6]
-puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
-puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
-
-set_input_delay 2.0 -clock [get_clocks $::env(SDRAM_CLOCK_NAME)] {sdram_resetn}
-
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[0]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[1]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[2]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[3]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[4]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[5]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[6]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[7]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[8]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[9]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[10]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[11]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[12]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[13]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[14]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[15]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[16]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[17]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[18]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[19]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[20]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[21]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[22]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[23]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[24]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[25]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[26]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[27]]
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[28]]
-#set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[29]] Masked SDRAM clock
-set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_oeb*]
-
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[0]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[1]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[2]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[3]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[4]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[5]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[6]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[7]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[8]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[9]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[10]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[11]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[12]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[13]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[14]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[15]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[16]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[17]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[18]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[19]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[20]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[21]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[22]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[23]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[24]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[25]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[26]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[27]]
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[28]]
-#set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_outp 29]] Masked SDRAM clock
-set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_oeb*]
-
-################################################
-# PAD SDRAM Clock domain input output
-# Note: PAD SDRAM clock is same as SDRAM clock
-#       it's a feedback clock through pads
-################################################
-
-create_clock [get_ports $::env(PAD_SDRAM_CLOCK_PORT)]  -name $::env(PAD_SDRAM_CLOCK_NAME)  -period $::env(SDRAM_CLOCK_PERIOD)
-set_input_delay  $sdram_input_delay_value -max  -clock [get_clocks $::env(PAD_SDRAM_CLOCK_NAME)] [get_port io_in*]
-set_input_delay  1                        -min -clock [get_clocks $::env(PAD_SDRAM_CLOCK_NAME)] [get_port io_in*]
-
-
-set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_NAME)] -group [get_clocks $::env(SDRAM_CLOCK_NAME)]
-
-## Add clock uncertainty
-#Note: We have PAD_SDRAM_CLOCK_NAME => SDRAM_CLOCK_NAME path only
-set_clock_uncertainty -from $::env(WB_CLOCK_NAME)        -to $::env(WB_CLOCK_NAME)    -setup 0.400
-set_clock_uncertainty -from $::env(SDRAM_CLOCK_NAME)     -to $::env(SDRAM_CLOCK_NAME) -setup 0.400
-set_clock_uncertainty -from $::env(PAD_SDRAM_CLOCK_NAME) -to $::env(SDRAM_CLOCK_NAME) -setup 0.400
-
-set_clock_uncertainty -from $::env(WB_CLOCK_NAME)        -to $::env(WB_CLOCK_NAME)    -hold 0.050
-set_clock_uncertainty -from $::env(SDRAM_CLOCK_NAME)     -to $::env(SDRAM_CLOCK_NAME) -hold 0.050
-set_clock_uncertainty -from $::env(PAD_SDRAM_CLOCK_NAME) -to $::env(SDRAM_CLOCK_NAME) -hold 0.050 
-
-# TODO set this as parameter
-set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
-puts "\[INFO\]: Setting load to: $cap_load"
-set_load  $cap_load [all_outputs]
-
diff --git a/openlane/sdram/config.tcl b/openlane/sdram/config.tcl
deleted file mode 100755
index ffef2ed..0000000
--- a/openlane/sdram/config.tcl
+++ /dev/null
@@ -1,92 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-# Global
-# ------
-
-set script_dir [file dirname [file normalize [info script]]]
-# Name
-set ::env(DESIGN_NAME) sdrc_top
-
-
-set ::env(DESIGN_IS_CORE) "0"
-set ::env(FP_PDN_CORE_RING) "0"
-
-# Timing configuration
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "wb_clk_i sdram_clk"
-
-set ::env(SYNTH_MAX_FANOUT) 4
-
-# Sources
-# -------
-
-# Local sources + no2usb sources
-set ::env(VERILOG_FILES) "\
-         $script_dir/../../verilog/rtl/sdram_ctrl/src/top/sdrc_top.v \
-         $script_dir/../../verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v \
-         $script_dir/../../verilog/rtl/lib/async_fifo.sv  \
-         $script_dir/../../verilog/rtl/lib/wb_stagging.sv \
-         $script_dir/../../verilog/rtl/sdram_ctrl/src/core/sdrc_core.v \
-         $script_dir/../../verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v \
-         $script_dir/../../verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v \
-         $script_dir/../../verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v\ 
-         $script_dir/../../verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v \
-         $script_dir/../../verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v "
-
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
-
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
-
-set ::env(LEC_ENABLE) 0
-
-set ::env(VDD_PIN) [list {vccd1}]
-set ::env(GND_PIN) [list {vssd1}]
-
-
-# Floorplanning
-# -------------
-
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-set ::env(FP_SIZING) "absolute"
-set ::env(DIE_AREA) [list 0.0 0.0 700.0 500.0]
-
-
-
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0
-
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
-
-
-set ::env(PL_ROUTABILITY_DRIVEN) 1
-
-# helps in anteena fix
-set ::env(USE_ARC_ANTENNA_CHECK) "0"
-
-set ::env(FP_IO_VEXTEND) 4
-set ::env(FP_IO_HEXTEND) 4
-
-
-set ::env(GLB_RT_MAXLAYER) 4
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-set ::env(DIODE_INSERTION_STRATEGY) 5
-
-set ::env(FP_PDN_VPITCH) 100
-set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 5
-set ::env(FP_PDN_HWIDTH) 5
diff --git a/openlane/sdram/pdn.tcl b/openlane/sdram/pdn.tcl
deleted file mode 100644
index 1fe689b..0000000
--- a/openlane/sdram/pdn.tcl
+++ /dev/null
@@ -1,49 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-# Power nets
-set ::power_nets $::env(VDD_PIN)
-set ::ground_nets $::env(GND_PIN)
-
-set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
-
-pdngen::specify_grid stdcell {
-    name grid
-    rails {
-	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
-    }
-    straps {
-	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
-	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
-    }
-    connect {{met1 met4} {met4 met5}}
-}
-
-pdngen::specify_grid macro {
-    power_pins "VPWR"
-    ground_pins "VGND"
-    blockages "li1 met1 met2 met3 met4"
-    straps { 
-    } 
-    connect {{met4_PIN_ver met5}}
-}
-
-set ::halo 5
-
-# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
-set ::rails_start_with "POWER" ;
-
-# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
-set ::stripes_start_with "POWER" ;
diff --git a/openlane/sdram/pin_order.cfg b/openlane/sdram/pin_order.cfg
deleted file mode 100644
index d05e596..0000000
--- a/openlane/sdram/pin_order.cfg
+++ /dev/null
@@ -1,302 +0,0 @@
-#BUS_SORT
-#MANUAL_PLACE
-
-#W
-wb_clk_i            0000 0
-wb_rst_n            0000 1
-
-
-#N
-io_oeb\[29\]  
-io_out\[29\]        
-io_in\[29\]         
-io_oeb\[28\]  
-io_out\[28\]        
-io_in\[28\]         
-io_oeb\[27\]  
-io_out\[27\]        
-io_in\[27\]         
-io_oeb\[26\]  
-io_out\[26\]        
-io_in\[26\]         
-io_oeb\[25\]  
-io_out\[25\]        
-io_in\[25\]         
-io_oeb\[24\]  
-io_out\[24\]        
-io_in\[24\]         
-io_oeb\[23\]  
-io_out\[23\]        
-io_in\[23\]         
-io_oeb\[22\]  
-io_out\[22\]        
-io_in\[22\]         
-io_oeb\[21\]  
-io_out\[21\]        
-io_in\[21\]         
-io_oeb\[20\]  
-io_out\[20\]        
-io_in\[20\]         
-io_oeb\[19\]  
-io_out\[19\]        
-io_in\[19\]         
-io_oeb\[18\]  
-io_out\[18\]        
-io_in\[18\]         
-io_oeb\[17\]  
-io_out\[17\]        
-io_in\[17\]         
-io_oeb\[16\]  
-io_out\[16\]        
-io_in\[16\]         
-io_oeb\[15\]  
-io_out\[15\]        
-io_in\[15\]         
-io_oeb\[14\]  
-io_out\[14\]        
-io_in\[14\]         
-io_oeb\[13\]  
-io_out\[13\]        
-io_in\[13\]         
-io_oeb\[12\]  
-io_out\[12\]        
-io_in\[12\]         
-io_oeb\[11\]  
-io_out\[11\]        
-io_in\[11\]         
-io_oeb\[10\]  
-io_out\[10\]        
-io_in\[10\]         
-io_oeb\[9\]  
-io_out\[9\]        
-io_in\[9\]         
-io_oeb\[8\]  
-io_out\[8\]        
-io_in\[8\]         
-io_oeb\[7\]  
-io_out\[7\]        
-io_in\[7\]         
-io_oeb\[6\]  
-io_out\[6\]        
-io_in\[6\]         
-io_oeb\[5\]  
-io_out\[5\]        
-io_in\[5\]         
-io_oeb\[4\]  
-io_out\[4\]        
-io_in\[4\]         
-io_oeb\[3\]  
-io_out\[3\]        
-io_in\[3\]         
-io_oeb\[2\]  
-io_out\[2\]        
-io_in\[2\]         
-io_oeb\[1\]  
-io_out\[1\]        
-io_in\[1\]         
-io_oeb\[0\]  
-io_out\[0\]        
-io_in\[0\]         
-
-
-#E
-sdram_clk          0000 0
-sdram_resetn       0000 1
-sdr_init_done      0000 2
-cfg_sdr_width\[1\] 0000 3
-cfg_sdr_width\[0\] 0000 4
-cfg_colbits\[1\]   0000 5
-cfg_colbits\[0\]   0000 6
-cfg_sdr_tras_d\[3\] 0000 7
-cfg_sdr_tras_d\[2\] 0000 8
-cfg_sdr_tras_d\[1\] 0000 9
-cfg_sdr_tras_d\[0\] 0000 10
-cfg_sdr_trp_d\[3\]  0000 11
-cfg_sdr_trp_d\[2\]  0000 12
-cfg_sdr_trp_d\[1\]  0000 13
-cfg_sdr_trp_d\[0\]  0000 14
-cfg_sdr_trcd_d\[3\] 0000 15
-cfg_sdr_trcd_d\[2\] 0000 16
-cfg_sdr_trcd_d\[1\] 0000 17
-cfg_sdr_trcd_d\[0\] 0000 18
-cfg_sdr_en          0000 19
-cfg_req_depth\[1\]  0000 20
-cfg_req_depth\[0\]  0000 21
-cfg_sdr_mode_reg\[12\] 0000 22
-cfg_sdr_mode_reg\[11\] 0000 23
-cfg_sdr_mode_reg\[10\] 0000 24
-cfg_sdr_mode_reg\[9\] 0000 25
-cfg_sdr_mode_reg\[8\] 0000 26
-cfg_sdr_mode_reg\[7\] 0000 27
-cfg_sdr_mode_reg\[6\] 0000 28
-cfg_sdr_mode_reg\[5\] 0000 29
-cfg_sdr_mode_reg\[4\] 0000 30
-cfg_sdr_mode_reg\[3\] 0000 31
-cfg_sdr_mode_reg\[2\] 0000 32
-cfg_sdr_mode_reg\[1\] 0000 33
-cfg_sdr_mode_reg\[0\] 0000 34
-cfg_sdr_cas\[2\]      0000 35
-cfg_sdr_cas\[1\]      0000 36
-cfg_sdr_cas\[0\]      0000 37
-cfg_sdr_trcar_d\[3\]  0000 38
-cfg_sdr_trcar_d\[2\]  0000 39
-cfg_sdr_trcar_d\[1\]  0000 40
-cfg_sdr_trcar_d\[0\]  0000 41
-cfg_sdr_twr_d\[3\]    0000 42
-cfg_sdr_twr_d\[2\]    0000 43
-cfg_sdr_twr_d\[1\]    0000 44
-cfg_sdr_twr_d\[0\]    0000 45
-cfg_sdr_rfsh\[11\]    0000 46
-cfg_sdr_rfsh\[10\]    0000 47
-cfg_sdr_rfsh\[9\]    0000 48
-cfg_sdr_rfsh\[8\]    0000 49
-cfg_sdr_rfsh\[7\]    0000 50
-cfg_sdr_rfsh\[6\]    0000 51
-cfg_sdr_rfsh\[5\]    0000 52
-cfg_sdr_rfsh\[4\]    0000 53
-cfg_sdr_rfsh\[3\]    0000 54
-cfg_sdr_rfsh\[2\]    0000 55
-cfg_sdr_rfsh\[1\]    0000 56
-cfg_sdr_rfsh\[0\]    0000 57
-cfg_sdr_rfmax\[2\]   0000 58
-cfg_sdr_rfmax\[1\]   0000 59
-cfg_sdr_rfmax\[0\]   0000 60
-
-sdram_debug\[0\]     200  0
-sdram_debug\[1\]   
-sdram_debug\[2\]   
-sdram_debug\[3\]   
-sdram_debug\[4\]   
-sdram_debug\[5\]   
-sdram_debug\[6\]   
-sdram_debug\[7\]   
-sdram_debug\[8\]   
-sdram_debug\[9\]   
-sdram_debug\[10\]   
-sdram_debug\[11\]   
-sdram_debug\[12\]   
-sdram_debug\[13\]   
-sdram_debug\[14\]   
-sdram_debug\[15\]   
-sdram_debug\[16\]   
-sdram_debug\[17\]   
-sdram_debug\[18\]   
-sdram_debug\[19\]   
-sdram_debug\[20\]   
-sdram_debug\[21\]   
-sdram_debug\[22\]   
-sdram_debug\[23\]   
-sdram_debug\[24\]   
-sdram_debug\[25\]   
-sdram_debug\[26\]   
-sdram_debug\[27\]   
-sdram_debug\[28\]   
-sdram_debug\[29\]   
-sdram_debug\[30\]   
-sdram_debug\[31\]   
-
-#S
-wb_stb_i             0000 0
-wb_we_i              0000 1
-wb_addr_i\[31\]      0000 2
-wb_addr_i\[30\]      0000 3
-wb_addr_i\[29\]      0000 4
-wb_addr_i\[28\]      0000 5
-wb_addr_i\[27\]      0000 6
-wb_addr_i\[26\]      0000 7
-wb_addr_i\[25\]      0000 8
-wb_addr_i\[24\]      0000 9
-wb_addr_i\[23\]      0000 10
-wb_addr_i\[22\]      0000 11
-wb_addr_i\[21\]      0000 12
-wb_addr_i\[20\]      0000 13
-wb_addr_i\[19\]      0000 14
-wb_addr_i\[18\]      0000 15
-wb_addr_i\[17\]      0000 16
-wb_addr_i\[16\]      0000 17
-wb_addr_i\[15\]      0000 18
-wb_addr_i\[14\]      0000 19
-wb_addr_i\[13\]      0000 20
-wb_addr_i\[12\]      0000 21
-wb_addr_i\[11\]      0000 22
-wb_addr_i\[10\]      0000 23
-wb_addr_i\[9\]      0000 24
-wb_addr_i\[8\]      0000 25
-wb_addr_i\[7\]      0000 26
-wb_addr_i\[6\]      0000 27
-wb_addr_i\[5\]      0000 28
-wb_addr_i\[4\]      0000 29
-wb_addr_i\[3\]      0000 30
-wb_addr_i\[2\]      0000 31
-wb_addr_i\[1\]      0000 32
-wb_addr_i\[0\]      0000 33
-wb_sel_i\[3\]       0000 34
-wb_sel_i\[2\]       0000 35
-wb_sel_i\[1\]       0000 36
-wb_sel_i\[0\]       0000 37
-wb_dat_i\[31\]      0000 38
-wb_dat_i\[30\]      0000 39
-wb_dat_i\[29\]      0000 40
-wb_dat_i\[28\]      0000 41
-wb_dat_i\[27\]      0000 42
-wb_dat_i\[26\]      0000 43
-wb_dat_i\[25\]      0000 44
-wb_dat_i\[24\]      0000 45
-wb_dat_i\[23\]      0000 46
-wb_dat_i\[22\]      0000 47
-wb_dat_i\[21\]      0000 48
-wb_dat_i\[20\]      0000 49
-wb_dat_i\[19\]      0000 50
-wb_dat_i\[18\]      0000 51
-wb_dat_i\[17\]      0000 52
-wb_dat_i\[16\]      0000 53
-wb_dat_i\[15\]      0000 54
-wb_dat_i\[14\]      0000 55
-wb_dat_i\[13\]      0000 56
-wb_dat_i\[12\]      0000 57
-wb_dat_i\[11\]      0000 58
-wb_dat_i\[10\]      0000 59
-wb_dat_i\[9\]      0000 60
-wb_dat_i\[8\]      0000 61
-wb_dat_i\[7\]      0000 62
-wb_dat_i\[6\]      0000 63
-wb_dat_i\[5\]      0000 64
-wb_dat_i\[4\]      0000 65
-wb_dat_i\[3\]      0000 66
-wb_dat_i\[2\]      0000 67
-wb_dat_i\[1\]      0000 68
-wb_dat_i\[0\]      0000 69
-wb_dat_o\[31\]     0000 70
-wb_dat_o\[30\]     0000 71
-wb_dat_o\[29\]     0000 72
-wb_dat_o\[28\]     0000 73
-wb_dat_o\[27\]     0000 74
-wb_dat_o\[26\]     0000 75
-wb_dat_o\[25\]     0000 76
-wb_dat_o\[24\]     0000 77
-wb_dat_o\[23\]     0000 78
-wb_dat_o\[22\]     0000 79
-wb_dat_o\[21\]     0000 80
-wb_dat_o\[20\]     0000 81
-wb_dat_o\[19\]     0000 82
-wb_dat_o\[18\]     0000 83
-wb_dat_o\[17\]     0000 84
-wb_dat_o\[16\]     0000 85
-wb_dat_o\[15\]     0000 86
-wb_dat_o\[14\]     0000 87
-wb_dat_o\[13\]     0000 88
-wb_dat_o\[12\]     0000 89
-wb_dat_o\[11\]     0000 90
-wb_dat_o\[10\]     0000 91
-wb_dat_o\[9\]     0000 92
-wb_dat_o\[8\]     0000 93
-wb_dat_o\[7\]     0000 94
-wb_dat_o\[6\]     0000 95
-wb_dat_o\[5\]     0000 96
-wb_dat_o\[4\]     0000 97
-wb_dat_o\[3\]     0000 98
-wb_dat_o\[2\]     0000 99
-wb_dat_o\[1\]     0000 100
-wb_dat_o\[0\]     0000 101
-wb_ack_o          0000 102
-wb_cyc_i          0000 103
diff --git a/openlane/sdram/sta.tcl b/openlane/sdram/sta.tcl
deleted file mode 100644
index f4f630d..0000000
--- a/openlane/sdram/sta.tcl
+++ /dev/null
@@ -1,134 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-
-
-set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
-set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
-set ::env(CURRENT_NETLIST) /project/openlane/sdram/runs/sdram/results/lvs/sdrc_top.lvs.powered.v
-set ::env(DESIGN_NAME) "sdrc_top"
-set ::env(CURRENT_SPEF) /project/openlane/sdram/runs/sdram/results/routing/sdrc_top.spef
-set ::env(BASE_SDC_FILE) "/project/openlane/sdram/base.sdc"
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
-set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-set ::env(SYNTH_CAP_LOAD) "17.65"
-set ::env(WIRE_RC_LAYER) "met1"
-
-
-set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
-read_liberty -min $::env(LIB_FASTEST)
-read_liberty -max $::env(LIB_SLOWEST)
-read_verilog $::env(CURRENT_NETLIST)
-link_design  $::env(DESIGN_NAME)
-
-read_spef  $::env(CURRENT_SPEF)
-
-read_sdc -echo $::env(BASE_SDC_FILE)
-
-# check for missing constraints
-check_setup  -verbose > unconstraints.rpt
-
-set_operating_conditions -analysis_type single
-# Propgate the clock
-set_propagated_clock [all_clocks]
-
-report_tns
-report_wns
-report_power 
-report_checks -unique -slack_max -0.0 -group_count 100 
-report_checks -unique -slack_min -0.0 -group_count 100 
-report_checks -path_delay min_max 
-report_checks -group_count 100  -slack_max -0.01  > timing.rpt
-
-report_checks -group_count 100  -slack_min -0.01 >> timing.rpt
-
-report_checks -to [get_port io_out[0]]  -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[1]]  -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[2]]  -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[3]]  -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[4]]  -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[5]]  -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[6]]  -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[7]]  -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[8]]  -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[9]]  -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[10]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[11]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[12]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[13]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[14]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[15]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[16]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[17]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[18]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[19]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[20]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[21]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[22]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[23]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[24]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[25]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[26]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[27]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[28]] -path_delay min >> timing.rpt
-
-report_checks -to [get_port io_out[0]]  -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[1]]  -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[2]]  -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[3]]  -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[4]]  -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[5]]  -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[6]]  -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[7]]  -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[8]]  -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[9]]  -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[10]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[11]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[12]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[13]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[14]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[15]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[16]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[17]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[18]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[19]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[20]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[21]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[22]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[23]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[24]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[25]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[26]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[27]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[28]] -path_delay max >> timing.rpt
-
-report_checks -from [get_port io_in[0]] -path_delay max >> timing.rpt
-report_checks -from [get_port io_in[1]] -path_delay max >> timing.rpt
-report_checks -from [get_port io_in[2]] -path_delay max >> timing.rpt
-report_checks -from [get_port io_in[3]] -path_delay max >> timing.rpt
-report_checks -from [get_port io_in[4]] -path_delay max >> timing.rpt
-report_checks -from [get_port io_in[5]] -path_delay max >> timing.rpt
-report_checks -from [get_port io_in[6]] -path_delay max >> timing.rpt
-report_checks -from [get_port io_in[7]] -path_delay max >> timing.rpt
-
-report_checks -from [get_port io_in[0]] -path_delay min >> timing.rpt
-report_checks -from [get_port io_in[1]] -path_delay min >> timing.rpt
-report_checks -from [get_port io_in[2]] -path_delay min >> timing.rpt
-report_checks -from [get_port io_in[3]] -path_delay min >> timing.rpt
-report_checks -from [get_port io_in[4]] -path_delay min >> timing.rpt
-report_checks -from [get_port io_in[5]] -path_delay min >> timing.rpt
-report_checks -from [get_port io_in[6]] -path_delay min >> timing.rpt
-report_checks -from [get_port io_in[7]] -path_delay min >> timing.rpt
diff --git a/openlane/uart_i2cm/base.sdc b/openlane/uart_i2cm/base.sdc
deleted file mode 100644
index 5a0d2fe..0000000
--- a/openlane/uart_i2cm/base.sdc
+++ /dev/null
@@ -1,74 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-
-set_units -time ns
-set ::env(CORE_CLOCK_PERIOD) "10"
-set ::env(CORE_CLOCK_PORT)   "app_clk"
-set ::env(CORE_CLOCK_NAME)   "app_clk"
-
-set ::env(LINE_CLOCK_PERIOD) "100"
-set ::env(LINE_CLOCK_PORT)   "u_lineclk_buf/X"
-set ::env(LINE_CLOCK_NAME)   "line_clk"
-
-######################################
-# WB Clock domain input output
-######################################
-create_clock [get_ports $::env(CORE_CLOCK_PORT)]  -name $::env(CORE_CLOCK_NAME)  -period $::env(CORE_CLOCK_PERIOD)
-create_clock [get_pins  $::env(LINE_CLOCK_PORT)]  -name $::env(LINE_CLOCK_NAME)  -period $::env(LINE_CLOCK_PERIOD)
-
-set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
-set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
-
-set line_input_delay_value  [expr $::env(LINE_CLOCK_PERIOD) * 0.6]
-set line_output_delay_value [expr $::env(LINE_CLOCK_PERIOD) * 0.6]
-puts "\[INFO\]: Setting wb output delay to:$core_output_delay_value"
-puts "\[INFO\]: Setting wb input delay to: $core_input_delay_value"
-
-
-set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {uart_rstn}
-set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {i2c_rstn}
-set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {uart_i2c_sel}
-
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_cs*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_addr*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wr*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_be*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wdata*]
-
-
-set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_rdata*]
-set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_ack*]
-
-set_input_delay  $line_input_delay_value   -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_in*]
-set_output_delay $line_input_delay_value   -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_oeb*]
-set_output_delay $line_output_delay_value  -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_out*]
-
-
-set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(CORE_CLOCK_NAME)] -group [get_clocks $::env(LINE_CLOCK_NAME)] 
-
-set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)   -to $::env(CORE_CLOCK_NAME)  -setup 0.400
-set_clock_uncertainty -from $::env(LINE_CLOCK_NAME)   -to $::env(LINE_CLOCK_NAME) -setup 0.400
-
-set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)   -to $::env(CORE_CLOCK_NAME)  -hold 0.050
-set_clock_uncertainty -from $::env(LINE_CLOCK_NAME)   -to $::env(LINE_CLOCK_NAME) -hold 0.050
-
-# TODO set this as parameter
-set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
-puts "\[INFO\]: Setting load to: $cap_load"
-set_load  $cap_load [all_outputs]
-
diff --git a/openlane/uart_i2cm/config.tcl b/openlane/uart_i2cm/config.tcl
deleted file mode 100644
index 088a579..0000000
--- a/openlane/uart_i2cm/config.tcl
+++ /dev/null
@@ -1,95 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-# Global
-# ------
-
-set script_dir [file dirname [file normalize [info script]]]
-# Name
-set ::env(DESIGN_NAME) uart_i2c_top
-
-
-set ::env(DESIGN_IS_CORE) "0"
-set ::env(FP_PDN_CORE_RING) "0"
-
-# Timing configuration
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "app_clk"
-
-set ::env(SYNTH_MAX_FANOUT) 4
-
-# Sources
-# -------
-
-# Local sources + no2usb sources
-set ::env(VERILOG_FILES) "\
-    $script_dir/../../verilog/rtl/uart/src/uart_core.sv  \
-    $script_dir/../../verilog/rtl/uart/src/uart_cfg.sv   \
-    $script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \
-    $script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \
-    $script_dir/../../verilog/rtl/lib/async_fifo_th.sv   \
-    $script_dir/../../verilog/rtl/lib/reset_sync.sv      \
-    $script_dir/../../verilog/rtl/lib/double_sync_low.v  \
-    $script_dir/../../verilog/rtl/lib/clk_ctl.v          \
-    $script_dir/../../verilog/rtl/lib/registers.v        \
-    $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v      \
-    $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v     \
-    $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_top.v           \
-    $script_dir/../../verilog/rtl/uart_i2c/src/uart_i2c_top.sv       \
-    "
-
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/i2cm/src/includes ]
-
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
-
-set ::env(LEC_ENABLE) 0
-
-set ::env(VDD_PIN) [list {vccd1}]
-set ::env(GND_PIN) [list {vssd1}]
-
-
-# Floorplanning
-# -------------
-
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-set ::env(FP_SIZING) "absolute"
-set ::env(DIE_AREA) [list 0.0 0.0 300.0 400.0]
-
-
-
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0
-
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
-
-
-set ::env(PL_ROUTABILITY_DRIVEN) 1
-
-set ::env(FP_IO_VEXTEND) 4
-set ::env(FP_IO_HEXTEND) 4
-
-
-set ::env(GLB_RT_MAXLAYER) 4
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-
-set ::env(DIODE_INSERTION_STRATEGY) 4
-
-set ::env(FP_PDN_VPITCH) 100
-set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 5
-set ::env(FP_PDN_HWIDTH) 5
diff --git a/openlane/uart_i2cm/pdn.tcl b/openlane/uart_i2cm/pdn.tcl
deleted file mode 100644
index 1fe689b..0000000
--- a/openlane/uart_i2cm/pdn.tcl
+++ /dev/null
@@ -1,49 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-# Power nets
-set ::power_nets $::env(VDD_PIN)
-set ::ground_nets $::env(GND_PIN)
-
-set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
-
-pdngen::specify_grid stdcell {
-    name grid
-    rails {
-	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
-    }
-    straps {
-	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
-	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
-    }
-    connect {{met1 met4} {met4 met5}}
-}
-
-pdngen::specify_grid macro {
-    power_pins "VPWR"
-    ground_pins "VGND"
-    blockages "li1 met1 met2 met3 met4"
-    straps { 
-    } 
-    connect {{met4_PIN_ver met5}}
-}
-
-set ::halo 5
-
-# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
-set ::rails_start_with "POWER" ;
-
-# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
-set ::stripes_start_with "POWER" ;
diff --git a/openlane/uart_i2cm/pin_order.cfg b/openlane/uart_i2cm/pin_order.cfg
deleted file mode 100644
index 870fa34..0000000
--- a/openlane/uart_i2cm/pin_order.cfg
+++ /dev/null
@@ -1,40 +0,0 @@
-#BUS_SORT
-#MANUAL_PLACE
-
-#S
-app_clk                0000 0
-uart_rstn    
-i2c_rstn 
-uart_i2c_sel            
-io_in\[1\]             
-io_out\[1\]             
-io_oeb\[1\]             
-io_in\[0\]             
-io_out\[0\]             
-io_oeb\[0\]             
-
-#N
-reg_cs                 0000 0
-reg_wr                 0000 1
-reg_addr\[3\]          0000 4
-reg_addr\[2\]          0000 5
-reg_addr\[1\]          0000 6
-reg_addr\[0\]          0000 7
-reg_be                 0000 10
-reg_wdata\[7\]         0000 11
-reg_wdata\[6\]         0000 12
-reg_wdata\[5\]         0000 13
-reg_wdata\[4\]         0000 14
-reg_wdata\[3\]         0000 15
-reg_wdata\[2\]         0000 16
-reg_wdata\[1\]         0000 17
-reg_wdata\[0\]         0000 18
-reg_rdata\[7\]         0000 19
-reg_rdata\[6\]         0000 20
-reg_rdata\[5\]         0000 21
-reg_rdata\[4\]         0000 22
-reg_rdata\[3\]         0000 23
-reg_rdata\[2\]         0000 24
-reg_rdata\[1\]         0000 25
-reg_rdata\[0\]         0000 26
-reg_ack                0000 27
diff --git a/openlane/uart_i2cm/sta.tcl b/openlane/uart_i2cm/sta.tcl
deleted file mode 100644
index ef1ab52..0000000
--- a/openlane/uart_i2cm/sta.tcl
+++ /dev/null
@@ -1,56 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
-set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
-set ::env(CURRENT_NETLIST) /project/openlane/uart_i2cm/runs/uart_i2cm/results/lvs/uart_i2c_top.lvs.powered.v
-set ::env(DESIGN_NAME) "uart_i2c_top"
-set ::env(CURRENT_SPEF) /project/openlane/uart_i2cm/runs/uart_i2cm/results/routing/uart_i2c_top.spef
-set ::env(BASE_SDC_FILE) "/project/openlane/uart_i2cm/base.sdc"
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
-set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-set ::env(SYNTH_CAP_LOAD) "17.65"
-set ::env(WIRE_RC_LAYER) "met1"
-
-
-set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
-read_liberty -min $::env(LIB_FASTEST)
-read_liberty -max $::env(LIB_SLOWEST)
-read_verilog $::env(CURRENT_NETLIST)
-link_design  $::env(DESIGN_NAME)
-
-read_spef  $::env(CURRENT_SPEF)
-
-read_sdc -echo $::env(BASE_SDC_FILE)
-
-# check for missing constraints
-#check_setup  -verbose > unconstraints.rpt
-
-set_operating_conditions -analysis_type bc_wc
-# Propgate the clock
-set_propagated_clock [all_clocks]
-
-report_tns
-report_wns
-report_power 
-report_checks -unique -slack_max -0.0 -group_count 100 
-report_checks -unique -slack_min -0.0 -group_count 100 
-report_checks -path_delay min_max 
-report_checks -group_count 100  -slack_max -0.01 
-
-
-
-
diff --git a/openlane/uart_i2cm_usb/base.sdc b/openlane/uart_i2cm_usb/base.sdc
deleted file mode 100644
index 3d3a783..0000000
--- a/openlane/uart_i2cm_usb/base.sdc
+++ /dev/null
@@ -1,82 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-
-set_units -time ns
-set ::env(CORE_CLOCK_PERIOD) "10"
-set ::env(CORE_CLOCK_PORT)   "app_clk"
-set ::env(CORE_CLOCK_NAME)   "app_clk"
-
-set ::env(LINE_CLOCK_PERIOD) "100"
-set ::env(LINE_CLOCK_PORT)   "u_uart_core.u_lineclk_buf/X"
-set ::env(LINE_CLOCK_NAME)   "line_clk"
-
-set ::env(USB_CLOCK_PERIOD) "100"
-set ::env(USB_CLOCK_PORT)   "usb_clk"
-set ::env(USB_CLOCK_NAME)   "usb_clk"
-
-######################################
-# WB Clock domain input output
-######################################
-create_clock [get_ports $::env(CORE_CLOCK_PORT)]  -name $::env(CORE_CLOCK_NAME)  -period $::env(CORE_CLOCK_PERIOD)
-create_clock [get_pins  $::env(LINE_CLOCK_PORT)]  -name $::env(LINE_CLOCK_NAME)  -period $::env(LINE_CLOCK_PERIOD)
-create_clock [get_ports $::env(USB_CLOCK_PORT)]  -name $::env(USB_CLOCK_NAME)  -period $::env(USB_CLOCK_PERIOD)
-
-set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
-set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
-
-set line_input_delay_value  [expr $::env(LINE_CLOCK_PERIOD) * 0.6]
-set line_output_delay_value [expr $::env(LINE_CLOCK_PERIOD) * 0.6]
-
-set usb_input_delay_value  [expr $::env(USB_CLOCK_PERIOD) * 0.6]
-set usb_output_delay_value [expr $::env(USB_CLOCK_PERIOD) * 0.6]
-puts "\[INFO\]: Setting wb output delay to:$core_output_delay_value"
-puts "\[INFO\]: Setting wb input delay to: $core_input_delay_value"
-
-
-set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {uart_rstn}
-set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {i2c_rstn}
-set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {usb_rstn}
-
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_cs*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_addr*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wr*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_be*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wdata*]
-
-
-set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_rdata*]
-set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_ack*]
-
-set_input_delay  $line_input_delay_value   -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_in*]
-set_output_delay $line_input_delay_value   -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_oeb*]
-set_output_delay $line_output_delay_value  -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_out*]
-
-
-set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(CORE_CLOCK_NAME)] -group [get_clocks $::env(LINE_CLOCK_NAME)] 
-
-set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)   -to $::env(CORE_CLOCK_NAME)  -setup 0.400
-set_clock_uncertainty -from $::env(LINE_CLOCK_NAME)   -to $::env(LINE_CLOCK_NAME) -setup 0.400
-
-set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)   -to $::env(CORE_CLOCK_NAME)  -hold 0.050
-set_clock_uncertainty -from $::env(LINE_CLOCK_NAME)   -to $::env(LINE_CLOCK_NAME) -hold 0.050
-
-# TODO set this as parameter
-set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
-puts "\[INFO\]: Setting load to: $cap_load"
-set_load  $cap_load [all_outputs]
-
diff --git a/openlane/uart_i2cm_usb/config.tcl b/openlane/uart_i2cm_usb/config.tcl
deleted file mode 100644
index 8888d8a..0000000
--- a/openlane/uart_i2cm_usb/config.tcl
+++ /dev/null
@@ -1,108 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-# Global
-# ------
-
-set script_dir [file dirname [file normalize [info script]]]
-# Name
-set ::env(DESIGN_NAME) uart_i2c_usb_top
-
-
-set ::env(DESIGN_IS_CORE) "0"
-set ::env(FP_PDN_CORE_RING) "0"
-
-# Timing configuration
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "app_clk usb_clk"
-
-set ::env(SYNTH_MAX_FANOUT) 4
-
-# Sources
-# -------
-
-# Local sources + no2usb sources
-set ::env(VERILOG_FILES) "\
-    $script_dir/../../verilog/rtl/uart/src/uart_core.sv  \
-    $script_dir/../../verilog/rtl/uart/src/uart_cfg.sv   \
-    $script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \
-    $script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \
-    $script_dir/../../verilog/rtl/lib/async_wb.sv   \
-    $script_dir/../../verilog/rtl/lib/async_fifo.sv      \
-    $script_dir/../../verilog/rtl/lib/async_fifo_th.sv   \
-    $script_dir/../../verilog/rtl/lib/reset_sync.sv      \
-    $script_dir/../../verilog/rtl/lib/double_sync_low.v  \
-    $script_dir/../../verilog/rtl/lib/clk_ctl.v          \
-    $script_dir/../../verilog/rtl/lib/registers.v        \
-    $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v      \
-    $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v     \
-    $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_top.v           \
-    $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_core.sv    \
-    $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_crc16.sv   \
-    $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_crc5.sv    \
-    $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_fifo.sv    \  
-    $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_sie.sv     \
-    $script_dir/../../verilog/rtl/usb1_host/src/phy/usb_fs_phy.v     \
-    $script_dir/../../verilog/rtl/usb1_host/src/phy/usb_transceiver.v\
-    $script_dir/../../verilog/rtl/usb1_host/src/top/usb1_host.sv     \
-    $script_dir/../../verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv\
-    "
-
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/i2cm/src/includes $script_dir/../../verilog/rtl/usb1_host/src/includes ]
-
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
-
-set ::env(LEC_ENABLE) 0
-
-set ::env(VDD_PIN) [list {vccd1}]
-set ::env(GND_PIN) [list {vssd1}]
-
-
-# Floorplanning
-# -------------
-
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-set ::env(FP_SIZING) "absolute"
-set ::env(DIE_AREA) [list 0.0 0.0 600.0 700.0]
-
-set ::env(PL_TARGET_DENSITY) "0.45"
-
-
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0
-
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
-
-
-set ::env(PL_ROUTABILITY_DRIVEN) 1
-
-# helps in anteena fix
-set ::env(USE_ARC_ANTENNA_CHECK) "0"
-
-set ::env(FP_IO_VEXTEND) 4
-set ::env(FP_IO_HEXTEND) 4
-
-
-set ::env(GLB_RT_MAXLAYER) 4
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-set ::env(DIODE_INSERTION_STRATEGY) 5
-
-set ::env(FP_PDN_VPITCH) 100
-set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 5
-set ::env(FP_PDN_HWIDTH) 5
diff --git a/openlane/uart_i2cm_usb/pdn.tcl b/openlane/uart_i2cm_usb/pdn.tcl
deleted file mode 100644
index 1fe689b..0000000
--- a/openlane/uart_i2cm_usb/pdn.tcl
+++ /dev/null
@@ -1,49 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-# Power nets
-set ::power_nets $::env(VDD_PIN)
-set ::ground_nets $::env(GND_PIN)
-
-set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
-
-pdngen::specify_grid stdcell {
-    name grid
-    rails {
-	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
-    }
-    straps {
-	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
-	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
-    }
-    connect {{met1 met4} {met4 met5}}
-}
-
-pdngen::specify_grid macro {
-    power_pins "VPWR"
-    ground_pins "VGND"
-    blockages "li1 met1 met2 met3 met4"
-    straps { 
-    } 
-    connect {{met4_PIN_ver met5}}
-}
-
-set ::halo 5
-
-# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
-set ::rails_start_with "POWER" ;
-
-# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
-set ::stripes_start_with "POWER" ;
diff --git a/openlane/uart_i2cm_usb/pin_order.cfg b/openlane/uart_i2cm_usb/pin_order.cfg
deleted file mode 100644
index cd4e00c..0000000
--- a/openlane/uart_i2cm_usb/pin_order.cfg
+++ /dev/null
@@ -1,105 +0,0 @@
-#BUS_SORT
-#MANUAL_PLACE
-
-#S
-app_clk                0000 0
-usb_clk
-
-reg_cs                 
-reg_wr                 
-reg_addr\[7\]          
-reg_addr\[6\]          
-reg_addr\[5\]          
-reg_addr\[4\]          
-reg_addr\[3\]          
-reg_addr\[2\]          
-reg_addr\[1\]          
-reg_addr\[0\]          
-reg_be                 
-reg_wdata\[31\]         
-reg_wdata\[30\]         
-reg_wdata\[29\]         
-reg_wdata\[28\]         
-reg_wdata\[27\]         
-reg_wdata\[26\]         
-reg_wdata\[25\]         
-reg_wdata\[24\]         
-reg_wdata\[23\]         
-reg_wdata\[22\]         
-reg_wdata\[21\]         
-reg_wdata\[20\]         
-reg_wdata\[19\]         
-reg_wdata\[18\]         
-reg_wdata\[17\]         
-reg_wdata\[16\]         
-reg_wdata\[15\]         
-reg_wdata\[14\]         
-reg_wdata\[13\]         
-reg_wdata\[12\]         
-reg_wdata\[11\]         
-reg_wdata\[10\]         
-reg_wdata\[9\]         
-reg_wdata\[8\]         
-reg_wdata\[7\]         
-reg_wdata\[6\]         
-reg_wdata\[5\]         
-reg_wdata\[4\]         
-reg_wdata\[3\]         
-reg_wdata\[2\]         
-reg_wdata\[1\]         
-reg_wdata\[0\]  
-       
-reg_rdata\[31\]         
-reg_rdata\[30\]         
-reg_rdata\[29\]         
-reg_rdata\[28\]         
-reg_rdata\[27\]         
-reg_rdata\[26\]         
-reg_rdata\[25\]         
-reg_rdata\[24\]         
-reg_rdata\[23\]         
-reg_rdata\[22\]         
-reg_rdata\[21\]         
-reg_rdata\[20\]         
-reg_rdata\[19\]         
-reg_rdata\[18\]         
-reg_rdata\[17\]         
-reg_rdata\[16\]         
-reg_rdata\[15\]         
-reg_rdata\[14\]         
-reg_rdata\[13\]         
-reg_rdata\[12\]         
-reg_rdata\[11\]         
-reg_rdata\[10\]         
-reg_rdata\[9\]         
-reg_rdata\[8\]         
-reg_rdata\[7\]         
-reg_rdata\[6\]         
-reg_rdata\[5\]         
-reg_rdata\[4\]         
-reg_rdata\[3\]         
-reg_rdata\[2\]         
-reg_rdata\[1\]         
-reg_rdata\[0\]         
-reg_ack                
-
-
-uart_rstn    
-i2c_rstn 
-usb_rstn 
-scl_pad_i 
-scl_pad_o
-scl_pad_oen_o
-sda_pad_i
-sda_pad_o
-sda_padoen_o
-uart_rxd
-uart_txd
-usb_in_dp
-usb_in_dn
-usb_out_dp
-usb_out_dn
-usb_out_tx_oen
-
-         
-
diff --git a/openlane/uart_i2cm_usb/sta.tcl b/openlane/uart_i2cm_usb/sta.tcl
deleted file mode 100644
index ef1ab52..0000000
--- a/openlane/uart_i2cm_usb/sta.tcl
+++ /dev/null
@@ -1,56 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
-set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
-set ::env(CURRENT_NETLIST) /project/openlane/uart_i2cm/runs/uart_i2cm/results/lvs/uart_i2c_top.lvs.powered.v
-set ::env(DESIGN_NAME) "uart_i2c_top"
-set ::env(CURRENT_SPEF) /project/openlane/uart_i2cm/runs/uart_i2cm/results/routing/uart_i2c_top.spef
-set ::env(BASE_SDC_FILE) "/project/openlane/uart_i2cm/base.sdc"
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
-set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-set ::env(SYNTH_CAP_LOAD) "17.65"
-set ::env(WIRE_RC_LAYER) "met1"
-
-
-set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
-read_liberty -min $::env(LIB_FASTEST)
-read_liberty -max $::env(LIB_SLOWEST)
-read_verilog $::env(CURRENT_NETLIST)
-link_design  $::env(DESIGN_NAME)
-
-read_spef  $::env(CURRENT_SPEF)
-
-read_sdc -echo $::env(BASE_SDC_FILE)
-
-# check for missing constraints
-#check_setup  -verbose > unconstraints.rpt
-
-set_operating_conditions -analysis_type bc_wc
-# Propgate the clock
-set_propagated_clock [all_clocks]
-
-report_tns
-report_wns
-report_power 
-report_checks -unique -slack_max -0.0 -group_count 100 
-report_checks -unique -slack_min -0.0 -group_count 100 
-report_checks -path_delay min_max 
-report_checks -group_count 100  -slack_max -0.01 
-
-
-
-
diff --git a/openlane/yifive/config.tcl b/openlane/yifive/config.tcl
deleted file mode 100644
index 2fe0330..0000000
--- a/openlane/yifive/config.tcl
+++ /dev/null
@@ -1,121 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-# Base Configurations. Don't Touch
-# section begin
-set script_dir [file dirname [file normalize [info script]]]
-
-source $script_dir/../../caravel/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
-
-set ::env(DESIGN_NAME) yifive
-set verilog_root $script_dir/../../verilog/
-set lef_root $script_dir/../../lef/
-set gds_root $script_dir/../../gds/
-#section end
-
-# User Configurations
-#
-set ::env(DESIGN_IS_CORE) 1
-set ::env(FP_PDN_CORE_RING) 1
-
-
-## Source Verilog Files
-set ::env(VERILOG_FILES) "\
-	$script_dir/../../caravel/verilog/rtl/defines.v \
-	$script_dir/yifive.v"
-
-## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2 wb_clk_i"
-#set ::env(CLOCK_NET) "mprj.clk"
-
-set ::env(CLOCK_PERIOD) "10"
-
-## Internal Macros
-### Macro Placement
-set ::env(FP_SIZING) "absolute"
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
-
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
-
-
-### Black-box verilog and views
-set ::env(VERILOG_FILES_BLACKBOX) "\
-        $script_dir/../../verilog/gl/spi_master.v \
-        $script_dir/../../verilog/gl/wb_interconnect.v \
-        $script_dir/../../verilog/gl/glbl_cfg.v     \
-        $script_dir/../../verilog/gl/uart.v     \
-	$script_dir/../../verilog/gl/sdram.v \
-	$script_dir/../../verilog/gl/wb_host.v \
-	$script_dir/../../verilog/gl/clk_skew_adjust.v \
-	$script_dir/../../verilog/gl/syntacore.v \
-	"
-
-set ::env(EXTRA_LEFS) "\
-	$lef_root/spi_master.lef \
-	$lef_root/glbl_cfg.lef \
-	$lef_root/wb_interconnect.lef \
-	$lef_root/sdram.lef \
-	$lef_root/uart.lef \
-	$lef_root/wb_host.lef \
-	$lef_root/clk_skew_adjust.lef \
-	$lef_root/syntacore.lef \
-	"
-
-set ::env(EXTRA_GDS_FILES) "\
-	$gds_root/spi_master.gds \
-	$gds_root/glbl_cfg.gds \
-	$gds_root/wb_interconnect.gds \
-	$gds_root/uart.gds \
-	$gds_root/sdram.gds \
-	$gds_root/wb_host.gds \
-	$gds_root/clk_skew_adjust.gds \
-	$gds_root/syntacore.gds \
-	"
-
-set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
-
-set ::env(GLB_RT_MAXLAYER) 5
-
-set ::env(FP_PDN_CHECK_NODES) 0
-
-set ::env(RUN_KLAYOUT_DRC) 0
-
-set ::env(VDD_PIN) [list {vccd1}]
-set ::env(GND_PIN) [list {vssd1}]
-
-
-# The following is because there are no std cells in the example wrapper project.
-#set ::env(SYNTH_TOP_LEVEL) 1
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-
-set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
-#
-set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FILL_INSERTION) 0
-set ::env(TAP_DECAP_INSERTION) 0
-set ::env(CLOCK_TREE_SYNTH) 0
-
-#set ::env(MAGIC_EXT_USE_GDS) "1"
-
-
-set ::env(PL_DIAMOND_SEARCH_HEIGHT) "250"
-
-
diff --git a/openlane/yifive/pin_order.cfg b/openlane/yifive/pin_order.cfg
deleted file mode 100644
index 90cde69..0000000
--- a/openlane/yifive/pin_order.cfg
+++ /dev/null
@@ -1,156 +0,0 @@
-#BUS_SORT
-#NR
-analog_io\[8\]
-io_in\[15\]
-io_out\[15\]
-io_oeb\[15\]
-analog_io\[9\]
-io_in\[16\]
-io_out\[16\]
-io_oeb\[16\]
-analog_io\[10\]
-io_in\[17\]
-io_out\[17\]
-io_oeb\[17\]
-analog_io\[11\]
-io_in\[18\]
-io_out\[18\]
-io_oeb\[18\]
-analog_io\[12\]
-io_in\[19\]
-io_out\[19\]
-io_oeb\[19\]
-analog_io\[13\]
-io_in\[20\]
-io_out\[20\]
-io_oeb\[20\]
-analog_io\[14\]
-io_in\[21\]
-io_out\[21\]
-io_oeb\[21\]
-analog_io\[15\]
-io_in\[22\]
-io_out\[22\]
-io_oeb\[22\]
-analog_io\[16\]
-io_in\[23\]
-io_out\[23\]
-io_oeb\[23\]
-
-#S
-wb_.*
-wbs_.*
-la_.*
-user_clock2
-user_irq.*
-
-#E
-io_in\[0\]
-io_out\[0\]
-io_oeb\[0\]
-io_in\[1\]
-io_out\[1\]
-io_oeb\[1\]
-io_in\[2\]
-io_out\[2\]
-io_oeb\[2\]
-io_in\[3\]
-io_out\[3\]
-io_oeb\[3\]
-io_in\[4\]
-io_out\[4\]
-io_oeb\[4\]
-io_in\[5\]
-io_out\[5\]
-io_oeb\[5\]
-io_in\[6\]
-io_out\[6\]
-io_oeb\[6\]
-analog_io\[0\]
-io_in\[7\]
-io_out\[7\]
-io_oeb\[7\]
-analog_io\[1\]
-io_in\[8\]
-io_out\[8\]
-io_oeb\[8\]
-analog_io\[2\]
-io_in\[9\]
-io_out\[9\]
-io_oeb\[9\]
-analog_io\[3\]
-io_in\[10\]
-io_out\[10\]
-io_oeb\[10\]
-analog_io\[4\]
-io_in\[11\]
-io_out\[11\]
-io_oeb\[11\]
-analog_io\[5\]
-io_in\[12\]
-io_out\[12\]
-io_oeb\[12\]
-analog_io\[6\]
-io_in\[13\]
-io_out\[13\]
-io_oeb\[13\]
-analog_io\[7\]
-io_in\[14\]
-io_out\[14\]
-io_oeb\[14\]
-
-#WR
-analog_io\[17\]
-io_in\[24\]
-io_out\[24\]
-io_oeb\[24\]
-analog_io\[18\]
-io_in\[25\]
-io_out\[25\]
-io_oeb\[25\]
-analog_io\[19\]
-io_in\[26\]
-io_out\[26\]
-io_oeb\[26\]
-analog_io\[20\]
-io_in\[27\]
-io_out\[27\]
-io_oeb\[27\]
-analog_io\[21\]
-io_in\[28\]
-io_out\[28\]
-io_oeb\[28\]
-analog_io\[22\]
-io_in\[29\]
-io_out\[29\]
-io_oeb\[29\]
-analog_io\[23\]
-io_in\[30\]
-io_out\[30\]
-io_oeb\[30\]
-analog_io\[24\]
-io_in\[31\]
-io_out\[31\]
-io_oeb\[31\]
-analog_io\[25\]
-io_in\[32\]
-io_out\[32\]
-io_oeb\[32\]
-analog_io\[26\]
-io_in\[33\]
-io_out\[33\]
-io_oeb\[33\]
-analog_io\[27\]
-io_in\[34\]
-io_out\[34\]
-io_oeb\[34\]
-analog_io\[28\]
-io_in\[35\]
-io_out\[35\]
-io_oeb\[35\]
-io_in\[36\]
-io_out\[36\]
-io_oeb\[36\]
-io_in\[37\]
-io_out\[37\]
-io_oeb\[37\]