diff --git a/openlane/Makefile b/openlane/Makefile
index e2e91a5..4d42a79 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -1,5 +1,4 @@
 # SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
@@ -13,16 +12,16 @@
 # limitations under the License.
 #
 # SPDX-License-Identifier: Apache-2.0
-
 #SHELL = sh -xv
+
 BLOCKS = $(shell find * -maxdepth 0 -type d)
 CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
 CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
 
-OPENLANE_TAG = mpw5
+OPENLANE_TAG = mpw6
 OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)
-OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
-OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
+OPENLANE_BASIC_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
+OPENLANE_INTERACTIVE_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite -it -file ./$*/interactive.tcl"
 
 all: $(BLOCKS)
 
@@ -30,18 +29,45 @@
 	@echo "Missing $@. Please create a configuration for that design"
 	@exit 1
 
-$(BLOCKS) : % : ./%/config.tcl FORCE
+.PHONY: $(BLOCKS)
+$(BLOCKS) : % : ./%/config.tcl
+ifeq ($(OPENLANE_ROOT),)
+	@echo "Please export OPENLANE_ROOT"
+	@exit 1
+endif
+ifeq ($(PDK_ROOT),)
+	@echo "Please export PDK_ROOT"
+	@exit 1
+endif
 	@echo "###############################################"
 	@sleep 1
 
 	@if [ -f ./$*/interactive.tcl ]; then\
-		docker run -it  \
-		-v $(PWD)/..:/project \
+		docker run --rm -v $(OPENLANE_ROOT):/openlane \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(PWD)/..:$(PWD)/.. \
+		-v $(MCW_ROOT):$(MCW_ROOT) \
+		-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+		-e MCW_ROOT=$(MCW_ROOT) \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+		-e PDK=$(PDK) \
+		-e TEST_MISMATCHES=tools \
+		-e MISMATCHES_OK=1 \
 		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
 		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
 	else\
-		docker run -it  \
-		-v $(PWD)/..:/project \
+		docker run --rm -v $(OPENLANE_ROOT):/openlane \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(PWD)/..:$(PWD)/.. \
+		-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+		-v $(MCW_ROOT):$(MCW_ROOT) \
+		-e MCW_ROOT=$(MCW_ROOT) \
+		-e PDK=$(PDK) \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+		-e TEST_MISMATCHES=tools \
+		-e MISMATCHES_OK=1 \
 		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
 		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
 	fi
@@ -50,6 +76,25 @@
 	cp $*/runs/$*/PDK_SOURCES ../signoff/$*/
 	cp $*/runs/$*/reports/final_summary_report.csv ../signoff/$*/
 
+.PHONY: openlane
+openlane: check-openlane-env
+	if [ -d "$(OPENLANE_ROOT)" ]; then\
+		echo "Deleting exisiting $(OPENLANE_ROOT)" && \
+		rm -rf $(OPENLANE_ROOT) && sleep 2; \
+	fi
+	git clone https://github.com/The-OpenROAD-Project/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
+		cd $(OPENLANE_ROOT) && \
+		export OPENLANE_IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+		export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+		$(MAKE) pull-openlane
+
+.PHONY: check-openlane-env
+check-openlane-env:
+ifeq ($(OPENLANE_ROOT),)
+	@echo "Please export OPENLANE_ROOT"
+	@exit 1
+endif
+
 FORCE:
 
 clean:
diff --git a/openlane/mbist/base.sdc b/openlane/mbist/base.sdc
deleted file mode 100644
index 26a1fe6..0000000
--- a/openlane/mbist/base.sdc
+++ /dev/null
@@ -1,128 +0,0 @@
-###############################################################################
-# Created by write_sdc
-# Sun Nov 14 09:33:23 2021
-###############################################################################
-current_design mbist_top
-###############################################################################
-# Timing Constraints
-###############################################################################
-create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}]
-create_clock -name wb_clk2_i -period 10.0000 [get_ports {wb_clk2_i}]
-create_generated_clock -name bist_mem_clk_a -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks wb_clk2_i] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a]
-create_generated_clock -name bist_mem_clk_b -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks wb_clk2_i] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b]
-
-set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks {bist_mem_clk_a bist_mem_clk_b}]  -group [get_clocks {wb_clk_i }] -group [get_clocks {wb_clk2_i}]
-
-set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
-set_clock_uncertainty -hold 0.2500 [all_clocks]
-
-set ::env(SYNTH_TIMING_DERATE) 0.05
-puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
-set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
-set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
-
-set_input_delay  -max 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}]
-set_input_delay  -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}]
-
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}]
-
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}]
-
-set_false_path -from [get_ports {bist_en}]
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}]
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}]
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}]
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}]
-
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_en}]
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}]
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}]
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}]
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}]
-
-## Functional Inputs
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_adr_i[*]}]  
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_stb_i}]      
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_cyc_i}]      
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_we_i}]      
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wbd_mbist1_dat_o[*]}] 
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_sel_i[*]}]
-
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_adr_i[*]}]  
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_stb_i}]      
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_cyc_i}]      
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_we_i}]      
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wbd_mbist1_dat_o[*]}] 
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_sel_i[*]}]
-
-set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_dat_o[*]}]  
-set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_ack_o}]  
-set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_err_o}]  
-
-set_output_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_dat_o[*]}]  
-set_output_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_ack_o}]  
-set_output_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_err_o}]  
-
-## Towards MEMORY from MBIST CLOCK
-## PORT-A
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}]
-
-
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
-
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
-
-
-
-## PORT-B
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}]
-
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}]
-
-
-# Set max delay for clock skew
-
-set_max_delay   3.5 -from [get_ports {wbd_clk_int}]
-set_max_delay   2 -to   [get_ports {wbd_clk_mbist}]
-set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_mbist
-
-###############################################################################
-# Environment
-###############################################################################
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
-puts "\[INFO\]: Setting load to: $cap_load"
-set_load  $cap_load [all_outputs]
-
-set_timing_derate -early 0.9500
-set_timing_derate -late 1.0500
-###############################################################################
-# Design Rules
-###############################################################################
-set_max_fanout 4.0000 [current_design]
diff --git a/openlane/mbist/config.tcl b/openlane/mbist/config.tcl
deleted file mode 100755
index 78cd955..0000000
--- a/openlane/mbist/config.tcl
+++ /dev/null
@@ -1,123 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-# Global
-# ------
-
-set script_dir [file dirname [file normalize [info script]]]
-# Name
-
-set ::env(DESIGN_NAME) mbist_top
-
-set ::env(DESIGN_IS_CORE) "0"
-
-# Timing configuration
-set ::env(CLOCK_PERIOD) "10"
-#set ::env(CLOCK_PORT) "u_cts_wb_clk_b1.u_buf/X  \
-#	               u_cts_wb_clk_b2.u_buf/X  \
-#		       "
-set ::env(CLOCK_PORT) { wb_clk_i mem_no\[3\].u_mem_sel.u_mem_clk_sel.u_mux/X mem_no\[2\].u_mem_sel.u_mem_clk_sel.u_mux/X mem_no\[1\].u_mem_sel.u_mem_clk_sel.u_mux/X mem_no\[0\].u_mem_sel.u_mem_clk_sel.u_mux/X  }
-
-set ::env(SYNTH_MAX_FANOUT) 4
-
-## CTS BUFFER
-set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
-set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
-set ::env(CLOCK_BUFFER_FANOUT) "8"
-
-
-# Sources
-# -------
-
-# Local sources + no2usb sources
-set ::env(VERILOG_FILES) "\
-     $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_addr_gen.sv \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_fsm.sv     \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_op_sel.sv  \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_repair_addr.sv \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_sti_sel.sv \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_pat_sel.sv \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_mux.sv \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_data_cmp.sv \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv \
-     $script_dir/../../verilog/rtl/mbist/src/top/mbist_top.sv  \
-     $script_dir/../../verilog/rtl/lib/ctech_cells.sv     \
-     $script_dir/../../verilog/rtl/lib/reset_sync.sv \
-     $script_dir/../../verilog/rtl/lib/ser_shift.sv \
-	     "
-
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/mbist/include ]
-set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-
-
-set ::env(SYNTH_PARAMS) "BIST_ADDR_WD 9,\
-	                 BIST_DATA_WD 32,\
-		         BIST_ADDR_START 9'h000,\
-			 BIST_ADDR_END 9'h1FB,\
-			 BIST_REPAIR_ADDR_START 9'h1FC,\
-			 BIST_RAD_WD_I 9,\
-			 BIST_RAD_WD_O 9\
-			 "
-
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
-
-set ::env(LEC_ENABLE) 0
-
-set ::env(VDD_PIN) [list {vccd1}]
-set ::env(GND_PIN) [list {vssd1}]
-
-
-# Floorplanning
-# -------------
-
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 1500 200"
-
-
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 1
-
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
-
-
-set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.30"
-
-
-
-set ::env(FP_IO_VEXTEND) 4
-set ::env(FP_IO_HEXTEND) 4
-
-set ::env(FP_PDN_VPITCH) 140
-set ::env(FP_PDN_HPITCH) 140
-set ::env(FP_PDN_VWIDTH) 5
-set ::env(FP_PDN_HWIDTH) 5
-
-set ::env(GLB_RT_MAXLAYER) 5
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-
-set ::env(DIODE_INSERTION_STRATEGY) 4
-
-
-set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
-set ::env(QUIT_ON_MAGIC_DRC) "1"
-set ::env(QUIT_ON_LVS_ERROR) "0"
-set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/mbist/interactive.tcl b/openlane/mbist/interactive.tcl
deleted file mode 100644
index f59586f..0000000
--- a/openlane/mbist/interactive.tcl
+++ /dev/null
@@ -1,219 +0,0 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-package require openlane;
-
-
-proc run_placement_step {args} {
-    # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
-    # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
-    # set_def $pdndef
-    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
-        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
-    }
-
-    run_placement
-}
-
-proc run_cts_step {args} {
-    # set_def $::env(opendp_result_file_tag).def
-    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
-        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
-    }
-
-    run_cts
-    run_resizer_timing
-}
-
-proc run_routing_step {args} {
-    # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
-    # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
-    # set_def $resizerdef
-    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
-        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
-    }
-    run_routing
-}
-
-proc run_diode_insertion_2_5_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
-        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
-    }
-	if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
-		run_antenna_check
-		heal_antenna_violators; # modifies the routed DEF
-	}
-
-}
-
-proc run_power_pins_insertion_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
-        set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
-    }
-    if { $::env(LVS_INSERT_POWER_PINS) } {
-		write_powered_verilog
-		set_netlist $::env(lvs_result_file_tag).powered.v
-    }
-
-}
-
-proc run_lvs_step {{ lvs_enabled 1 }} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
-        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
-    }
-	if { $lvs_enabled } {
-		run_magic_spice_export
-		run_lvs; # requires run_magic_spice_export
-	}
-
-}
-
-proc run_drc_step {{ drc_enabled 1 }} {
-    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
-        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
-    }
-	if { $drc_enabled } {
-		run_magic_drc
-		run_klayout_drc
-	}
-}
-
-proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
-    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
-        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
-    }
-	if { $antenna_check_enabled } {
-		run_antenna_check
-	}
-}
-
-proc run_flow {args} {
-       set script_dir [file dirname [file normalize [info script]]]
-
-		set options {
-		{-design required}
-		{-save_path optional}
-		{-no_lvs optional}
-	    {-no_drc optional}
-	    {-no_antennacheck optional}
-	}
-	set flags {-save}
-	parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
-
-	prep {*}$args
-
-        set LVS_ENABLED 1
-        set DRC_ENABLED 1
-        set ANTENNACHECK_ENABLED 1
-
-        set steps [dict create "synthesis" {run_synthesis "" } \
-                "floorplan" {run_floorplan ""} \
-                "placement" {run_placement_step ""} \
-                "cts" {run_cts_step ""} \
-                "routing" {run_routing_step ""}\
-                "diode_insertion" {run_diode_insertion_2_5_step ""} \
-                "power_pins_insertion" {run_power_pins_insertion_step ""} \
-                "gds_magic" {run_magic ""} \
-                "gds_drc_klayout" {run_klayout ""} \
-                "gds_xor_klayout" {run_klayout_gds_xor ""} \
-                "lvs" "run_lvs_step $LVS_ENABLED" \
-                "drc" "run_drc_step $DRC_ENABLED" \
-                "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
-                "cvc" {run_lef_cvc}
-        ]
-
-       set_if_unset arg_values(-to) "cvc";
-
-       if {  [info exists ::env(CURRENT_STEP) ] } {
-           puts "\[INFO\]:Picking up where last execution left off"
-           puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
-       } else {
-           set ::env(CURRENT_STEP) "synthesis";
-       }
-       set_if_unset arg_values(-from) $::env(CURRENT_STEP);
-       set exe 0;
-       dict for {step_name step_exe} $steps {
-           if { [ string equal $arg_values(-from) $step_name ] } {
-               set exe 1;
-           }
-
-           if { $exe } {
-               # For when it fails
-               set ::env(CURRENT_STEP) $step_name
-               [lindex $step_exe 0] [lindex $step_exe 1] ;
-           }
-
-           if { [ string equal $arg_values(-to) $step_name ] } {
-               set exe 0:
-               break;
-           }
-
-       }
-
-       # for when it resumes
-       set steps_as_list [dict keys $steps]
-       set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
-       set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
-
-	if {  [info exists flags_map(-save) ] } {
-		if { ! [info exists arg_values(-save_path)] } {
-			set arg_values(-save_path) ""
-		}
-		save_views 	-lef_path $::env(magic_result_file_tag).lef \
-			-def_path $::env(CURRENT_DEF) \
-			-gds_path $::env(magic_result_file_tag).gds \
-			-mag_path $::env(magic_result_file_tag).mag \
-			-maglef_path $::env(magic_result_file_tag).lef.mag \
-			-spice_path $::env(magic_result_file_tag).spice \
-			-spef_path $::env(CURRENT_SPEF) \
-			-verilog_path $::env(CURRENT_NETLIST) \
-			-save_path $arg_values(-save_path) \
-			-tag $::env(RUN_TAG)
-	}
-
-
-	calc_total_runtime
-	save_state
-	generate_final_summary_report
-	
-	check_timing_violations
-
-	puts_success "Flow Completed Without Fatal Errors."
-
-}
-
-run_flow {*}$argv
diff --git a/openlane/mbist/pin_order.cfg b/openlane/mbist/pin_order.cfg
deleted file mode 100644
index 0416192..0000000
--- a/openlane/mbist/pin_order.cfg
+++ /dev/null
@@ -1,527 +0,0 @@
-#BUS_SORT
-
-#MANUAL_PLACE
-
-
-#S
-rst_n            0000 0        
-
-
-
-#E
-cfg_cska_mbist\[3\]  0000 0 4
-cfg_cska_mbist\[2\]
-cfg_cska_mbist\[1\]
-cfg_cska_mbist\[0\]
-wb_clk2_i         
-wb_clk_i         
-wbd_clk_mbist
-wbd_clk_int         
-
-wb_cyc_i            0025 0 2
-wb_stb_i
-wb_we_i
-wb_cs_i\[1\]
-wb_cs_i\[0\]
-wb_adr_i\[8\]
-wb_adr_i\[7\]
-wb_adr_i\[6\]
-wb_adr_i\[5\]
-wb_adr_i\[4\]
-wb_adr_i\[3\]
-wb_adr_i\[2\]
-wb_adr_i\[1\]
-wb_adr_i\[0\]
-wb_dat_i\[31\]
-wb_dat_i\[30\]
-wb_dat_i\[29\]
-wb_dat_i\[28\]
-wb_dat_i\[27\]
-wb_dat_i\[26\]
-wb_dat_i\[25\]
-wb_dat_i\[24\]
-wb_dat_i\[23\]
-wb_dat_i\[22\]
-wb_dat_i\[21\]
-wb_dat_i\[20\]
-wb_dat_i\[19\]
-wb_dat_i\[18\]
-wb_dat_i\[17\]
-wb_dat_i\[16\]
-wb_dat_i\[15\]
-wb_dat_i\[14\]
-wb_dat_i\[13\]
-wb_dat_i\[12\]
-wb_dat_i\[11\]
-wb_dat_i\[10\]
-wb_dat_i\[9\]
-wb_dat_i\[8\]
-wb_dat_i\[7\]
-wb_dat_i\[6\]
-wb_dat_i\[5\]
-wb_dat_i\[4\]
-wb_dat_i\[3\]
-wb_dat_i\[2\]
-wb_dat_i\[1\]
-wb_dat_i\[0\]
-wb_sel_i\[3\]
-wb_sel_i\[2\]
-wb_sel_i\[1\]
-wb_sel_i\[0\]
-wb_dat_o\[31\]
-wb_dat_o\[30\]
-wb_dat_o\[29\]
-wb_dat_o\[28\]
-wb_dat_o\[27\]
-wb_dat_o\[26\]
-wb_dat_o\[25\]
-wb_dat_o\[24\]
-wb_dat_o\[23\]
-wb_dat_o\[22\]
-wb_dat_o\[21\]
-wb_dat_o\[20\]
-wb_dat_o\[19\]
-wb_dat_o\[18\]
-wb_dat_o\[17\]
-wb_dat_o\[16\]
-wb_dat_o\[15\]
-wb_dat_o\[14\]
-wb_dat_o\[13\]
-wb_dat_o\[12\]
-wb_dat_o\[11\]
-wb_dat_o\[10\]
-wb_dat_o\[9\]
-wb_dat_o\[8\]
-wb_dat_o\[7\]
-wb_dat_o\[6\]
-wb_dat_o\[5\]
-wb_dat_o\[4\]
-wb_dat_o\[3\]
-wb_dat_o\[2\]
-wb_dat_o\[1\]
-wb_dat_o\[0\]
-wb_ack_o
-wb_err_o
-
-
-bist_error_cnt3\[3\] 0150 0 2
-bist_error_cnt3\[2\]
-bist_error_cnt3\[1\]
-bist_error_cnt3\[0\]
-bist_correct\[3\]
-bist_error\[3\]
-bist_error_cnt2\[3\]
-bist_error_cnt2\[2\]
-bist_error_cnt2\[1\]
-bist_error_cnt2\[0\]
-bist_correct\[2\]
-bist_error\[2\]
-bist_error_cnt1\[3\]
-bist_error_cnt1\[2\]
-bist_error_cnt1\[1\]
-bist_error_cnt1\[0\]
-bist_correct\[1\]
-bist_error\[1\]
-bist_error_cnt0\[3\]
-bist_error_cnt0\[2\]
-bist_error_cnt0\[1\]
-bist_error_cnt0\[0\]
-bist_correct\[0\]
-bist_error\[0\]
-bist_done
-bist_sdo
-bist_shift
-bist_sdi
-bist_load
-bist_run
-bist_en           
-
-#S
-mem_clk_a\[0\]       250 0 2
-mem_cen_a\[0\]
-mem_web_a\[0\]
-mem_addr_a0\[0\]
-mem_addr_a0\[1\]
-mem_addr_a0\[2\]
-mem_addr_a0\[3\]
-mem_addr_a0\[4\]
-mem_addr_a0\[5\]
-mem_addr_a0\[6\]
-mem_addr_a0\[7\]
-mem_addr_a0\[8\]
-mem_mask_a0\[0\]
-mem_mask_a0\[1\]
-mem_mask_a0\[2\]
-mem_mask_a0\[3\]
-mem_din_a0\[0\]
-mem_din_a0\[1\]
-mem_din_a0\[2\]
-mem_din_a0\[3\]
-mem_din_a0\[4\]
-mem_din_a0\[5\]
-mem_din_a0\[6\]
-mem_din_a0\[7\]
-mem_din_a0\[8\]
-mem_din_a0\[9\]
-mem_din_a0\[10\]
-mem_din_a0\[11\]
-mem_din_a0\[12\]
-mem_din_a0\[13\]
-mem_din_a0\[14\]
-mem_din_a0\[15\]
-mem_din_a0\[16\]
-mem_din_a0\[17\]
-mem_din_a0\[18\]
-mem_din_a0\[19\]
-mem_din_a0\[20\]
-mem_din_a0\[21\]
-mem_din_a0\[22\]
-mem_din_a0\[23\]
-mem_din_a0\[24\]
-mem_din_a0\[25\]
-mem_din_a0\[26\]
-mem_din_a0\[27\]
-mem_din_a0\[28\]
-mem_din_a0\[29\]
-mem_din_a0\[30\]
-mem_din_a0\[31\]
-
-
-mem_dout_a0\[0\]  350 0 2
-mem_dout_a0\[1\]
-mem_dout_a0\[2\]
-mem_dout_a0\[3\]
-mem_dout_a0\[4\]
-mem_dout_a0\[5\]
-mem_dout_a0\[6\]
-mem_dout_a0\[7\]
-mem_dout_a0\[8\]
-mem_dout_a0\[9\]
-mem_dout_a0\[10\]
-mem_dout_a0\[11\]
-mem_dout_a0\[12\]
-mem_dout_a0\[13\]
-mem_dout_a0\[14\]
-mem_dout_a0\[15\]
-mem_dout_a0\[16\]
-mem_dout_a0\[17\]
-mem_dout_a0\[18\]
-mem_dout_a0\[19\]
-mem_dout_a0\[20\]
-mem_dout_a0\[21\]
-mem_dout_a0\[22\]
-mem_dout_a0\[23\]
-mem_dout_a0\[24\]
-mem_dout_a0\[25\]
-mem_dout_a0\[26\]
-mem_dout_a0\[27\]
-mem_dout_a0\[28\]
-mem_dout_a0\[29\]
-mem_dout_a0\[30\]
-mem_dout_a0\[31\]
-
-
-mem_clk_b\[0\]    0450 0 2
-mem_cen_b\[0\]
-mem_addr_b0\[8\]
-mem_addr_b0\[7\]
-mem_addr_b0\[6\]
-mem_addr_b0\[5\]
-mem_addr_b0\[4\]
-mem_addr_b0\[3\]
-mem_addr_b0\[2\]
-mem_addr_b0\[1\]
-mem_addr_b0\[0\]
-
-
-mem_clk_a\[1\]       1000 0 2
-mem_cen_a\[1\]
-mem_web_a\[1\]
-mem_addr_a1\[0\]
-mem_addr_a1\[1\]
-mem_addr_a1\[2\]
-mem_addr_a1\[3\]
-mem_addr_a1\[4\]
-mem_addr_a1\[5\]
-mem_addr_a1\[6\]
-mem_addr_a1\[7\]
-mem_addr_a1\[8\]
-mem_mask_a1\[0\]
-mem_mask_a1\[1\]
-mem_mask_a1\[2\]
-mem_mask_a1\[3\]
-mem_din_a1\[0\]
-mem_din_a1\[1\]
-mem_din_a1\[2\]
-mem_din_a1\[3\]
-mem_din_a1\[4\]
-mem_din_a1\[5\]
-mem_din_a1\[6\]
-mem_din_a1\[7\]
-mem_din_a1\[8\]
-mem_din_a1\[9\]
-mem_din_a1\[10\]
-mem_din_a1\[11\]
-mem_din_a1\[12\]
-mem_din_a1\[13\]
-mem_din_a1\[14\]
-mem_din_a1\[15\]
-mem_din_a1\[16\]
-mem_din_a1\[17\]
-mem_din_a1\[18\]
-mem_din_a1\[19\]
-mem_din_a1\[20\]
-mem_din_a1\[21\]
-mem_din_a1\[22\]
-mem_din_a1\[23\]
-mem_din_a1\[24\]
-mem_din_a1\[25\]
-mem_din_a1\[26\]
-mem_din_a1\[27\]
-mem_din_a1\[28\]
-mem_din_a1\[29\]
-mem_din_a1\[30\]
-mem_din_a1\[31\]
-
-
-mem_dout_a1\[0\]  1100 0 2
-mem_dout_a1\[1\]
-mem_dout_a1\[2\]
-mem_dout_a1\[3\]
-mem_dout_a1\[4\]
-mem_dout_a1\[5\]
-mem_dout_a1\[6\]
-mem_dout_a1\[7\]
-mem_dout_a1\[8\]
-mem_dout_a1\[9\]
-mem_dout_a1\[10\]
-mem_dout_a1\[11\]
-mem_dout_a1\[12\]
-mem_dout_a1\[13\]
-mem_dout_a1\[14\]
-mem_dout_a1\[15\]
-mem_dout_a1\[16\]
-mem_dout_a1\[17\]
-mem_dout_a1\[18\]
-mem_dout_a1\[19\]
-mem_dout_a1\[20\]
-mem_dout_a1\[21\]
-mem_dout_a1\[22\]
-mem_dout_a1\[23\]
-mem_dout_a1\[24\]
-mem_dout_a1\[25\]
-mem_dout_a1\[26\]
-mem_dout_a1\[27\]
-mem_dout_a1\[28\]
-mem_dout_a1\[29\]
-mem_dout_a1\[30\]
-mem_dout_a1\[31\]
-
-
-mem_clk_b\[1\]    1200 0 2
-mem_cen_b\[1\]
-mem_addr_b1\[8\]
-mem_addr_b1\[7\]
-mem_addr_b1\[6\]
-mem_addr_b1\[5\]
-mem_addr_b1\[4\]
-mem_addr_b1\[3\]
-mem_addr_b1\[2\]
-mem_addr_b1\[1\]
-mem_addr_b1\[0\]
-
-
-#N
-mem_clk_a\[2\]       250 0 2
-mem_cen_a\[2\]
-mem_web_a\[2\]
-mem_addr_a2\[0\]
-mem_addr_a2\[1\]
-mem_addr_a2\[2\]
-mem_addr_a2\[3\]
-mem_addr_a2\[4\]
-mem_addr_a2\[5\]
-mem_addr_a2\[6\]
-mem_addr_a2\[7\]
-mem_addr_a2\[8\]
-mem_mask_a2\[0\]
-mem_mask_a2\[1\]
-mem_mask_a2\[2\]
-mem_mask_a2\[3\]
-mem_din_a2\[0\]
-mem_din_a2\[1\]
-mem_din_a2\[2\]
-mem_din_a2\[3\]
-mem_din_a2\[4\]
-mem_din_a2\[5\]
-mem_din_a2\[6\]
-mem_din_a2\[7\]
-mem_din_a2\[8\]
-mem_din_a2\[9\]
-mem_din_a2\[10\]
-mem_din_a2\[11\]
-mem_din_a2\[12\]
-mem_din_a2\[13\]
-mem_din_a2\[14\]
-mem_din_a2\[15\]
-mem_din_a2\[16\]
-mem_din_a2\[17\]
-mem_din_a2\[18\]
-mem_din_a2\[19\]
-mem_din_a2\[20\]
-mem_din_a2\[21\]
-mem_din_a2\[22\]
-mem_din_a2\[23\]
-mem_din_a2\[24\]
-mem_din_a2\[25\]
-mem_din_a2\[26\]
-mem_din_a2\[27\]
-mem_din_a2\[28\]
-mem_din_a2\[29\]
-mem_din_a2\[30\]
-mem_din_a2\[31\]
-
-
-mem_dout_a2\[0\]  0350 0 2
-mem_dout_a2\[1\]
-mem_dout_a2\[2\]
-mem_dout_a2\[3\]
-mem_dout_a2\[4\]
-mem_dout_a2\[5\]
-mem_dout_a2\[6\]
-mem_dout_a2\[7\]
-mem_dout_a2\[8\]
-mem_dout_a2\[9\]
-mem_dout_a2\[10\]
-mem_dout_a2\[11\]
-mem_dout_a2\[12\]
-mem_dout_a2\[13\]
-mem_dout_a2\[14\]
-mem_dout_a2\[15\]
-mem_dout_a2\[16\]
-mem_dout_a2\[17\]
-mem_dout_a2\[18\]
-mem_dout_a2\[19\]
-mem_dout_a2\[20\]
-mem_dout_a2\[21\]
-mem_dout_a2\[22\]
-mem_dout_a2\[23\]
-mem_dout_a2\[24\]
-mem_dout_a2\[25\]
-mem_dout_a2\[26\]
-mem_dout_a2\[27\]
-mem_dout_a2\[28\]
-mem_dout_a2\[29\]
-mem_dout_a2\[30\]
-mem_dout_a2\[31\]
-
-
-mem_clk_b\[2\]    0450 0 2
-mem_cen_b\[2\]
-mem_addr_b2\[8\]
-mem_addr_b2\[7\]
-mem_addr_b2\[6\]
-mem_addr_b2\[5\]
-mem_addr_b2\[4\]
-mem_addr_b2\[3\]
-mem_addr_b2\[2\]
-mem_addr_b2\[1\]
-mem_addr_b2\[0\]
-
-
-mem_clk_a\[3\]       1000 0 2
-mem_cen_a\[3\]
-mem_web_a\[3\]
-mem_addr_a3\[0\]
-mem_addr_a3\[1\]
-mem_addr_a3\[2\]
-mem_addr_a3\[3\]
-mem_addr_a3\[4\]
-mem_addr_a3\[5\]
-mem_addr_a3\[6\]
-mem_addr_a3\[7\]
-mem_addr_a3\[8\]
-mem_mask_a3\[0\]
-mem_mask_a3\[1\]
-mem_mask_a3\[2\]
-mem_mask_a3\[3\]
-mem_din_a3\[0\]
-mem_din_a3\[1\]
-mem_din_a3\[2\]
-mem_din_a3\[3\]
-mem_din_a3\[4\]
-mem_din_a3\[5\]
-mem_din_a3\[6\]
-mem_din_a3\[7\]
-mem_din_a3\[8\]
-mem_din_a3\[9\]
-mem_din_a3\[10\]
-mem_din_a3\[11\]
-mem_din_a3\[12\]
-mem_din_a3\[13\]
-mem_din_a3\[14\]
-mem_din_a3\[15\]
-mem_din_a3\[16\]
-mem_din_a3\[17\]
-mem_din_a3\[18\]
-mem_din_a3\[19\]
-mem_din_a3\[20\]
-mem_din_a3\[21\]
-mem_din_a3\[22\]
-mem_din_a3\[23\]
-mem_din_a3\[24\]
-mem_din_a3\[25\]
-mem_din_a3\[26\]
-mem_din_a3\[27\]
-mem_din_a3\[28\]
-mem_din_a3\[29\]
-mem_din_a3\[30\]
-mem_din_a3\[31\]
-
-
-mem_dout_a3\[0\]  1100 0 2
-mem_dout_a3\[1\]
-mem_dout_a3\[2\]
-mem_dout_a3\[3\]
-mem_dout_a3\[4\]
-mem_dout_a3\[5\]
-mem_dout_a3\[6\]
-mem_dout_a3\[7\]
-mem_dout_a3\[8\]
-mem_dout_a3\[9\]
-mem_dout_a3\[10\]
-mem_dout_a3\[11\]
-mem_dout_a3\[12\]
-mem_dout_a3\[13\]
-mem_dout_a3\[14\]
-mem_dout_a3\[15\]
-mem_dout_a3\[16\]
-mem_dout_a3\[17\]
-mem_dout_a3\[18\]
-mem_dout_a3\[19\]
-mem_dout_a3\[20\]
-mem_dout_a3\[21\]
-mem_dout_a3\[22\]
-mem_dout_a3\[23\]
-mem_dout_a3\[24\]
-mem_dout_a3\[25\]
-mem_dout_a3\[26\]
-mem_dout_a3\[27\]
-mem_dout_a3\[28\]
-mem_dout_a3\[29\]
-mem_dout_a3\[30\]
-mem_dout_a3\[31\]
-
-
-mem_clk_b\[3\]    1200 0 2
-mem_cen_b\[3\]
-mem_addr_b3\[8\]
-mem_addr_b3\[7\]
-mem_addr_b3\[6\]
-mem_addr_b3\[5\]
-mem_addr_b3\[4\]
-mem_addr_b3\[3\]
-mem_addr_b3\[2\]
-mem_addr_b3\[1\]
-mem_addr_b3\[0\]
-
diff --git a/openlane/mbist/sta.tcl b/openlane/mbist/sta.tcl
deleted file mode 100644
index 57a6c35..0000000
--- a/openlane/mbist/sta.tcl
+++ /dev/null
@@ -1,88 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-
-set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
-set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
-set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
-set ::env(DESIGN_NAME) "mbist_top"
-set ::env(BASE_SDC_FILE) "base.sdc"
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
-set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-set ::env(SYNTH_CAP_LOAD) "17.65"
-set ::env(WIRE_RC_LAYER) "met1"
-
-#To disable empty filler cell black box get created
-#set link_make_black_boxes 0
-
-
-set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
-define_corners wc bc tt
-read_liberty -corner bc $::env(LIB_FASTEST)
-read_liberty -corner wc $::env(LIB_SLOWEST)
-read_liberty -corner tt $::env(LIB_TYPICAL)
-
-
-read_verilog ../user_project_wrapper/netlist/mbist.v
-link_design  $::env(DESIGN_NAME)
-
-
-read_spef ../../spef/mbist_top.spef  
-
-
-read_sdc -echo $::env(BASE_SDC_FILE)
-
-# check for missing constraints
-check_setup  -verbose > unconstraints.rpt
-
-set_operating_conditions -analysis_type single
-# Propgate the clock
-set_propagated_clock [all_clocks]
-
-report_tns
-report_wns
-#report_power 
-echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_ss_max.rpt
-report_checks -unique -path_delay max -slack_max -0.0 -group_count 100 -corner wc >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group bist_clk  -corner wc  >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group mem_clk_a  -corner wc  >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group mem_clk_b -corner wc  >> timing_ss_max.rpt
-report_checks -path_delay max   -corner wc >> timing_ss_max.rpt
-
-echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_ff_min.rpt
-report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner bc >> timing_ff_min.rpt
-report_checks -group_count 100  -path_delay min -path_group bist_clk  -corner bc  >> timing_ff_min.rpt
-report_checks -group_count 100  -path_delay min -path_group mem_clk_a  -corner bc  >> timing_ff_min.rpt
-report_checks -group_count 100  -path_delay min -path_group mem_clk_b -corner bc  >> timing_ff_min.rpt
-report_checks -path_delay min  -corner bc >> timing_ff_min.rpt
-
-echo "################ CORNER : TT (MAX) TIMING Report ###################" > timing_tt_max.rpt
-report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_max.rpt
-report_checks -group_count 100  -path_delay max -path_group bist_clk  -corner tt  >> timing_tt_max.rpt
-report_checks -group_count 100  -path_delay max -path_group mem_clk_a  -corner tt  >> timing_tt_max.rpt
-report_checks -group_count 100  -path_delay max -path_group mem_clk_b -corner tt  >> timing_tt_max.rpt
-report_checks -path_delay min  -corner tt >> timing_tt_min.rpt
-
-echo "################ CORNER : TT (MIN) TIMING Report ###################" > timing_tt_min.rpt
-report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_min.rpt
-report_checks -group_count 100  -path_delay min -path_group bist_clk  -corner tt  >> timing_tt_min.rpt
-report_checks -group_count 100  -path_delay min -path_group mem_clk_a -corner tt  >> timing_tt_min.rpt
-report_checks -group_count 100  -path_delay min -path_group mem_clk_b -corner tt  >> timing_tt_min.rpt
-report_checks -path_delay min  -corner tt >> timing_tt_min.rpt
-
-report_checks -path_delay min
-
-#exit
diff --git a/openlane/mbist1/base.sdc b/openlane/mbist1/base.sdc
deleted file mode 100644
index 8ae25b1..0000000
--- a/openlane/mbist1/base.sdc
+++ /dev/null
@@ -1,163 +0,0 @@
-###############################################################################
-# Created by write_sdc
-# Sun Nov 14 09:33:23 2021
-###############################################################################
-current_design mbist_top
-###############################################################################
-# Timing Constraints
-###############################################################################
-create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}]
-create_generated_clock -name bist_mem_clk_a -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks wb_clk_i] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a]
-create_generated_clock -name bist_mem_clk_b -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks wb_clk_i] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b]
-
-set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks {wb_clk_i bist_mem_clk_a bist_mem_clk_b}]  
-
-set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
-set_clock_uncertainty -setup 0.2500 wb_clk_i
-set_clock_uncertainty -setup 0.2500 mem_clk_a
-set_clock_uncertainty -setup 0.2500 mem_clk_b
-
-set_clock_uncertainty -hold 0.2500 wb_clk_i
-set_clock_uncertainty -hold 0.2500 mem_clk_a
-set_clock_uncertainty -hold 0.2500 mem_clk_b
-
-set ::env(SYNTH_TIMING_DERATE) 0.05
-puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
-set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
-set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
-
-set_input_delay  -max 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}]
-set_input_delay  -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}]
-
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}]
-
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}]
-
-set_false_path -from [get_ports {bist_en}]
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}]
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}]
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}]
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}]
-
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_en}]
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}]
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}]
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}]
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}]
-
-## Functional Inputs
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_adr_i[*]}]  
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_stb_i}]      
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_cyc_i}]      
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_we_i}]      
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wbd_mbist1_dat_o[*]}] 
-set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_sel_i[*]}]
-
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_adr_i[*]}]  
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_stb_i}]      
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_cyc_i}]      
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_we_i}]      
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wbd_mbist1_dat_o[*]}] 
-set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_sel_i[*]}]
-
-set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_dat_o[*]}]  
-set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_ack_o}]  
-set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_err_o}]  
-
-set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_dat_o[*]}]  
-set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_ack_o}]  
-set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_err_o}]  
-
-## Towards MEMORY from MBIST CLOCK
-## PORT-A
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}]
-
-
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
-
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
-
-
-
-## PORT-B
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}]
-
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}]
-
-
-# Set max delay for clock skew
-
-set_max_delay   3.5 -from [get_ports {wbd_clk_int}]
-set_max_delay   2 -to   [get_ports {wbd_clk_mbist}]
-set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_mbist
-
-###############################################################################
-# Environment
-###############################################################################
-set_load -pin_load 0.0334 [get_ports {bist_correct}]
-set_load -pin_load 0.0334 [get_ports {bist_done}]
-set_load -pin_load 0.0334 [get_ports {bist_error}]
-set_load -pin_load 0.0334 [get_ports {bist_sdo}]
-set_load -pin_load 0.0334 [get_ports {mem_cen_a}]
-set_load -pin_load 0.0334 [get_ports {mem_cen_b}]
-set_load -pin_load 0.0334 [get_ports {mem_clk_a}]
-set_load -pin_load 0.0334 [get_ports {mem_clk_b}]
-set_load -pin_load 0.0334 [get_ports {mem_web_b}]
-set_load -pin_load 0.0334 [get_ports {bist_error_cnt[3]}]
-set_load -pin_load 0.0334 [get_ports {bist_error_cnt[2]}]
-set_load -pin_load 0.0334 [get_ports {bist_error_cnt[1]}]
-set_load -pin_load 0.0334 [get_ports {bist_error_cnt[0]}]
-set_load -pin_load 0.0334 [get_ports {wb_cyc_i}]
-set_load -pin_load 0.0334 [get_ports {wb_stb_i}]
-set_load -pin_load 0.0334 [get_ports {wb_adr_i[*]}]
-set_load -pin_load 0.0334 [get_ports {wb_we_i}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_i[*]}]
-set_load -pin_load 0.0334 [get_ports {wb_sel_i[*]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_a[*]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_b[*]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[*]}]
-set_load -pin_load 0.0334 [get_ports {mem_mask_b[*]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_en}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_load}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_run}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdi}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_shift}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[*]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_we_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[*]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[*]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[*]}]
-set_timing_derate -early 0.9500
-set_timing_derate -late 1.0500
-###############################################################################
-# Design Rules
-###############################################################################
-set_max_fanout 4.0000 [current_design]
diff --git a/openlane/mbist1/config.tcl b/openlane/mbist1/config.tcl
deleted file mode 100755
index 1876487..0000000
--- a/openlane/mbist1/config.tcl
+++ /dev/null
@@ -1,113 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-# Global
-# ------
-
-set script_dir [file dirname [file normalize [info script]]]
-# Name
-
-set ::env(DESIGN_NAME) mbist_top1
-
-set ::env(DESIGN_IS_CORE) "0"
-
-# Timing configuration
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "u_cts_wb_clk_b1.u_buf/X  u_cts_wb_clk_b2.u_buf/X u_mem_sel.u_cts_mem_clk_a.u_buf/X u_mem_sel.u_cts_mem_clk_b.u_buf/X"
-
-set ::env(SYNTH_MAX_FANOUT) 4
-
-# Sources
-# -------
-
-# Local sources + no2usb sources
-set ::env(VERILOG_FILES) "\
-     $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_addr_gen.sv \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_fsm.sv     \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_op_sel.sv  \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_repair_addr.sv \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_sti_sel.sv \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_pat_sel.sv \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_mux.sv \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_data_cmp.sv \
-     $script_dir/../../verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv \
-     $script_dir/../../verilog/rtl/mbist/src/top/mbist_top1.sv  \
-     $script_dir/../../verilog/rtl/lib/ctech_cells.sv     \
-     $script_dir/../../verilog/rtl/lib/reset_sync.sv \
-	     "
-
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/mbist/include ]
-set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-
-
-set ::env(SYNTH_PARAMS) "BIST_ADDR_WD 9,\
-	                 BIST_DATA_WD 32,\
-		         BIST_ADDR_START 9'h000,\
-			 BIST_ADDR_END 9'h1FB,\
-			 BIST_REPAIR_ADDR_START 9'h1FC,\
-			 BIST_RAD_WD_I 9,\
-			 BIST_RAD_WD_O 9\
-			 "
-
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
-
-set ::env(LEC_ENABLE) 0
-
-set ::env(VDD_PIN) [list {vccd1}]
-set ::env(GND_PIN) [list {vssd1}]
-
-
-# Floorplanning
-# -------------
-
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 200 275"
-
-
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 1
-
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
-
-
-set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.35"
-
-
-
-set ::env(FP_IO_VEXTEND) 4
-set ::env(FP_IO_HEXTEND) 4
-
-set ::env(FP_PDN_VPITCH) 100
-set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 5
-set ::env(FP_PDN_HWIDTH) 5
-
-set ::env(GLB_RT_MAXLAYER) 5
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-
-set ::env(DIODE_INSERTION_STRATEGY) 4
-
-
-set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
-set ::env(QUIT_ON_MAGIC_DRC) "1"
-set ::env(QUIT_ON_LVS_ERROR) "0"
-set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/mbist1/interactive.tcl b/openlane/mbist1/interactive.tcl
deleted file mode 100644
index f59586f..0000000
--- a/openlane/mbist1/interactive.tcl
+++ /dev/null
@@ -1,219 +0,0 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-package require openlane;
-
-
-proc run_placement_step {args} {
-    # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
-    # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
-    # set_def $pdndef
-    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
-        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
-    }
-
-    run_placement
-}
-
-proc run_cts_step {args} {
-    # set_def $::env(opendp_result_file_tag).def
-    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
-        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
-    }
-
-    run_cts
-    run_resizer_timing
-}
-
-proc run_routing_step {args} {
-    # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
-    # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
-    # set_def $resizerdef
-    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
-        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
-    }
-    run_routing
-}
-
-proc run_diode_insertion_2_5_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
-        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
-    }
-	if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
-		run_antenna_check
-		heal_antenna_violators; # modifies the routed DEF
-	}
-
-}
-
-proc run_power_pins_insertion_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
-        set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
-    }
-    if { $::env(LVS_INSERT_POWER_PINS) } {
-		write_powered_verilog
-		set_netlist $::env(lvs_result_file_tag).powered.v
-    }
-
-}
-
-proc run_lvs_step {{ lvs_enabled 1 }} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
-        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
-    }
-	if { $lvs_enabled } {
-		run_magic_spice_export
-		run_lvs; # requires run_magic_spice_export
-	}
-
-}
-
-proc run_drc_step {{ drc_enabled 1 }} {
-    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
-        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
-    }
-	if { $drc_enabled } {
-		run_magic_drc
-		run_klayout_drc
-	}
-}
-
-proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
-    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
-        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
-    }
-	if { $antenna_check_enabled } {
-		run_antenna_check
-	}
-}
-
-proc run_flow {args} {
-       set script_dir [file dirname [file normalize [info script]]]
-
-		set options {
-		{-design required}
-		{-save_path optional}
-		{-no_lvs optional}
-	    {-no_drc optional}
-	    {-no_antennacheck optional}
-	}
-	set flags {-save}
-	parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
-
-	prep {*}$args
-
-        set LVS_ENABLED 1
-        set DRC_ENABLED 1
-        set ANTENNACHECK_ENABLED 1
-
-        set steps [dict create "synthesis" {run_synthesis "" } \
-                "floorplan" {run_floorplan ""} \
-                "placement" {run_placement_step ""} \
-                "cts" {run_cts_step ""} \
-                "routing" {run_routing_step ""}\
-                "diode_insertion" {run_diode_insertion_2_5_step ""} \
-                "power_pins_insertion" {run_power_pins_insertion_step ""} \
-                "gds_magic" {run_magic ""} \
-                "gds_drc_klayout" {run_klayout ""} \
-                "gds_xor_klayout" {run_klayout_gds_xor ""} \
-                "lvs" "run_lvs_step $LVS_ENABLED" \
-                "drc" "run_drc_step $DRC_ENABLED" \
-                "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
-                "cvc" {run_lef_cvc}
-        ]
-
-       set_if_unset arg_values(-to) "cvc";
-
-       if {  [info exists ::env(CURRENT_STEP) ] } {
-           puts "\[INFO\]:Picking up where last execution left off"
-           puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
-       } else {
-           set ::env(CURRENT_STEP) "synthesis";
-       }
-       set_if_unset arg_values(-from) $::env(CURRENT_STEP);
-       set exe 0;
-       dict for {step_name step_exe} $steps {
-           if { [ string equal $arg_values(-from) $step_name ] } {
-               set exe 1;
-           }
-
-           if { $exe } {
-               # For when it fails
-               set ::env(CURRENT_STEP) $step_name
-               [lindex $step_exe 0] [lindex $step_exe 1] ;
-           }
-
-           if { [ string equal $arg_values(-to) $step_name ] } {
-               set exe 0:
-               break;
-           }
-
-       }
-
-       # for when it resumes
-       set steps_as_list [dict keys $steps]
-       set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
-       set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
-
-	if {  [info exists flags_map(-save) ] } {
-		if { ! [info exists arg_values(-save_path)] } {
-			set arg_values(-save_path) ""
-		}
-		save_views 	-lef_path $::env(magic_result_file_tag).lef \
-			-def_path $::env(CURRENT_DEF) \
-			-gds_path $::env(magic_result_file_tag).gds \
-			-mag_path $::env(magic_result_file_tag).mag \
-			-maglef_path $::env(magic_result_file_tag).lef.mag \
-			-spice_path $::env(magic_result_file_tag).spice \
-			-spef_path $::env(CURRENT_SPEF) \
-			-verilog_path $::env(CURRENT_NETLIST) \
-			-save_path $arg_values(-save_path) \
-			-tag $::env(RUN_TAG)
-	}
-
-
-	calc_total_runtime
-	save_state
-	generate_final_summary_report
-	
-	check_timing_violations
-
-	puts_success "Flow Completed Without Fatal Errors."
-
-}
-
-run_flow {*}$argv
diff --git a/openlane/mbist1/pin_order.cfg b/openlane/mbist1/pin_order.cfg
deleted file mode 100644
index 82dd636..0000000
--- a/openlane/mbist1/pin_order.cfg
+++ /dev/null
@@ -1,213 +0,0 @@
-#BUS_SORT
-
-#MANUAL_PLACE
-
-
-#S
-rst_n            0000 0        
-
-
-
-#E
-cfg_cska_mbist\[3\]  0000 0 4
-cfg_cska_mbist\[2\]
-cfg_cska_mbist\[1\]
-cfg_cska_mbist\[0\]
-wb_clk_i         
-wbd_clk_mbist
-wbd_clk_int         
-
-wb_cyc_i            0025 0 2
-wb_stb_i
-wb_we_i
-wb_adr_i\[8\]
-wb_adr_i\[7\]
-wb_adr_i\[6\]
-wb_adr_i\[5\]
-wb_adr_i\[4\]
-wb_adr_i\[3\]
-wb_adr_i\[2\]
-wb_adr_i\[1\]
-wb_adr_i\[0\]
-wb_dat_i\[31\]
-wb_dat_i\[30\]
-wb_dat_i\[29\]
-wb_dat_i\[28\]
-wb_dat_i\[27\]
-wb_dat_i\[26\]
-wb_dat_i\[25\]
-wb_dat_i\[24\]
-wb_dat_i\[23\]
-wb_dat_i\[22\]
-wb_dat_i\[21\]
-wb_dat_i\[20\]
-wb_dat_i\[19\]
-wb_dat_i\[18\]
-wb_dat_i\[17\]
-wb_dat_i\[16\]
-wb_dat_i\[15\]
-wb_dat_i\[14\]
-wb_dat_i\[13\]
-wb_dat_i\[12\]
-wb_dat_i\[11\]
-wb_dat_i\[10\]
-wb_dat_i\[9\]
-wb_dat_i\[8\]
-wb_dat_i\[7\]
-wb_dat_i\[6\]
-wb_dat_i\[5\]
-wb_dat_i\[4\]
-wb_dat_i\[3\]
-wb_dat_i\[2\]
-wb_dat_i\[1\]
-wb_dat_i\[0\]
-wb_sel_i\[3\]
-wb_sel_i\[2\]
-wb_sel_i\[1\]
-wb_sel_i\[0\]
-wb_dat_o\[31\]
-wb_dat_o\[30\]
-wb_dat_o\[29\]
-wb_dat_o\[28\]
-wb_dat_o\[27\]
-wb_dat_o\[26\]
-wb_dat_o\[25\]
-wb_dat_o\[24\]
-wb_dat_o\[23\]
-wb_dat_o\[22\]
-wb_dat_o\[21\]
-wb_dat_o\[20\]
-wb_dat_o\[19\]
-wb_dat_o\[18\]
-wb_dat_o\[17\]
-wb_dat_o\[16\]
-wb_dat_o\[15\]
-wb_dat_o\[14\]
-wb_dat_o\[13\]
-wb_dat_o\[12\]
-wb_dat_o\[11\]
-wb_dat_o\[10\]
-wb_dat_o\[9\]
-wb_dat_o\[8\]
-wb_dat_o\[7\]
-wb_dat_o\[6\]
-wb_dat_o\[5\]
-wb_dat_o\[4\]
-wb_dat_o\[3\]
-wb_dat_o\[2\]
-wb_dat_o\[1\]
-wb_dat_o\[0\]
-wb_ack_o
-wb_err_o
-
-
-bist_error_cnt\[3\] 0150 0 2
-bist_error_cnt\[2\]
-bist_error_cnt\[1\]
-bist_error_cnt\[0\]
-bist_correct
-bist_error
-bist_done
-bist_sdo
-bist_shift
-bist_sdi
-bist_load
-bist_run
-bist_en           
-
-#W
-mem_clk_b       0000 0 2
-mem_cen_b
-mem_web_b
-mem_mask_b\[0\]
-mem_mask_b\[1\]
-mem_mask_b\[2\]
-mem_mask_b\[3\]
-mem_addr_b\[0\]
-mem_addr_b\[1\]
-mem_addr_b\[2\]
-mem_addr_b\[3\]
-mem_addr_b\[4\]
-mem_addr_b\[5\]
-mem_addr_b\[6\]
-mem_addr_b\[7\]
-mem_addr_b\[8\]
-mem_din_b\[0\]
-mem_din_b\[1\]
-mem_din_b\[2\]
-mem_din_b\[3\]
-mem_din_b\[4\]
-mem_din_b\[5\]
-mem_din_b\[6\]
-mem_din_b\[7\]
-mem_din_b\[8\]
-mem_din_b\[9\]
-mem_din_b\[10\]
-mem_din_b\[11\]
-mem_din_b\[12\]
-mem_din_b\[13\]
-mem_din_b\[14\]
-mem_din_b\[15\]
-mem_din_b\[16\]
-mem_din_b\[17\]
-mem_din_b\[18\]
-mem_din_b\[19\]
-mem_din_b\[20\]
-mem_din_b\[21\]
-mem_din_b\[22\]
-mem_din_b\[23\]
-mem_din_b\[24\]
-mem_din_b\[25\]
-mem_din_b\[26\]
-mem_din_b\[27\]
-mem_din_b\[28\]
-mem_din_b\[29\]
-mem_din_b\[30\]
-mem_din_b\[31\]
-
-
-mem_dout_a\[0\]  0100 0 2
-mem_dout_a\[1\]
-mem_dout_a\[2\]
-mem_dout_a\[3\]
-mem_dout_a\[4\]
-mem_dout_a\[5\]
-mem_dout_a\[6\]
-mem_dout_a\[7\]
-mem_dout_a\[8\]
-mem_dout_a\[9\]
-mem_dout_a\[10\]
-mem_dout_a\[11\]
-mem_dout_a\[12\]
-mem_dout_a\[13\]
-mem_dout_a\[14\]
-mem_dout_a\[15\]
-mem_dout_a\[16\]
-mem_dout_a\[17\]
-mem_dout_a\[18\]
-mem_dout_a\[19\]
-mem_dout_a\[20\]
-mem_dout_a\[21\]
-mem_dout_a\[22\]
-mem_dout_a\[23\]
-mem_dout_a\[24\]
-mem_dout_a\[25\]
-mem_dout_a\[26\]
-mem_dout_a\[27\]
-mem_dout_a\[28\]
-mem_dout_a\[29\]
-mem_dout_a\[30\]
-mem_dout_a\[31\]
-
-
-mem_clk_a          0200 0 2
-mem_cen_a
-mem_addr_a\[8\]
-mem_addr_a\[7\]
-mem_addr_a\[6\]
-mem_addr_a\[5\]
-mem_addr_a\[4\]
-mem_addr_a\[3\]
-mem_addr_a\[2\]
-mem_addr_a\[1\]
-mem_addr_a\[0\]
diff --git a/openlane/mbist1/sta.tcl b/openlane/mbist1/sta.tcl
deleted file mode 100644
index 57a6c35..0000000
--- a/openlane/mbist1/sta.tcl
+++ /dev/null
@@ -1,88 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-
-set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
-set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
-set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
-set ::env(DESIGN_NAME) "mbist_top"
-set ::env(BASE_SDC_FILE) "base.sdc"
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
-set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-set ::env(SYNTH_CAP_LOAD) "17.65"
-set ::env(WIRE_RC_LAYER) "met1"
-
-#To disable empty filler cell black box get created
-#set link_make_black_boxes 0
-
-
-set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
-define_corners wc bc tt
-read_liberty -corner bc $::env(LIB_FASTEST)
-read_liberty -corner wc $::env(LIB_SLOWEST)
-read_liberty -corner tt $::env(LIB_TYPICAL)
-
-
-read_verilog ../user_project_wrapper/netlist/mbist.v
-link_design  $::env(DESIGN_NAME)
-
-
-read_spef ../../spef/mbist_top.spef  
-
-
-read_sdc -echo $::env(BASE_SDC_FILE)
-
-# check for missing constraints
-check_setup  -verbose > unconstraints.rpt
-
-set_operating_conditions -analysis_type single
-# Propgate the clock
-set_propagated_clock [all_clocks]
-
-report_tns
-report_wns
-#report_power 
-echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_ss_max.rpt
-report_checks -unique -path_delay max -slack_max -0.0 -group_count 100 -corner wc >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group bist_clk  -corner wc  >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group mem_clk_a  -corner wc  >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group mem_clk_b -corner wc  >> timing_ss_max.rpt
-report_checks -path_delay max   -corner wc >> timing_ss_max.rpt
-
-echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_ff_min.rpt
-report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner bc >> timing_ff_min.rpt
-report_checks -group_count 100  -path_delay min -path_group bist_clk  -corner bc  >> timing_ff_min.rpt
-report_checks -group_count 100  -path_delay min -path_group mem_clk_a  -corner bc  >> timing_ff_min.rpt
-report_checks -group_count 100  -path_delay min -path_group mem_clk_b -corner bc  >> timing_ff_min.rpt
-report_checks -path_delay min  -corner bc >> timing_ff_min.rpt
-
-echo "################ CORNER : TT (MAX) TIMING Report ###################" > timing_tt_max.rpt
-report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_max.rpt
-report_checks -group_count 100  -path_delay max -path_group bist_clk  -corner tt  >> timing_tt_max.rpt
-report_checks -group_count 100  -path_delay max -path_group mem_clk_a  -corner tt  >> timing_tt_max.rpt
-report_checks -group_count 100  -path_delay max -path_group mem_clk_b -corner tt  >> timing_tt_max.rpt
-report_checks -path_delay min  -corner tt >> timing_tt_min.rpt
-
-echo "################ CORNER : TT (MIN) TIMING Report ###################" > timing_tt_min.rpt
-report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_min.rpt
-report_checks -group_count 100  -path_delay min -path_group bist_clk  -corner tt  >> timing_tt_min.rpt
-report_checks -group_count 100  -path_delay min -path_group mem_clk_a -corner tt  >> timing_tt_min.rpt
-report_checks -group_count 100  -path_delay min -path_group mem_clk_b -corner tt  >> timing_tt_min.rpt
-report_checks -path_delay min  -corner tt >> timing_tt_min.rpt
-
-report_checks -path_delay min
-
-#exit
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl
index 68f6db6..7650732 100755
--- a/openlane/pinmux/config.tcl
+++ b/openlane/pinmux/config.tcl
@@ -97,7 +97,7 @@
 set ::env(FP_PDN_VWIDTH) 5
 set ::env(FP_PDN_HWIDTH) 5
 
-set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg
index 2ff62e6..b3273bf 100644
--- a/openlane/pinmux/pin_order.cfg
+++ b/openlane/pinmux/pin_order.cfg
@@ -91,6 +91,7 @@
 pinmux_debug\[29\]
 pinmux_debug\[30\]
 pinmux_debug\[31\]
+dbg_clk_mon
 
 #W
 
diff --git a/openlane/qspim_top/config.tcl b/openlane/qspim_top/config.tcl
index e2a3b24..f17f63d 100755
--- a/openlane/qspim_top/config.tcl
+++ b/openlane/qspim_top/config.tcl
@@ -93,7 +93,7 @@
 set ::env(FP_PDN_VWIDTH) 5
 set ::env(FP_PDN_HWIDTH) 5
 
-set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/uart_i2cm_usb_spi_top/base.sdc b/openlane/uart_i2cm_usb_spi_top/base.sdc
index 735b5fb..4a33fc5 100644
--- a/openlane/uart_i2cm_usb_spi_top/base.sdc
+++ b/openlane/uart_i2cm_usb_spi_top/base.sdc
@@ -7,8 +7,8 @@
 # Timing Constraints
 ###############################################################################
 create_clock -name app_clk -period 10.0000 [get_ports {app_clk}]
-create_clock -name uart0_baud_clk -period 100.0000 [get_pins {u_uart0_core.u_lineclk_buf.u_mux/X}]
-create_clock -name uart1_baud_clk -period 100.0000 [get_pins {u_uart1_core.u_lineclk_buf.u_mux/X}]
+create_clock -name uart0_baud_clk -period 100.0000 [get_pins {u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uart1_baud_clk -period 100.0000 [get_pins {u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}]
 create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}]
 
 set_clock_transition 0.1500 [all_clocks]
@@ -35,10 +35,13 @@
 set_max_delay 5 -from wbd_clk_int -to wbd_clk_uart
 
 
+set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {i2c_rstn}]
+set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {uart_rstn}]
+set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {usb_rstn}]
 
-set_input_delay 3.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {i2c_rstn}]
-set_input_delay 3.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {uart_rstn}]
-set_input_delay 3.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {usb_rstn}]
+set_input_delay -min 1.5000 -clock [get_clocks {app_clk}] -add_delay [get_ports {i2c_rstn}]
+set_input_delay -min 1.5000 -clock [get_clocks {app_clk}] -add_delay [get_ports {uart_rstn}]
+set_input_delay -min 1.5000 -clock [get_clocks {app_clk}] -add_delay [get_ports {usb_rstn}]
 
 
 set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_addr[*]}]
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl
index 2627452..a97080d 100644
--- a/openlane/uart_i2cm_usb_spi_top/config.tcl
+++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -27,7 +27,7 @@
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "app_clk usb_clk u_uart_core.u_lineclk_buf.u_mux/X"
+set ::env(CLOCK_PORT) "app_clk usb_clk u_uart0_core.u_lineclk_buf.genblk1.u_mux/X u_uart1_core.u_lineclk_buf.genblk1.u_mux/X"
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
@@ -72,6 +72,7 @@
     $script_dir/../../verilog/rtl/lib/ctech_cells.sv     \
     "
 
+set ::env(SYNTH_NO_FLAT) {1}
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/i2cm/src/includes $script_dir/../../verilog/rtl/usb1_host/src/includes ]
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -101,7 +102,7 @@
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.45"
+set ::env(PL_TARGET_DENSITY) "0.46"
 
 # helps in anteena fix
 set ::env(USE_ARC_ANTENNA_CHECK) "0"
@@ -114,7 +115,7 @@
 set ::env(FP_PDN_VWIDTH) 5
 set ::env(FP_PDN_HWIDTH) 5
 
-set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 4
@@ -122,6 +123,9 @@
 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
 
+set ::env(GLB_RT_ADJUSTMENT) {0.25}
+set ::env(CELL_PAD) {2}
+
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"
 set ::env(QUIT_ON_LVS_ERROR) "0"
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index c1e47ab..19757e8 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -16,6 +16,7 @@
 # Base Configurations. Don't Touch
 # section begin
 
+set ::env(PDK) "sky130A"
 set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
 
 # YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS 
@@ -43,8 +44,10 @@
 
 ## Source Verilog Files
 set ::env(VERILOG_FILES) "\
+	$proj_dir/../../verilog/rtl//yifive/ycr1c/src/top/ycr_top_wb.sv \
 	$proj_dir/../../verilog/rtl/user_project_wrapper.v"
 
+
 ## Clock configurations
 set ::env(CLOCK_PORT) "user_clock2 wb_clk_i"
 #set ::env(CLOCK_NET) "mprj.clk"
@@ -70,8 +73,11 @@
         $proj_dir/../../verilog/gl/pinmux.v     \
         $proj_dir/../../verilog/gl/uart_i2c_usb_spi_top.v     \
 	$proj_dir/../../verilog/gl/wb_host.v \
-	$proj_dir/../../verilog/gl/yifive.v \
-	$proj_dir/../../verilog/gl/DFFRAM.v \
+	$proj_dir/../../verilog/gl/ycr_intf.v \
+	$proj_dir/../../verilog/gl/ycr_core_top.v \
+	$proj_dir/../../verilog/gl/ycr_iconnect.v \
+	$proj_dir/../../verilog/gl/digital_pll.v \
+	$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
 	"
 
 set ::env(EXTRA_LEFS) "\
@@ -80,8 +86,11 @@
 	$lef_root/wb_interconnect.lef \
 	$lef_root/uart_i2c_usb_spi_top.lef \
 	$lef_root/wb_host.lef \
-	$lef_root/yifive.lef \
-	$lef_root/DFFRAM.lef \
+	$lef_root/ycr_intf.lef \
+	$lef_root/ycr_core_top.lef \
+	$lef_root/ycr_iconnect.lef \
+	$lef_root/digital_pll.lef \
+	$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
 	"
 
 set ::env(EXTRA_GDS_FILES) "\
@@ -90,15 +99,18 @@
 	$gds_root/wb_interconnect.gds \
 	$gds_root/uart_i2c_usb_spi_top.gds \
 	$gds_root/wb_host.gds \
-	$gds_root/yifive.gds \
-	$gds_root/DFFRAM.gds \
+	$gds_root/ycr_intf.gds \
+	$gds_root/ycr_core_top.gds \
+	$gds_root/ycr_iconnect.gds \
+	$gds_root/digital_pll.gds \
+	$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
 	"
 
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 
-#set ::env(VERILOG_INCLUDE_DIRS) [glob $proj_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $proj_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
 
-set ::env(GLB_RT_MAXLAYER) 6
+#set ::env(GLB_RT_MAXLAYER) 6
 set ::env(RT_MAX_LAYER) {met5}
 
 set ::env(FP_PDN_CHECK_NODES) 0
@@ -109,42 +121,52 @@
 set ::env(FP_PDN_ENABLE_MACROS_GRID) "1"
 set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
 
-set ::env(VDD_NETS) "vccd1 vccd2 vdda1 vdda2"
-set ::env(GND_NETS) "vssd1 vssd2 vssa1 vssa2"
+set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2}
+set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2}
 #
-set ::env(VDD_PIN) "vccd1"
-set ::env(GND_PIN) "vssd1"
+set ::env(VDD_PIN) {vccd1}
+set ::env(GND_PIN) {vssd1}
+
+set ::env(GLB_RT_OBS) "                              \
+	                li1   150 130  833.1  546.54,\
+	                met1  150 130  833.1  546.54,\
+	                met2  150 130  833.1  546.54,\
+                        met3  150 130  833.1  546.54,\
+
+	                li1   950 130  1633.1 546.54,\
+	                met1  950 130  1633.1 546.54,\
+	                met2  950 130  1633.1 546.54,\
+                        met3  950 130  1633.1 546.54,\
+
+                        li1   150  750 833.1  1166.54,\
+                        met1  150  750 833.1  1166.54,\
+                        met2  150  750 833.1  1166.54,\
+                        met3  150  750 833.1  1166.54,\
+	                met5  0 0 2920 3520"
+
 set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0"
 
-set ::env(GLB_RT_OBS) " met5  0    0    2920   3520, \
-	                met4  125  1750  675   2490, \
-	                met4  125  2645  675   3385, \
-	                met4  125  900   675   1640, \
-	                met4  800  110  1350    850, \
-	                met4  850  2645 1400   3385, \
-	                met4  1575 2645 2125   3385 \
-	              "
-                      
-
-#set ::env(FP_PDN_MACRO_HOOKS) " \
-#	u_intercon vccd1 vssd1 \
-#	u_pinmux vccd1 vssd1 \
-#	u_qspi_master vccd1 vssd1 \
-#	u_riscv_top vccd1 vssd1 \
-#	u_tsram0_2kb vccd1 vssd1 \
-#	u_icache_2kb vccd1 vssd1 \
-#	u_dcache_2kb vccd1 vssd1 \
-#	u_mbist vccd1 vssd1 \
-#	u_sram0_2kb vccd1 vssd1 \
-#	u_sram1_2kb vccd1 vssd1 \
-#	u_sram2_2kb vccd1 vssd1 \
-#	u_sram3_2kb vccd1 vssd1 \
-#	u_uart_i2c_usb_spi vccd1 vssd1 \
-#	u_wb_host vccd1 vssd1 "
+set ::env(FP_PDN_MACRO_HOOKS) " \
+	u_intercon vccd1 vssd1,\
+	u_pinmux vccd1 vssd1,\
+	u_qspi_master vccd1 vssd1,\
+	u_riscv_top vccd1 vssd1,\
+	u_tsram0_2kb vccd1 vssd1,\
+	u_icache_2kb vccd1 vssd1,\
+	u_dcache_2kb vccd1 vssd1,\
+	u_sram0_2kb vccd1 vssd1,\
+	u_sram1_2kb vccd1 vssd1,\
+	u_sram2_2kb vccd1 vssd1,\
+	u_sram3_2kb vccd1 vssd1,\
+	u_uart_i2c_usb_spi vccd1 vssd1,\
+	u_wb_host vccd1 vssd1,\
+	u_riscv_top.i_core_top_0 vccd1 vssd1, \
+	u_riscv_top.u_intf vccd1 vssd1 \
+       	"
 
 
 # The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_TOP_LEVEL) 1
+set ::env(SYNTH_TOP_LEVEL) 0
 set ::env(PL_RANDOM_GLB_PLACEMENT) 1
 
 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
@@ -160,8 +182,7 @@
 set ::env(CLOCK_TREE_SYNTH) 0
 
 set ::env(QUIT_ON_LVS_ERROR) "0"
-set ::env(QUIT_ON_TR_DRC) "1"
-set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_MAGIC_DRC) "0"
 set ::env(QUIT_ON_NEGATIVE_WNS) "0"
 set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
@@ -170,13 +191,26 @@
 set ::env(FP_PDN_HORIZONTAL_HALO) "10"
 set ::env(FP_PDN_VERTICAL_HALO) "10"
 
+#
+
+set ::env(FP_PDN_CORE_RING_HOFFSET) {12.45}
+set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_HWIDTH) {3.1}
+
+set ::env(FP_PDN_CORE_RING_VOFFSET) {12.45}
+set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_VWIDTH) {3.1}
+
+
 set ::env(FP_PDN_VOFFSET) "5"
 set ::env(FP_PDN_VPITCH) "80"
 set ::env(FP_PDN_VSPACING) "15.5"
 set ::env(FP_PDN_VWIDTH) "3.1"
 
-set ::env(FP_PDN_HOFFSET) "16.65"
-set ::env(FP_PDN_HPITCH) "130"
+set ::env(FP_PDN_HOFFSET) "10"
+set ::env(FP_PDN_HPITCH) "90"
+set ::env(FP_PDN_HSPACING) "10"
+set ::env(FP_PDN_HWIDTH) "3.1"
 
 
 
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index 2842c9f..07190b7 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -19,41 +19,53 @@
 package require openlane;
 
 proc run_placement_step {args} {
-    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
-        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
-    }
+	if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+		set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+	} else {
+		set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+	}
 
-    run_placement
+	run_placement
 }
 
 proc run_cts_step {args} {
-    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
-        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
-    }
+	if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+		set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+	} else {
+		set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+	}
 
-    run_cts
-    run_resizer_timing
+	run_cts
+	run_resizer_timing
 }
 
 proc run_routing_step {args} {
-    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
-        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
-    }
-    run_routing
+	if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+		set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+	} else {
+		set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+	}
+	run_routing
+}
+
+proc run_parasitics_sta_step {args} {
+	if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+		set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+	} else {
+		set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+	}
+
+	if { $::env(RUN_SPEF_EXTRACTION) } {
+		run_parasitics_sta
+	}
 }
 
 proc run_diode_insertion_2_5_step {args} {
-    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
-        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
-    }
+	if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+		set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+	} else {
+		set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+	}
 	if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
 		run_antenna_check
 		heal_antenna_violators; # modifies the routed DEF
@@ -62,36 +74,41 @@
 }
 
 proc run_lvs_step {{ lvs_enabled 1 }} {
-    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
-        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
-    }
-	if { $lvs_enabled } {
-		run_magic_spice_export
+	if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+		set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+	} else {
+		set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+	}
+
+	if { $lvs_enabled && $::env(RUN_LVS) } {
+		run_magic_spice_export;
 		run_lvs; # requires run_magic_spice_export
 	}
 
 }
 
 proc run_drc_step {{ drc_enabled 1 }} {
-    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
-        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
-    }
+	if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+		set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+	} else {
+		set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+	}
 	if { $drc_enabled } {
-		run_magic_drc
-		run_klayout_drc
+		if { $::env(RUN_MAGIC_DRC) } {
+			run_magic_drc
+		}
+		if {$::env(RUN_KLAYOUT_DRC)} {
+			run_klayout_drc
+		}
 	}
 }
 
 proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
-    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
-        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
-    }
+	if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+		set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+	} else {
+		set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+	}
 	if { $antenna_check_enabled } {
 		run_antenna_check
 	}
@@ -99,8 +116,23 @@
 
 proc run_eco_step {args} {
 	if {  $::env(ECO_ENABLE) == 1 } {
-        run_eco
-    }
+		run_eco_flow
+	}
+}
+
+proc run_magic_step {args} {
+	if {$::env(RUN_MAGIC)} {
+		run_magic
+	}
+}
+
+proc run_klayout_step {args} {
+	if {$::env(RUN_KLAYOUT)} {
+		run_klayout
+	}
+	if {$::env(RUN_KLAYOUT_XOR)} {
+		run_klayout_gds_xor
+	}
 }
 
 proc save_final_views {args} {
@@ -113,19 +145,19 @@
 	set arg_list [list]
 
 	# If they don't exist, save_views will simply not copy them
-	lappend arg_list -lef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef
-	lappend arg_list -gds_path $::env(finishing_results)/$::env(DESIGN_NAME).gds
-	lappend arg_list -mag_path $::env(finishing_results)/$::env(DESIGN_NAME).mag
-	lappend arg_list -maglef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef.mag
-	lappend arg_list -spice_path $::env(finishing_results)/$::env(DESIGN_NAME).spice
-	
+	lappend arg_list -lef_path $::env(signoff_results)/$::env(DESIGN_NAME).lef
+	lappend arg_list -gds_path $::env(signoff_results)/$::env(DESIGN_NAME).gds
+	lappend arg_list -mag_path $::env(signoff_results)/$::env(DESIGN_NAME).mag
+	lappend arg_list -maglef_path $::env(signoff_results)/$::env(DESIGN_NAME).lef.mag
+	lappend arg_list -spice_path $::env(signoff_results)/$::env(DESIGN_NAME).spice
+
 	# Guaranteed to have default values
 	lappend arg_list -def_path $::env(CURRENT_DEF)
 	lappend arg_list -verilog_path $::env(CURRENT_NETLIST)
 
 	# Not guaranteed to have default values
-	if { [info exists ::env(SPEF_TYPICAL)] } {
-		lappend arg_list -spef_path $::env(SPEF_TYPICAL)
+	if { [info exists ::env(CURRENT_SPEF)] } {
+		lappend arg_list -spef_path $::env(CURRENT_SPEF)
 	}
 	if { [info exists ::env(CURRENT_SDF)] } {
 		lappend arg_list -sdf_path $::env(CURRENT_SDF)
@@ -154,15 +186,13 @@
 	}
 }
 
-
-
-
 proc gen_pdn {args} {
-    puts_info "Generating PDN..."
+    increment_index
     TIMER::timer_start
-	
-    set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles).def]
-    set ::env(PGA_RPT_FILE) [index_file $::env(floorplan_tmpfiles).pga.rpt]
+    puts_info "Generating PDN..."
+
+    set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles)/pdn.def]
+    set ::env(PGA_RPT_FILE) [index_file $::env(floorplan_tmpfiles)/pdn.pga.rpt]
 
     run_openroad_script $::env(SCRIPTS_DIR)/openroad/pdn.tcl \
         |& -indexed_log [index_file $::env(floorplan_logs)/pdn.log]
@@ -177,12 +207,50 @@
 }
 
 proc run_power_grid_generation {args} {
+	if { [info exists ::env(VDD_NETS)] || [info exists ::env(GND_NETS)] } {
+		# they both must exist and be equal in length
+		# current assumption: they cannot have a common ground
+		if { ! [info exists ::env(VDD_NETS)] || ! [info exists ::env(GND_NETS)] } {
+			puts_err "VDD_NETS and GND_NETS must *both* either be defined or undefined"
+			return -code error
+		}
+		# standard cell power and ground nets are assumed to be the first net
+		set ::env(VDD_PIN) [lindex $::env(VDD_NETS) 0]
+		set ::env(GND_PIN) [lindex $::env(GND_NETS) 0]
+	} elseif { [info exists ::env(SYNTH_USE_PG_PINS_DEFINES)] } {
+		set ::env(VDD_NETS) [list]
+		set ::env(GND_NETS) [list]
+		# get the pins that are in $synthesis_tmpfiles.pg_define.v
+		# that are not in $synthesis_results.v
+		#
+		set full_pins {*}[extract_pins_from_yosys_netlist $::env(synthesis_tmpfiles)/pg_define.v]
+		puts_info $full_pins
 
-	if {[info exists ::env(FP_PDN_POWER_STRAPS)]} {
-	     set power_domains [split $::env(FP_PDN_POWER_STRAPS) ","]
+		set non_pg_pins {*}[extract_pins_from_yosys_netlist $::env(synthesis_results)/$::env(DESIGN_NAME).v]
+		puts_info $non_pg_pins
+
+		# assumes the pins are ordered correctly (e.g., vdd1, vss1, vcc1, vss1, ...)
+		foreach {vdd gnd} $full_pins {
+			if { $vdd ne "" && $vdd ni $non_pg_pins } {
+				lappend ::env(VDD_NETS) $vdd
+			}
+			if { $gnd ne "" && $gnd ni $non_pg_pins } {
+				lappend ::env(GND_NETS) $gnd
+			}
+		}
+	} else {
+		set ::env(VDD_NETS) $::env(VDD_PIN)
+		set ::env(GND_NETS) $::env(GND_PIN)
 	}
 
-	# internal macros power connections 
+	puts_info "Power planning with power {$::env(VDD_NETS)} and ground {$::env(GND_NETS)}..."
+
+	if { [llength $::env(VDD_NETS)] != [llength $::env(GND_NETS)] } {
+		puts_err "VDD_NETS and GND_NETS must be of equal lengths"
+		return -code error
+	}
+
+	# check internal macros' power connection definitions
 	if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} {
 		set macro_hooks [dict create]
 		set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
@@ -192,73 +260,19 @@
 			set ground_net [lindex $pdn_hook 2]
 			dict append macro_hooks $instance_name [subst {$power_net $ground_net}]
 		}
-		
+
 		set power_net_indx [lsearch $::env(VDD_NETS) $power_net]
 		set ground_net_indx [lsearch $::env(GND_NETS) $ground_net]
 
 		# make sure that the specified power domains exist.
 		if { $power_net_indx == -1  || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } {
 			puts_err "Can't find $power_net and $ground_net domain. \
-			Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)." 
-		} 
-	}
-	
-	# generate multiple power grids per pair of (VDD,GND)
-	# offseted by WIDTH + SPACING
-	foreach domain $power_domains {
-		set ::env(VDD_NET)       [lindex $domain 0]
-	        set ::env(GND_NET)       [lindex $domain 1]
-	        set ::env(_WITH_STRAPS)  [lindex $domain 2]
-
-	        puts_info "Connecting Power: $::env(VDD_NET) & $::env(GND_NET) to All internal macros."
-		# internal macros power connections
-		set ::env(FP_PDN_MACROS) ""
-		if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 } {
-			# if macros connections to power are explicitly set
-			# default behavoir macro pins will be connected to the first power domain
-			if { [info exists ::env(FP_PDN_MACRO_HOOKS)] } {
-				set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
-				foreach {instance_name hooks} $macro_hooks {
-					set power [lindex $hooks 0]
-					set ground [lindex $hooks 1]			 
-					if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } {
-						set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
-                                                set ::env(FP_PDN_IRDROP) "0"
-						puts_info "Connecting $instance_name to $power and $ground nets."
-						lappend ::env(FP_PDN_MACROS) $instance_name
-					}
-				}
-			} 
-		} else {
-			puts_warn "All internal macros will not be connected to power $::env(VDD_NET) & $::env(GND_NET)."
+				Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)."
 		}
-		
-		gen_pdn
-
-		set ::env(FP_PDN_ENABLE_RAILS) 0
-		set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
-                set ::env(FP_PDN_IRDROP) "0"
-
-		# allow failure until open_pdks is up to date...
-		catch {set ::env(FP_PDN_VOFFSET) [expr $::env(FP_PDN_VOFFSET)+$::env(FP_PDN_VWIDTH)+$::env(FP_PDN_VSPACING)]}
-		catch {set ::env(FP_PDN_HOFFSET) [expr $::env(FP_PDN_HOFFSET)+$::env(FP_PDN_HWIDTH)+$::env(FP_PDN_HSPACING)]}
-
-		catch {set ::env(FP_PDN_CORE_RING_VOFFSET) \
-			[expr $::env(FP_PDN_CORE_RING_VOFFSET)\
-			+2*($::env(FP_PDN_CORE_RING_VWIDTH)\
-			+max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
-		catch {set ::env(FP_PDN_CORE_RING_HOFFSET) [expr $::env(FP_PDN_CORE_RING_HOFFSET)\
-			+2*($::env(FP_PDN_CORE_RING_HWIDTH)+\
-			max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
-		puts "FP_PDN_VOFFSET: $::env(FP_PDN_VOFFSET)"
-		puts "FP_PDN_HOFFSET: $::env(FP_PDN_HOFFSET)"
-		puts "FP_PDN_CORE_RING_VOFFSET: $::env(FP_PDN_CORE_RING_VOFFSET)"
-		puts "FP_PDN_CORE_RING_HOFFSET: $::env(FP_PDN_CORE_RING_HOFFSET)"
-
 	}
-	set ::env(FP_PDN_ENABLE_RAILS) 1
-}
 
+	gen_pdn
+}
 
 proc run_floorplan {args} {
 	puts_info "Running Floorplanning..."
@@ -333,6 +347,10 @@
 	prep {*}$args
     # signal trap SIGINT save_state;
 
+	if { [info exists flags_map(-gui)] } {
+		or_gui
+		return
+	}
 	if { [info exists arg_values(-override_env)] } {
 		set env_overrides [split $arg_values(-override_env) ','] 
 		foreach override $env_overrides {
@@ -344,25 +362,25 @@
 	}
 
     set LVS_ENABLED 1
-    set DRC_ENABLED 1
+    set DRC_ENABLED 0
     set ANTENNACHECK_ENABLED 1
 
-    set steps [dict create \
-		"synthesis" {run_synthesis "" } \
-		"floorplan" {run_floorplan ""} \
-		"placement" {run_placement_step ""} \
-		"cts" {run_cts_step ""} \
-		"routing" {run_routing_step ""}\
-                "eco" {run_eco_step ""} \
-		"diode_insertion" {run_diode_insertion_2_5_step ""} \
-		"gds_magic" {run_magic ""} \
-		"gds_drc_klayout" {run_klayout ""} \
-		"gds_xor_klayout" {run_klayout_gds_xor ""} \
-		"lvs" "run_lvs_step $LVS_ENABLED" \
-		"drc" "run_drc_step $DRC_ENABLED" \
-		"antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
-		"cvc" {run_lef_cvc}
-    ]
+	set steps [dict create \
+		"synthesis" "run_synthesis" \
+		"floorplan" "run_floorplan" \
+		"placement" "run_placement_step" \
+		"cts" "run_cts_step" \
+		"routing" "run_routing_step" \
+		"parasitics_sta" "run_parasitics_sta_step" \
+		"eco" "run_eco_step" \
+		"diode_insertion" "run_diode_insertion_2_5_step" \
+		"gds_magic" "run_magic_step" \
+		"gds_klayout" "run_klayout_step" \
+		"lvs" "run_lvs_step $LVS_ENABLED " \
+		"drc" "run_drc_step $DRC_ENABLED " \
+		"antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+		"cvc" "run_lef_cvc"
+	]
 
     set_if_unset arg_values(-to) "cvc";
 
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 9b2fa9f..752b00b 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,15 +1,15 @@
-u_qspi_master           2275             710           N
-u_uart_i2c_usb_spi      2275            1410           N
-u_pinmux                2275            2250           N
+u_qspi_master                2250             650           N
+u_uart_i2c_usb_spi           2250            1350           N
+u_pinmux                     2250            2150           N
 
-u_tcm_1KB_mem0          125             1750           N 
-u_tcm_1KB_mem1          125             2645           N 
-u_riscv_top	        850	        955	       N
-u_icache_1KB_mem0       125             900            N
-u_icache_1KB_mem1       800             110            N
+u_riscv_top.i_core_top_0    50	            1400 	   N
+u_riscv_top.u_connect       725	            1400	   N
+u_riscv_top.u_intf          950 	    650	           N
+u_dcache_2kb                150             130            N
+u_icache_2kb                950             130            N
+u_tsram0_2kb                150             750            N
 
-u_dcache_1KB_mem0       850             2645           N
-u_dcache_1KB_mem1       1575            2645           N
 
-u_intercon              1850            710            N
-u_wb_host               1750            175            N
+u_intercon                  1850            650            N
+u_wb_host                   1750            100            N
+u_pll                       2200            100            N
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl
index 7813f95..1bd5f1e 100644
--- a/openlane/user_project_wrapper/pdn_cfg.tcl
+++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -8,89 +8,158 @@
 	set ::env(GND_NET) $::env(GND_PIN)
 }
 
-set ::power_nets $::env(VDD_NET)
-set ::ground_nets $::env(GND_NET)
-
 if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
     if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
         foreach power_pin $::env(STD_CELL_POWER_PINS) {
-            add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern $power_pin -power
+            add_global_connection \
+                -net $::env(VDD_NET) \
+                -inst_pattern .* \
+                -pin_pattern $power_pin \
+                -power
         }
         foreach ground_pin $::env(STD_CELL_GROUND_PINS) {
-            add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern $ground_pin -ground
+            add_global_connection \
+                -net $::env(GND_NET) \
+                -inst_pattern .* \
+                -pin_pattern $ground_pin \
+                -ground
         }
     }
 }
 
-set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)
+if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 &&
+     [info exists ::env(FP_PDN_MACRO_HOOKS)]} {
+    set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
+    foreach pdn_hook $pdn_hooks {
+        set instance_name [lindex $pdn_hook 0]
+        set power_net [lindex $pdn_hook 1]
+        set ground_net [lindex $pdn_hook 2]
+        # This assumes the power pin and the power net have the same name.
+        # The macro hooks only give an instance name and not power pin names.
 
-# Assesses whether the deisgn is the core of the chip or not based on the 
+        add_global_connection \
+            -net $power_net \
+            -inst_pattern $instance_name \
+            -pin_pattern $power_net \
+            -power
+
+        add_global_connection \
+            -net $ground_net \
+            -inst_pattern $instance_name \
+            -pin_pattern $ground_net \
+            -ground
+    }
+}
+
+set secondary []
+
+foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
+    if { $vdd != $::env(VDD_NET)} {
+        lappend secondary $vdd
+
+        set db_net [[ord::get_db_block] findNet $vdd]
+        if {$db_net == "NULL"} {
+            set net [odb::dbNet_create [ord::get_db_block] $vdd]
+            $net setSpecial
+            $net setSigType "POWER"
+        }
+    }
+
+    if { $gnd != $::env(GND_NET)} {
+        lappend secondary $gnd
+
+        set db_net [[ord::get_db_block] findNet $gnd]
+        if {$db_net == "NULL"} {
+            set net [odb::dbNet_create [ord::get_db_block] $gnd]
+            $net setSpecial
+            $net setSigType "GROUND"
+        }
+    }
+}
+
+set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
+    -secondary_power $secondary
+
+# Assesses whether the design is the core of the chip or not based on the
 # value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
 if { $::env(DESIGN_IS_CORE) == 1 } {
     # Used if the design is the core of the chip
-    define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
-    if { $::env(_WITH_STRAPS) } {
-        add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
-        add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_UPPER_LAYER) -width $::env(FP_PDN_HWIDTH) -pitch $::env(FP_PDN_HPITCH) -offset $::env(FP_PDN_HOFFSET) -starts_with POWER
-    } 
-    add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
+    define_pdn_grid \
+        -name stdcell_grid \
+        -starts_with POWER \
+        -voltage_domain CORE \
+        -pins "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
+
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer $::env(FP_PDN_LOWER_LAYER) \
+        -width $::env(FP_PDN_VWIDTH) \
+        -pitch $::env(FP_PDN_VPITCH) \
+        -offset $::env(FP_PDN_VOFFSET) \
+	-nets "$::env(VDD_NET) $::env(GND_NET)" \
+        -starts_with POWER -extend_to_core_ring
+
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer $::env(FP_PDN_UPPER_LAYER) \
+        -width $::env(FP_PDN_HWIDTH) \
+        -pitch $::env(FP_PDN_HPITCH) \
+        -offset $::env(FP_PDN_HOFFSET) \
+	-nets "$::env(VDD_NET) $::env(GND_NET)" \
+        -starts_with POWER -extend_to_core_ring
+
+    add_pdn_connect \
+        -grid stdcell_grid \
+        -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
 } else {
     # Used if the design is a macro in the core
-    define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins $::env(FP_PDN_LOWER_LAYER)
-    add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
+    define_pdn_grid \
+        -name stdcell_grid \
+        -starts_with POWER \
+        -voltage_domain CORE \
+        -pins $::env(FP_PDN_LOWER_LAYER)
+
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer $::env(FP_PDN_LOWER_LAYER) \
+        -width $::env(FP_PDN_VWIDTH) \
+        -pitch $::env(FP_PDN_VPITCH) \
+        -offset $::env(FP_PDN_VOFFSET) \
+        -starts_with POWER
 }
 
 # Adds the standard cell rails if enabled.
 if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
-    add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_RAILS_LAYER) -width $::env(FP_PDN_RAIL_WIDTH) -followpins -starts_with POWER
-    add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}]
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer $::env(FP_PDN_RAILS_LAYER) \
+        -width $::env(FP_PDN_RAIL_WIDTH) \
+        -followpins \
+        -starts_with POWER
+
+    add_pdn_connect \
+        -grid stdcell_grid \
+        -layers "$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)"
 } 
 
 
 # Adds the core ring if enabled.
 if { $::env(FP_PDN_CORE_RING) == 1 } {
-    add_pdn_ring -grid stdcell_grid -layer [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]  \
-                     -widths [subst {$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)}] \
-                     -spacings [subst {$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)}] \
-                     -core_offset [subst {$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)}]
+    add_pdn_ring \
+        -grid stdcell_grid \
+        -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)" \
+        -widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \
+        -spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
+        -core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
 }
 
-# A general macro that follows the premise of the set heirarchy. You may want to modify this or add other macro configs
-# The macro power pin names are assumed to match the VDD and GND net names 
-# TODO: parameterize the power pin names 
-set macro {
-    orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
-    power_pins $::env(VDD_NET)
-    ground_pins $::env(GND_NET)
-    blockages $::env(MACRO_BLOCKAGES_LAYER)
-    straps {
-    }
-    connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}}
-}
+define_pdn_grid \
+    -macro \
+    -default \
+    -name macro \
+    -starts_with POWER \
+    -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
 
-if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1} {
-    if { [llength $::env(FP_PDN_MACROS)] > 0 } {
-        # generate automatically per instance:
-        foreach macro_instance $::env(FP_PDN_MACROS) {
-            set macro_instance_grid [subst $macro] 
-            dict append $macro_instance_grid instance $macro_instance
-            set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
-            pdngen::specify_grid macro [subst $macro_instance_grid]
-        }
-    } else {
-        set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
-        pdngen::specify_grid macro [subst $macro]
-    }
-    # CAN NOT ENABLE THE TCL COMMAND BECAUSE THERE IS NO ARGUMENT FOR SPECIFYING THE POWER AND GROUND PIN NAMES ON THE MACRO
-    # define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -pin_direction vertical -halo [subst {$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)}]
-    # add_pdn_connect -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
-} else {
-    define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -halo [subst {$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)}]
-}
-
-# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
-set ::rails_start_with "POWER" ;
-
-# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
-set ::stripes_start_with "POWER" ;
-
+add_pdn_connect \
+    -grid macro \
+    -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
diff --git a/openlane/wb_host/base.sdc b/openlane/wb_host/base.sdc
index 9d9cc79..a5b2325 100644
--- a/openlane/wb_host/base.sdc
+++ b/openlane/wb_host/base.sdc
@@ -8,7 +8,12 @@
 ###############################################################################
 create_clock -name wbm_clk_i -period 10.0000 [get_ports {wbm_clk_i}]
 create_clock -name wbs_clk_i -period 10.0000 [get_ports {wbs_clk_i}]
-create_clock -name uart_clk -period 100.0000 [get_pins {u_uart2wb.u_core.u_uart_clk.u_mux/X}]
+create_clock -name uart_clk -period 100.0000 [get_pins {u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
+
+create_clock -name int_pll_clock -period 10.0000  [get_pins {u_clkbuf_pll.u_buf/X}]
+create_clock -name wbs_ref_clk   -period 10.0000  [get_pins {u_wbs_ref_clkbuf.u_buf/X}]
+create_clock -name cpu_ref_clk   -period 10.0000  [get_pins {u_cpu_ref_clkbuf.u_buf/X}]
+create_clock -name usb_ref_clk   -period 10.0000  [get_pins {u_usb_ref_clkbuf.u_buf/X}]
 
 set_clock_transition 0.1500 [all_clocks]
 set_clock_uncertainty -setup 0.2500 [all_clocks]
@@ -20,9 +25,14 @@
 set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
 
 set_clock_groups -name async_clock -asynchronous \
- -group [get_clocks {uart_clk}]  \
- -group [get_clocks {wbs_clk_i}] \
- -group [get_clocks {wbm_clk_i}] -comment {Async Clock group}
+ -group [get_clocks {uart_clk}]      \
+ -group [get_clocks {wbs_clk_i}]     \
+ -group [get_clocks {wbm_clk_i}]     \
+ -group [get_clocks {int_pll_clock}] \
+ -group [get_clocks {wbs_ref_clk}]   \
+ -group [get_clocks {cpu_ref_clk}]   \
+ -group [get_clocks {usb_ref_clk}]   \
+ -comment {Async Clock group}
 
 ### ClkSkew Adjust
 set_case_analysis 0 [get_ports {cfg_cska_wh[0]}]
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 1dabc40..0d8ff81 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -26,7 +26,7 @@
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "wbm_clk_i wbs_clk_i u_uart2wb.u_core.u_uart_clk.u_mux/X"
+set ::env(CLOCK_PORT) "wbm_clk_i wbs_clk_i u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X"
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
@@ -85,7 +85,7 @@
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.38"
+set ::env(PL_TARGET_DENSITY) "0.40"
 
 
 
@@ -97,7 +97,7 @@
 set ::env(FP_PDN_VWIDTH) 5
 set ::env(FP_PDN_HWIDTH) 5
 
-set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 3448c6c..17b3e01 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -5,22 +5,6 @@
 
 #W
 usb_clk          0000 0 4
-cfg_clk_ctrl1\[31\]
-cfg_clk_ctrl1\[30\]
-cfg_clk_ctrl1\[29\]
-cfg_clk_ctrl1\[28\]
-cfg_clk_ctrl2\[27\]
-cfg_clk_ctrl2\[26\]
-cfg_clk_ctrl2\[25\]
-cfg_clk_ctrl2\[24\]
-cfg_clk_ctrl2\[23\]
-cfg_clk_ctrl2\[22\]
-cfg_clk_ctrl2\[21\]
-cfg_clk_ctrl2\[20\]
-cfg_clk_ctrl2\[19\]
-cfg_clk_ctrl2\[18\]
-cfg_clk_ctrl2\[17\]
-cfg_clk_ctrl2\[16\]
 
 cpu_clk               0100 0 2
 rtc_clk
@@ -159,33 +143,61 @@
 la_data_in\[17\]    
 
 #E
+cfg_dc_trim\[7\]   000 0 2
+cfg_dc_trim\[8\]
+cfg_dc_trim\[9\]
+cfg_dc_trim\[10\]
+cfg_dc_trim\[11\]
+cfg_dc_trim\[12\]
+cfg_dc_trim\[13\]
+cfg_dc_trim\[14\]
+cfg_dc_trim\[15\]
+cfg_dc_trim\[16\]
+cfg_dc_trim\[17\]
+cfg_dc_trim\[18\]
+cfg_dc_trim\[19\]
 
-uartm_rxd           100 0 2
+cfg_dc_trim\[25\]
+cfg_dc_trim\[24\]
+cfg_dc_trim\[23\]
+cfg_dc_trim\[22\]
+cfg_dc_trim\[21\]
+cfg_dc_trim\[20\]
+
+pll_clk_out\[0\]
+pll_clk_out\[1\]
+cfg_pll_fed_div\[0\]
+cfg_pll_fed_div\[1\]
+cfg_pll_fed_div\[2\]
+cfg_pll_fed_div\[3\]
+cfg_pll_fed_div\[4\]
+cfg_pll_enb
+cfg_dco_mode
+cfg_dc_trim\[0\]
+cfg_dc_trim\[1\]
+cfg_dc_trim\[2\]
+cfg_dc_trim\[3\]
+cfg_dc_trim\[4\]
+cfg_dc_trim\[5\]
+cfg_dc_trim\[6\]
+
+wbd_pll_rst_n 
+pll_ref_clk  
+
+
+
+uartm_rxd           300 0 2
 uartm_txd
 
+dbg_clk_mon
+
 
 #N
 wbd_int_rst_n         0100 0 2
-cfg_clk_ctrl2\[31\]
-cfg_clk_ctrl2\[30\]
-cfg_clk_ctrl2\[29\]
-cfg_clk_ctrl2\[28\]
-cfg_clk_ctrl2\[15\]
-cfg_clk_ctrl2\[14\]
-cfg_clk_ctrl2\[13\]
-cfg_clk_ctrl2\[12\]
-cfg_clk_ctrl2\[11\]
-cfg_clk_ctrl2\[10\]
-cfg_clk_ctrl2\[9\]
-cfg_clk_ctrl2\[8\]
-cfg_clk_ctrl2\[7\]
-cfg_clk_ctrl2\[6\]
-cfg_clk_ctrl2\[5\]
-cfg_clk_ctrl2\[4\]
-cfg_clk_ctrl2\[3\]
-cfg_clk_ctrl2\[2\]
-cfg_clk_ctrl2\[1\]
-cfg_clk_ctrl2\[0\]
+cfg_clk_ctrl1\[31\]
+cfg_clk_ctrl1\[30\]
+cfg_clk_ctrl1\[29\]
+cfg_clk_ctrl1\[28\]
 cfg_clk_ctrl1\[27\]
 cfg_clk_ctrl1\[26\]
 cfg_clk_ctrl1\[25\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 2b03cd9..33ac3c6 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -113,7 +113,7 @@
 set ::env(GLB_RT_ALLOW_CONGESTION) 0
 set ::env(GLB_RT_OVERFLOW_ITERS) 200
 
-set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
 
 
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index cca8e25..1534993 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -147,7 +147,7 @@
 
 
 #W
-ch_data_out\[36\]   0750 0 2
+ch_data_out\[36\]   000 0 2
 ch_data_out\[35\] 
 ch_data_out\[34\] 
 ch_data_out\[33\] 
@@ -172,7 +172,7 @@
 
 ch_clk_out\[0\]
 
-m1_wbd_stb_i         0950 0 2 
+m1_wbd_stb_i         100 0 2 
 m1_wbd_we_i         
 m1_wbd_adr_i\[31\]  
 m1_wbd_adr_i\[30\]  
@@ -279,7 +279,7 @@
 m1_wbd_err_o        
 m1_wbd_cyc_i        
 
-m2_wbd_stb_i        1150 0 2
+m2_wbd_stb_i        300 0 2
 m2_wbd_we_i         
 m2_wbd_adr_i\[31\]  
 m2_wbd_adr_i\[30\]  
@@ -397,7 +397,7 @@
 m2_wbd_err_o        
 m2_wbd_cyc_i       
 
-m3_wbd_stb_i        1350 0 2
+m3_wbd_stb_i        500 0 2
 m3_wbd_we_i         
 m3_wbd_adr_i\[31\]  
 m3_wbd_adr_i\[30\]  
@@ -701,7 +701,7 @@
 s1_wbd_ack_i        
 s1_wbd_cyc_o  
 
-ch_data_in\[36\]  1400 0 2  
+ch_data_in\[36\]  1500 0 2  
 ch_data_in\[35\]
 ch_data_in\[34\]
 ch_data_in\[33\]
@@ -725,7 +725,7 @@
 ch_data_out\[12\]
 ch_clk_out\[3\]
 
-s2_wbd_stb_o         1500 0 2
+s2_wbd_stb_o         1600 0 2
 s2_wbd_we_o         
 s2_wbd_adr_o\[7\]   
 s2_wbd_adr_o\[6\]   
diff --git a/openlane/ycr_core_top/base.sdc b/openlane/ycr_core_top/base.sdc
new file mode 100644
index 0000000..0a05d50
--- /dev/null
+++ b/openlane/ycr_core_top/base.sdc
@@ -0,0 +1,65 @@
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 10.0000 [get_ports {clk}]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+#IMEM Constraints
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
+
+#DMEM Constraints
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
+set_output_delay -max 2.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_resp_i[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_resp_i[*]}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs]
+set cap_load 0.0334
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl
new file mode 100644
index 0000000..8d0c0bd
--- /dev/null
+++ b/openlane/ycr_core_top/config.tcl
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(ROUTING_CORES) "6"
+
+set ::env(DESIGN_NAME) ycr_core_top
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "clk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+set ::env(LEC_ENABLE) 0
+
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_top.sv           \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_core_top.sv                    \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_dm.sv                          \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc_synchronizer.sv           \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_clk_ctrl.sv                    \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_scu.sv                         \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc.sv                        \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc_shift_reg.sv              \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_dmi.sv                         \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr_reset_cells.sv      \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ifu.sv           \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_idu.sv           \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_exu.sv           \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mprf.sv          \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_csr.sv           \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ialu.sv          \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mul.sv           \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_div.sv           \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_lsu.sv           \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_hdu.sv           \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_tdu.sv           \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_ipic.sv               \
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_req_retiming.sv               \
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/sync_fifo2.sv                     \
+	"
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+## Floorplan
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 540 950 "
+
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
+set ::env(PL_TARGET_DENSITY) 0.43
+set ::env(CELL_PAD) "4"
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 3
+
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
+
+#Need to cross-check why global timing opimization creating setup vio with hugh hold fix
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+
diff --git a/openlane/ycr_core_top/macro_placement.cfg b/openlane/ycr_core_top/macro_placement.cfg
new file mode 100644
index 0000000..8ec6301
--- /dev/null
+++ b/openlane/ycr_core_top/macro_placement.cfg
@@ -0,0 +1,2 @@
+u_icache.u_cmem_2kb  285.000 291.000 FS
+u_dcache.u_cmem_2kb 1185.000 291.000 N
diff --git a/openlane/ycr_core_top/pin_order.cfg b/openlane/ycr_core_top/pin_order.cfg
new file mode 100644
index 0000000..79b2c6f
--- /dev/null
+++ b/openlane/ycr_core_top/pin_order.cfg
@@ -0,0 +1,327 @@
+#BUS_SORT
+#MANUAL_PLACE
+#E
+core_uid\[1\]              0200 00 2
+core_uid\[0\]   
+imem2core_req_ack_i
+core2imem_req_o
+core2imem_cmd_o
+core2imem_addr_o\[31\]
+core2imem_addr_o\[30\]
+core2imem_addr_o\[29\]
+core2imem_addr_o\[28\]
+core2imem_addr_o\[27\]
+core2imem_addr_o\[26\]
+core2imem_addr_o\[25\]
+core2imem_addr_o\[24\]
+core2imem_addr_o\[23\]
+core2imem_addr_o\[22\]
+core2imem_addr_o\[21\]
+core2imem_addr_o\[20\]
+core2imem_addr_o\[19\]
+core2imem_addr_o\[18\]
+core2imem_addr_o\[17\]
+core2imem_addr_o\[16\]
+core2imem_addr_o\[15\]
+core2imem_addr_o\[14\]
+core2imem_addr_o\[13\]
+core2imem_addr_o\[12\]
+core2imem_addr_o\[11\]
+core2imem_addr_o\[10\]
+core2imem_addr_o\[9\]
+core2imem_addr_o\[8\]
+core2imem_addr_o\[7\]
+core2imem_addr_o\[6\]
+core2imem_addr_o\[5\]
+core2imem_addr_o\[4\]
+core2imem_addr_o\[3\]
+core2imem_addr_o\[2\]
+core2imem_addr_o\[1\]
+core2imem_addr_o\[0\]
+core2imem_bl_o\[2\]
+core2imem_bl_o\[1\]
+core2imem_bl_o\[0\]
+imem2core_rdata_i\[31\]
+imem2core_rdata_i\[30\]
+imem2core_rdata_i\[29\]
+imem2core_rdata_i\[28\]
+imem2core_rdata_i\[27\]
+imem2core_rdata_i\[26\]
+imem2core_rdata_i\[25\]
+imem2core_rdata_i\[24\]
+imem2core_rdata_i\[23\]
+imem2core_rdata_i\[22\]
+imem2core_rdata_i\[21\]
+imem2core_rdata_i\[20\]
+imem2core_rdata_i\[19\]
+imem2core_rdata_i\[18\]
+imem2core_rdata_i\[17\]
+imem2core_rdata_i\[16\]
+imem2core_rdata_i\[15\]
+imem2core_rdata_i\[14\]
+imem2core_rdata_i\[13\]
+imem2core_rdata_i\[12\]
+imem2core_rdata_i\[11\]
+imem2core_rdata_i\[10\]
+imem2core_rdata_i\[9\]
+imem2core_rdata_i\[8\]
+imem2core_rdata_i\[7\]
+imem2core_rdata_i\[6\]
+imem2core_rdata_i\[5\]
+imem2core_rdata_i\[4\]
+imem2core_rdata_i\[3\]
+imem2core_rdata_i\[2\]
+imem2core_rdata_i\[1\]
+imem2core_rdata_i\[0\]
+imem2core_resp_i\[1\]
+imem2core_resp_i\[0\]
+
+dmem2core_req_ack_i           0350 0 2
+core2dmem_req_o
+core2dmem_cmd_o
+core2dmem_width_o\[1\]
+core2dmem_width_o\[0\]
+core2dmem_addr_o\[31\]
+core2dmem_addr_o\[30\]
+core2dmem_addr_o\[29\]
+core2dmem_addr_o\[28\]
+core2dmem_addr_o\[27\]
+core2dmem_addr_o\[26\]
+core2dmem_addr_o\[25\]
+core2dmem_addr_o\[24\]
+core2dmem_addr_o\[23\]
+core2dmem_addr_o\[22\]
+core2dmem_addr_o\[21\]
+core2dmem_addr_o\[20\]
+core2dmem_addr_o\[19\]
+core2dmem_addr_o\[18\]
+core2dmem_addr_o\[17\]
+core2dmem_addr_o\[16\]
+core2dmem_addr_o\[15\]
+core2dmem_addr_o\[14\]
+core2dmem_addr_o\[13\]
+core2dmem_addr_o\[12\]
+core2dmem_addr_o\[11\]
+core2dmem_addr_o\[10\]
+core2dmem_addr_o\[9\]
+core2dmem_addr_o\[8\]
+core2dmem_addr_o\[7\]
+core2dmem_addr_o\[6\]
+core2dmem_addr_o\[5\]
+core2dmem_addr_o\[4\]
+core2dmem_addr_o\[3\]
+core2dmem_addr_o\[2\]
+core2dmem_addr_o\[1\]
+core2dmem_addr_o\[0\]
+core2dmem_wdata_o\[31\]
+core2dmem_wdata_o\[30\]
+core2dmem_wdata_o\[29\]
+core2dmem_wdata_o\[28\]
+core2dmem_wdata_o\[27\]
+core2dmem_wdata_o\[26\]
+core2dmem_wdata_o\[25\]
+core2dmem_wdata_o\[24\]
+core2dmem_wdata_o\[23\]
+core2dmem_wdata_o\[22\]
+core2dmem_wdata_o\[21\]
+core2dmem_wdata_o\[20\]
+core2dmem_wdata_o\[19\]
+core2dmem_wdata_o\[18\]
+core2dmem_wdata_o\[17\]
+core2dmem_wdata_o\[16\]
+core2dmem_wdata_o\[15\]
+core2dmem_wdata_o\[14\]
+core2dmem_wdata_o\[13\]
+core2dmem_wdata_o\[12\]
+core2dmem_wdata_o\[11\]
+core2dmem_wdata_o\[10\]
+core2dmem_wdata_o\[9\]
+core2dmem_wdata_o\[8\]
+core2dmem_wdata_o\[7\]
+core2dmem_wdata_o\[6\]
+core2dmem_wdata_o\[5\]
+core2dmem_wdata_o\[4\]
+core2dmem_wdata_o\[3\]
+core2dmem_wdata_o\[2\]
+core2dmem_wdata_o\[1\]
+core2dmem_wdata_o\[0\]
+dmem2core_rdata_i\[31\]
+dmem2core_rdata_i\[30\]
+dmem2core_rdata_i\[29\]
+dmem2core_rdata_i\[28\]
+dmem2core_rdata_i\[27\]
+dmem2core_rdata_i\[26\]
+dmem2core_rdata_i\[25\]
+dmem2core_rdata_i\[24\]
+dmem2core_rdata_i\[23\]
+dmem2core_rdata_i\[22\]
+dmem2core_rdata_i\[21\]
+dmem2core_rdata_i\[20\]
+dmem2core_rdata_i\[19\]
+dmem2core_rdata_i\[18\]
+dmem2core_rdata_i\[17\]
+dmem2core_rdata_i\[16\]
+dmem2core_rdata_i\[15\]
+dmem2core_rdata_i\[14\]
+dmem2core_rdata_i\[13\]
+dmem2core_rdata_i\[12\]
+dmem2core_rdata_i\[11\]
+dmem2core_rdata_i\[10\]
+dmem2core_rdata_i\[9\]
+dmem2core_rdata_i\[8\]
+dmem2core_rdata_i\[7\]
+dmem2core_rdata_i\[6\]
+dmem2core_rdata_i\[5\]
+dmem2core_rdata_i\[4\]
+dmem2core_rdata_i\[3\]
+dmem2core_rdata_i\[2\]
+dmem2core_rdata_i\[1\]
+dmem2core_rdata_i\[0\]
+dmem2core_resp_i\[1\]
+dmem2core_resp_i\[0\]
+
+core_debug\[48\]         0500 0 2
+core_debug\[47\]
+core_debug\[46\]
+core_debug\[45\]
+core_debug\[44\]
+core_debug\[43\]
+core_debug\[42\]
+core_debug\[41\]
+core_debug\[40\]
+core_debug\[39\]
+core_debug\[38\]
+core_debug\[37\]
+core_debug\[36\]
+core_debug\[35\]
+core_debug\[34\]
+core_debug\[33\]
+core_debug\[32\]
+core_debug\[31\]
+core_debug\[30\]
+core_debug\[29\]
+core_debug\[28\]
+core_debug\[27\]
+core_debug\[26\]
+core_debug\[25\]
+core_debug\[24\]
+core_debug\[23\]
+core_debug\[22\]
+core_debug\[21\]
+core_debug\[20\]
+core_debug\[19\]
+core_debug\[18\]
+core_debug\[17\]
+core_debug\[16\]
+core_debug\[15\]
+core_debug\[14\]
+core_debug\[13\]
+core_debug\[12\]
+core_debug\[11\]
+core_debug\[10\]
+core_debug\[9\]
+core_debug\[8\]
+core_debug\[7\]
+core_debug\[6\]
+core_debug\[5\]
+core_debug\[4\]
+core_debug\[3\]
+core_debug\[2\]
+core_debug\[1\]
+core_debug\[0\]
+
+core_irq_mtimer_i            0600 0 2
+core_mtimer_val_i\[63\]
+core_mtimer_val_i\[62\]
+core_mtimer_val_i\[61\]
+core_mtimer_val_i\[60\]
+core_mtimer_val_i\[59\]
+core_mtimer_val_i\[58\]
+core_mtimer_val_i\[57\]
+core_mtimer_val_i\[56\]
+core_mtimer_val_i\[55\]
+core_mtimer_val_i\[54\]
+core_mtimer_val_i\[53\]
+core_mtimer_val_i\[52\]
+core_mtimer_val_i\[51\]
+core_mtimer_val_i\[50\]
+core_mtimer_val_i\[49\]
+core_mtimer_val_i\[48\]
+core_mtimer_val_i\[47\]
+core_mtimer_val_i\[46\]
+core_mtimer_val_i\[45\]
+core_mtimer_val_i\[44\]
+core_mtimer_val_i\[43\]
+core_mtimer_val_i\[42\]
+core_mtimer_val_i\[41\]
+core_mtimer_val_i\[40\]
+core_mtimer_val_i\[39\]
+core_mtimer_val_i\[38\]
+core_mtimer_val_i\[37\]
+core_mtimer_val_i\[36\]
+core_mtimer_val_i\[35\]
+core_mtimer_val_i\[34\]
+core_mtimer_val_i\[33\]
+core_mtimer_val_i\[32\]
+core_mtimer_val_i\[31\]
+core_mtimer_val_i\[30\]
+core_mtimer_val_i\[29\]
+core_mtimer_val_i\[28\]
+core_mtimer_val_i\[27\]
+core_mtimer_val_i\[26\]
+core_mtimer_val_i\[25\]
+core_mtimer_val_i\[24\]
+core_mtimer_val_i\[23\]
+core_mtimer_val_i\[22\]
+core_mtimer_val_i\[21\]
+core_mtimer_val_i\[20\]
+core_mtimer_val_i\[19\]
+core_mtimer_val_i\[18\]
+core_mtimer_val_i\[17\]
+core_mtimer_val_i\[16\]
+core_mtimer_val_i\[15\]
+core_mtimer_val_i\[14\]
+core_mtimer_val_i\[13\]
+core_mtimer_val_i\[12\]
+core_mtimer_val_i\[11\]
+core_mtimer_val_i\[10\]
+core_mtimer_val_i\[9\]
+core_mtimer_val_i\[8\]
+core_mtimer_val_i\[7\]
+core_mtimer_val_i\[6\]
+core_mtimer_val_i\[5\]
+core_mtimer_val_i\[4\]
+core_mtimer_val_i\[3\]
+core_mtimer_val_i\[2\]
+core_mtimer_val_i\[1\]
+core_mtimer_val_i\[0\]
+
+core_irq_lines_i\[15\]
+core_irq_lines_i\[14\]
+core_irq_lines_i\[13\]
+core_irq_lines_i\[12\]
+core_irq_lines_i\[11\]
+core_irq_lines_i\[10\]
+core_irq_lines_i\[9\]
+core_irq_lines_i\[8\]
+core_irq_lines_i\[7\]
+core_irq_lines_i\[6\]
+core_irq_lines_i\[5\]
+core_irq_lines_i\[4\]
+core_irq_lines_i\[3\]
+core_irq_lines_i\[2\]
+core_irq_lines_i\[1\]
+core_irq_lines_i\[0\]
+core_irq_soft_i
+cpu_rst_n
+
+#S
+pwrup_rst_n       
+rst_n
+
+
+
+clk
+clk_o
+core_rst_n_o
+core_rdc_qlfy_o
diff --git a/openlane/ycr_iconnect/base.sdc b/openlane/ycr_iconnect/base.sdc
new file mode 100644
index 0000000..a8461ed
--- /dev/null
+++ b/openlane/ycr_iconnect/base.sdc
@@ -0,0 +1,97 @@
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 8.0000 [get_ports {core_clk}]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+#CORE-0 IMEM Constraints
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
+
+set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
+set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
+set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req_ack}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}]
+
+#CORE-0 DMEM Constraints
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req_ack}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}]
+
+#CORE-1 IMEM Constraints
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}]
+
+set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
+set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
+set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}]
+set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req_ack}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_rdata[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_rdata[*]}]
+
+#CORE-1 DMEM Constraints
+set_input_delay  -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
+set_input_delay  -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
+set_input_delay  -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}]
+set_input_delay  -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}]
+set_input_delay  -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}]
+
+set_input_delay  -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
+set_input_delay  -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
+set_input_delay  -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}]
+set_input_delay  -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}]
+set_input_delay  -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req_ack}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_rdata[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_rdata[*]}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs]
+set cap_load 0.0334
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/openlane/ycr_iconnect/config.tcl b/openlane/ycr_iconnect/config.tcl
new file mode 100644
index 0000000..45f429b
--- /dev/null
+++ b/openlane/ycr_iconnect/config.tcl
@@ -0,0 +1,100 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(ROUTING_CORES) "6"
+
+set ::env(DESIGN_NAME) ycr_iconnect
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "core_clk rtc_clk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+set ::env(LEC_ENABLE) 0
+
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_iconnect.sv                  \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_cross_bar.sv                 \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_router.sv                    \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_dmem_router.sv                \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_sram_mux.sv                   \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_tcm.sv                        \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_timer.sv                      \
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_req_retiming.sv               \
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ycr_arb.sv                        \
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ctech_cells.sv                    \
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/sync_fifo2.sv                     \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr_reset_cells.sv    \
+	"
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
+set ::env(LEC_ENABLE) 0
+
+## Floorplan
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 380 1100"
+
+#set ::env(PDN_CFG) $script_dir/pdn_cfg.tcl
+#set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
+set ::env(PL_TARGET_DENSITY) 0.20
+set ::env(CELL_PAD) "14"
+
+#set ::env(PL_ROUTABILITY_DRIVEN) "1"
+set ::env(PL_TIME_DRIVEN) "1"
+
+### PDN
+#set ::env(FP_PDN_CHECK_NODES) "0"
+#set ::env(FP_PDN_HORIZONTAL_HALO) "10"
+#set ::env(FP_PDN_VERTICAL_HALO) "10"
+#
+#set ::env(FP_PDN_VOFFSET) "5"
+#set ::env(FP_PDN_VPITCH) "80"
+#set ::env(FP_PDN_VSPACING) "15.5"
+#set ::env(FP_PDN_VWIDTH) "3.1"
+#
+#set ::env(FP_PDN_HOFFSET) "10"
+#set ::env(FP_PDN_HPITCH) "100"
+#set ::env(FP_PDN_HSPACING) "10"
+#set ::env(FP_PDN_HWIDTH) "3.1"
+
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 20
+set ::env(DIODE_INSERTION_STRATEGY) 3
+
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
+
+
diff --git a/openlane/ycr_iconnect/drc_exclude.cells b/openlane/ycr_iconnect/drc_exclude.cells
new file mode 100644
index 0000000..0ecc9c0
--- /dev/null
+++ b/openlane/ycr_iconnect/drc_exclude.cells
@@ -0,0 +1,55 @@
+sky130_fd_sc_hd__a2111oi_0
+sky130_fd_sc_hd__a21boi_0
+sky130_fd_sc_hd__and2_0
+sky130_fd_sc_hd__buf_16
+sky130_fd_sc_hd__clkdlybuf4s15_1
+sky130_fd_sc_hd__clkdlybuf4s18_1
+sky130_fd_sc_hd__clkdlybuf4s25_1
+sky130_fd_sc_hd__clkdlybuf4s50_1
+sky130_fd_sc_hd__fa_4
+sky130_fd_sc_hd__lpflow_bleeder_1
+sky130_fd_sc_hd__lpflow_clkbufkapwr_1
+sky130_fd_sc_hd__lpflow_clkbufkapwr_16
+sky130_fd_sc_hd__lpflow_clkbufkapwr_2
+sky130_fd_sc_hd__lpflow_clkbufkapwr_4
+sky130_fd_sc_hd__lpflow_clkbufkapwr_8
+sky130_fd_sc_hd__lpflow_clkinvkapwr_1
+sky130_fd_sc_hd__lpflow_clkinvkapwr_16
+sky130_fd_sc_hd__lpflow_clkinvkapwr_2
+sky130_fd_sc_hd__lpflow_clkinvkapwr_4
+sky130_fd_sc_hd__lpflow_clkinvkapwr_8
+sky130_fd_sc_hd__lpflow_decapkapwr_12
+sky130_fd_sc_hd__lpflow_decapkapwr_3
+sky130_fd_sc_hd__lpflow_decapkapwr_4
+sky130_fd_sc_hd__lpflow_decapkapwr_6
+sky130_fd_sc_hd__lpflow_decapkapwr_8
+sky130_fd_sc_hd__lpflow_inputiso0n_1
+sky130_fd_sc_hd__lpflow_inputiso0p_1
+sky130_fd_sc_hd__lpflow_inputiso1n_1
+sky130_fd_sc_hd__lpflow_inputiso1p_1
+sky130_fd_sc_hd__lpflow_inputisolatch_1
+sky130_fd_sc_hd__lpflow_isobufsrc_1
+sky130_fd_sc_hd__lpflow_isobufsrc_16
+sky130_fd_sc_hd__lpflow_isobufsrc_2
+sky130_fd_sc_hd__lpflow_isobufsrc_4
+sky130_fd_sc_hd__lpflow_isobufsrc_8
+sky130_fd_sc_hd__lpflow_isobufsrckapwr_16
+sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1
+sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2
+sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4
+sky130_fd_sc_hd__mux4_4
+sky130_fd_sc_hd__o21ai_0
+sky130_fd_sc_hd__o311ai_0
+sky130_fd_sc_hd__or2_0
+sky130_fd_sc_hd__probe_p_8
+sky130_fd_sc_hd__probec_p_8
+sky130_fd_sc_hd__xor3_1
+sky130_fd_sc_hd__xor3_2
+sky130_fd_sc_hd__xor3_4
+sky130_fd_sc_hd__xnor3_1
+sky130_fd_sc_hd__xnor3_2
+sky130_fd_sc_hd__xnor3_4
\ No newline at end of file
diff --git a/openlane/ycr_iconnect/pin_order.cfg b/openlane/ycr_iconnect/pin_order.cfg
new file mode 100644
index 0000000..1c9fbd6
--- /dev/null
+++ b/openlane/ycr_iconnect/pin_order.cfg
@@ -0,0 +1,821 @@
+#BUS_SORT
+#MANUAL_PLACE
+
+#W
+sram0_clk0                  000  0   2
+sram0_csb0
+sram0_web0
+sram0_addr0\[8\]
+sram0_addr0\[7\]
+sram0_addr0\[6\]
+sram0_addr0\[5\]
+sram0_addr0\[4\]
+sram0_addr0\[3\]
+sram0_addr0\[2\]
+sram0_addr0\[1\]
+sram0_addr0\[0\]
+sram0_wmask0\[3\]
+sram0_wmask0\[2\]
+sram0_wmask0\[1\]
+sram0_wmask0\[0\]
+sram0_din0\[31\]
+sram0_din0\[30\]
+sram0_din0\[29\]
+sram0_din0\[28\]
+sram0_din0\[27\]
+sram0_din0\[26\]
+sram0_din0\[25\]
+sram0_din0\[24\]
+sram0_din0\[23\]
+sram0_din0\[22\]
+sram0_din0\[21\]
+sram0_din0\[20\]
+sram0_din0\[19\]
+sram0_din0\[18\]
+sram0_din0\[17\]
+sram0_din0\[16\]
+sram0_din0\[15\]
+sram0_din0\[14\]
+sram0_din0\[13\]
+sram0_din0\[12\]
+sram0_din0\[11\]
+sram0_din0\[10\]
+sram0_din0\[9\]
+sram0_din0\[8\]
+sram0_din0\[7\]
+sram0_din0\[6\]
+sram0_din0\[5\]
+sram0_din0\[4\]
+sram0_din0\[3\]
+sram0_din0\[2\]
+sram0_din0\[1\]
+sram0_din0\[0\]
+sram0_dout0\[31\]
+sram0_dout0\[30\]
+sram0_dout0\[29\]
+sram0_dout0\[28\]
+sram0_dout0\[27\]
+sram0_dout0\[26\]
+sram0_dout0\[25\]
+sram0_dout0\[24\]
+sram0_dout0\[23\]
+sram0_dout0\[22\]
+sram0_dout0\[21\]
+sram0_dout0\[20\]
+sram0_dout0\[19\]
+sram0_dout0\[18\]
+sram0_dout0\[17\]
+sram0_dout0\[16\]
+sram0_dout0\[15\]
+sram0_dout0\[14\]
+sram0_dout0\[13\]
+sram0_dout0\[12\]
+sram0_dout0\[11\]
+sram0_dout0\[10\]
+sram0_dout0\[9\]
+sram0_dout0\[8\]
+sram0_dout0\[7\]
+sram0_dout0\[6\]
+sram0_dout0\[5\]
+sram0_dout0\[4\]
+sram0_dout0\[3\]
+sram0_dout0\[2\]
+sram0_dout0\[1\]
+sram0_dout0\[0\]
+
+
+sram0_clk1               110  0 2
+sram0_csb1
+sram0_addr1\[8\]
+sram0_addr1\[7\]
+sram0_addr1\[6\]
+sram0_addr1\[5\]
+sram0_addr1\[4\]
+sram0_addr1\[3\]
+sram0_addr1\[2\]
+sram0_addr1\[1\]
+sram0_addr1\[0\]
+sram0_dout1\[31\]
+sram0_dout1\[30\]
+sram0_dout1\[29\]
+sram0_dout1\[28\]
+sram0_dout1\[27\]
+sram0_dout1\[26\]
+sram0_dout1\[25\]
+sram0_dout1\[24\]
+sram0_dout1\[23\]
+sram0_dout1\[22\]
+sram0_dout1\[21\]
+sram0_dout1\[20\]
+sram0_dout1\[19\]
+sram0_dout1\[18\]
+sram0_dout1\[17\]
+sram0_dout1\[16\]
+sram0_dout1\[15\]
+sram0_dout1\[14\]
+sram0_dout1\[13\]
+sram0_dout1\[12\]
+sram0_dout1\[11\]
+sram0_dout1\[10\]
+sram0_dout1\[9\]
+sram0_dout1\[8\]
+sram0_dout1\[7\]
+sram0_dout1\[6\]
+sram0_dout1\[5\]
+sram0_dout1\[4\]
+sram0_dout1\[3\]
+sram0_dout1\[2\]
+sram0_dout1\[1\]
+sram0_dout1\[0\]
+
+core0_uid\[1\]   0200 00 2
+core0_uid\[0\]   
+core0_imem_req_ack
+core0_imem_req
+core0_imem_cmd
+core0_imem_addr\[31\]
+core0_imem_addr\[30\]
+core0_imem_addr\[29\]
+core0_imem_addr\[28\]
+core0_imem_addr\[27\]
+core0_imem_addr\[26\]
+core0_imem_addr\[25\]
+core0_imem_addr\[24\]
+core0_imem_addr\[23\]
+core0_imem_addr\[22\]
+core0_imem_addr\[21\]
+core0_imem_addr\[20\]
+core0_imem_addr\[19\]
+core0_imem_addr\[18\]
+core0_imem_addr\[17\]
+core0_imem_addr\[16\]
+core0_imem_addr\[15\]
+core0_imem_addr\[14\]
+core0_imem_addr\[13\]
+core0_imem_addr\[12\]
+core0_imem_addr\[11\]
+core0_imem_addr\[10\]
+core0_imem_addr\[9\]
+core0_imem_addr\[8\]
+core0_imem_addr\[7\]
+core0_imem_addr\[6\]
+core0_imem_addr\[5\]
+core0_imem_addr\[4\]
+core0_imem_addr\[3\]
+core0_imem_addr\[2\]
+core0_imem_addr\[1\]
+core0_imem_addr\[0\]
+core0_imem_bl\[2\]
+core0_imem_bl\[1\]
+core0_imem_bl\[0\]
+core0_imem_rdata\[31\]
+core0_imem_rdata\[30\]
+core0_imem_rdata\[29\]
+core0_imem_rdata\[28\]
+core0_imem_rdata\[27\]
+core0_imem_rdata\[26\]
+core0_imem_rdata\[25\]
+core0_imem_rdata\[24\]
+core0_imem_rdata\[23\]
+core0_imem_rdata\[22\]
+core0_imem_rdata\[21\]
+core0_imem_rdata\[20\]
+core0_imem_rdata\[19\]
+core0_imem_rdata\[18\]
+core0_imem_rdata\[17\]
+core0_imem_rdata\[16\]
+core0_imem_rdata\[15\]
+core0_imem_rdata\[14\]
+core0_imem_rdata\[13\]
+core0_imem_rdata\[12\]
+core0_imem_rdata\[11\]
+core0_imem_rdata\[10\]
+core0_imem_rdata\[9\]
+core0_imem_rdata\[8\]
+core0_imem_rdata\[7\]
+core0_imem_rdata\[6\]
+core0_imem_rdata\[5\]
+core0_imem_rdata\[4\]
+core0_imem_rdata\[3\]
+core0_imem_rdata\[2\]
+core0_imem_rdata\[1\]
+core0_imem_rdata\[0\]
+core0_imem_resp\[1\]
+core0_imem_resp\[0\]
+
+core0_dmem_req_ack   0350 0 2
+core0_dmem_req
+core0_dmem_cmd
+core0_dmem_width\[1\]
+core0_dmem_width\[0\]
+core0_dmem_addr\[31\]
+core0_dmem_addr\[30\]
+core0_dmem_addr\[29\]
+core0_dmem_addr\[28\]
+core0_dmem_addr\[27\]
+core0_dmem_addr\[26\]
+core0_dmem_addr\[25\]
+core0_dmem_addr\[24\]
+core0_dmem_addr\[23\]
+core0_dmem_addr\[22\]
+core0_dmem_addr\[21\]
+core0_dmem_addr\[20\]
+core0_dmem_addr\[19\]
+core0_dmem_addr\[18\]
+core0_dmem_addr\[17\]
+core0_dmem_addr\[16\]
+core0_dmem_addr\[15\]
+core0_dmem_addr\[14\]
+core0_dmem_addr\[13\]
+core0_dmem_addr\[12\]
+core0_dmem_addr\[11\]
+core0_dmem_addr\[10\]
+core0_dmem_addr\[9\]
+core0_dmem_addr\[8\]
+core0_dmem_addr\[7\]
+core0_dmem_addr\[6\]
+core0_dmem_addr\[5\]
+core0_dmem_addr\[4\]
+core0_dmem_addr\[3\]
+core0_dmem_addr\[2\]
+core0_dmem_addr\[1\]
+core0_dmem_addr\[0\]
+core0_dmem_wdata\[31\]
+core0_dmem_wdata\[30\]
+core0_dmem_wdata\[29\]
+core0_dmem_wdata\[28\]
+core0_dmem_wdata\[27\]
+core0_dmem_wdata\[26\]
+core0_dmem_wdata\[25\]
+core0_dmem_wdata\[24\]
+core0_dmem_wdata\[23\]
+core0_dmem_wdata\[22\]
+core0_dmem_wdata\[21\]
+core0_dmem_wdata\[20\]
+core0_dmem_wdata\[19\]
+core0_dmem_wdata\[18\]
+core0_dmem_wdata\[17\]
+core0_dmem_wdata\[16\]
+core0_dmem_wdata\[15\]
+core0_dmem_wdata\[14\]
+core0_dmem_wdata\[13\]
+core0_dmem_wdata\[12\]
+core0_dmem_wdata\[11\]
+core0_dmem_wdata\[10\]
+core0_dmem_wdata\[9\]
+core0_dmem_wdata\[8\]
+core0_dmem_wdata\[7\]
+core0_dmem_wdata\[6\]
+core0_dmem_wdata\[5\]
+core0_dmem_wdata\[4\]
+core0_dmem_wdata\[3\]
+core0_dmem_wdata\[2\]
+core0_dmem_wdata\[1\]
+core0_dmem_wdata\[0\]
+core0_dmem_rdata\[31\]
+core0_dmem_rdata\[30\]
+core0_dmem_rdata\[29\]
+core0_dmem_rdata\[28\]
+core0_dmem_rdata\[27\]
+core0_dmem_rdata\[26\]
+core0_dmem_rdata\[25\]
+core0_dmem_rdata\[24\]
+core0_dmem_rdata\[23\]
+core0_dmem_rdata\[22\]
+core0_dmem_rdata\[21\]
+core0_dmem_rdata\[20\]
+core0_dmem_rdata\[19\]
+core0_dmem_rdata\[18\]
+core0_dmem_rdata\[17\]
+core0_dmem_rdata\[16\]
+core0_dmem_rdata\[15\]
+core0_dmem_rdata\[14\]
+core0_dmem_rdata\[13\]
+core0_dmem_rdata\[12\]
+core0_dmem_rdata\[11\]
+core0_dmem_rdata\[10\]
+core0_dmem_rdata\[9\]
+core0_dmem_rdata\[8\]
+core0_dmem_rdata\[7\]
+core0_dmem_rdata\[6\]
+core0_dmem_rdata\[5\]
+core0_dmem_rdata\[4\]
+core0_dmem_rdata\[3\]
+core0_dmem_rdata\[2\]
+core0_dmem_rdata\[1\]
+core0_dmem_rdata\[0\]
+core0_dmem_resp\[1\]
+core0_dmem_resp\[0\]
+
+core0_debug\[48\]    0500 0 2
+core0_debug\[47\]
+core0_debug\[46\]
+core0_debug\[45\]
+core0_debug\[44\]
+core0_debug\[43\]
+core0_debug\[42\]
+core0_debug\[41\]
+core0_debug\[40\]
+core0_debug\[39\]
+core0_debug\[38\]
+core0_debug\[37\]
+core0_debug\[36\]
+core0_debug\[35\]
+core0_debug\[34\]
+core0_debug\[33\]
+core0_debug\[32\]
+core0_debug\[31\]
+core0_debug\[30\]
+core0_debug\[29\]
+core0_debug\[28\]
+core0_debug\[27\]
+core0_debug\[26\]
+core0_debug\[25\]
+core0_debug\[24\]
+core0_debug\[23\]
+core0_debug\[22\]
+core0_debug\[21\]
+core0_debug\[20\]
+core0_debug\[19\]
+core0_debug\[18\]
+core0_debug\[17\]
+core0_debug\[16\]
+core0_debug\[15\]
+core0_debug\[14\]
+core0_debug\[13\]
+core0_debug\[12\]
+core0_debug\[11\]
+core0_debug\[10\]
+core0_debug\[9\]
+core0_debug\[8\]
+core0_debug\[7\]
+core0_debug\[6\]
+core0_debug\[5\]
+core0_debug\[4\]
+core0_debug\[3\]
+core0_debug\[2\]
+core0_debug\[1\]
+core0_debug\[0\]
+
+core0_timer_irq        0600 0 2
+core0_timer_val\[63\]
+core0_timer_val\[62\]
+core0_timer_val\[61\]
+core0_timer_val\[60\]
+core0_timer_val\[59\]
+core0_timer_val\[58\]
+core0_timer_val\[57\]
+core0_timer_val\[56\]
+core0_timer_val\[55\]
+core0_timer_val\[54\]
+core0_timer_val\[53\]
+core0_timer_val\[52\]
+core0_timer_val\[51\]
+core0_timer_val\[50\]
+core0_timer_val\[49\]
+core0_timer_val\[48\]
+core0_timer_val\[47\]
+core0_timer_val\[46\]
+core0_timer_val\[45\]
+core0_timer_val\[44\]
+core0_timer_val\[43\]
+core0_timer_val\[42\]
+core0_timer_val\[41\]
+core0_timer_val\[40\]
+core0_timer_val\[39\]
+core0_timer_val\[38\]
+core0_timer_val\[37\]
+core0_timer_val\[36\]
+core0_timer_val\[35\]
+core0_timer_val\[34\]
+core0_timer_val\[33\]
+core0_timer_val\[32\]
+core0_timer_val\[31\]
+core0_timer_val\[30\]
+core0_timer_val\[29\]
+core0_timer_val\[28\]
+core0_timer_val\[27\]
+core0_timer_val\[26\]
+core0_timer_val\[25\]
+core0_timer_val\[24\]
+core0_timer_val\[23\]
+core0_timer_val\[22\]
+core0_timer_val\[21\]
+core0_timer_val\[20\]
+core0_timer_val\[19\]
+core0_timer_val\[18\]
+core0_timer_val\[17\]
+core0_timer_val\[16\]
+core0_timer_val\[15\]
+core0_timer_val\[14\]
+core0_timer_val\[13\]
+core0_timer_val\[12\]
+core0_timer_val\[11\]
+core0_timer_val\[10\]
+core0_timer_val\[9\]
+core0_timer_val\[8\]
+core0_timer_val\[7\]
+core0_timer_val\[6\]
+core0_timer_val\[5\]
+core0_timer_val\[4\]
+core0_timer_val\[3\]
+core0_timer_val\[2\]
+core0_timer_val\[1\]
+core0_timer_val\[0\]
+
+core0_irq_lines\[15\]
+core0_irq_lines\[14\]
+core0_irq_lines\[13\]
+core0_irq_lines\[12\]
+core0_irq_lines\[11\]
+core0_irq_lines\[10\]
+core0_irq_lines\[9\]
+core0_irq_lines\[8\]
+core0_irq_lines\[7\]
+core0_irq_lines\[6\]
+core0_irq_lines\[5\]
+core0_irq_lines\[4\]
+core0_irq_lines\[3\]
+core0_irq_lines\[2\]
+core0_irq_lines\[1\]
+core0_irq_lines\[0\]
+core0_irq_soft
+
+
+#S
+core_icache_req_ack           000 0 2
+core_icache_req
+core_icache_cmd      
+core_icache_addr\[31\]     
+core_icache_addr\[30\]     
+core_icache_addr\[29\]     
+core_icache_addr\[28\]     
+core_icache_addr\[27\]     
+core_icache_addr\[26\]     
+core_icache_addr\[25\]     
+core_icache_addr\[24\]     
+core_icache_addr\[23\]     
+core_icache_addr\[22\]     
+core_icache_addr\[21\]     
+core_icache_addr\[20\]     
+core_icache_addr\[19\]     
+core_icache_addr\[18\]     
+core_icache_addr\[17\]     
+core_icache_addr\[16\]     
+core_icache_addr\[15\]     
+core_icache_addr\[14\]     
+core_icache_addr\[13\]     
+core_icache_addr\[12\]     
+core_icache_addr\[11\]     
+core_icache_addr\[10\]     
+core_icache_addr\[9\]     
+core_icache_addr\[8\]     
+core_icache_addr\[7\]     
+core_icache_addr\[6\]     
+core_icache_addr\[5\]     
+core_icache_addr\[4\]     
+core_icache_addr\[3\]     
+core_icache_addr\[2\]     
+core_icache_addr\[1\]     
+core_icache_addr\[0\]     
+core_icache_bl\[2\]      
+core_icache_bl\[1\]      
+core_icache_bl\[0\]      
+core_icache_width\[1\]    
+core_icache_width\[0\]    
+core_icache_rdata\[31\]    
+core_icache_rdata\[30\]    
+core_icache_rdata\[29\]    
+core_icache_rdata\[28\]    
+core_icache_rdata\[27\]    
+core_icache_rdata\[26\]    
+core_icache_rdata\[25\]    
+core_icache_rdata\[24\]    
+core_icache_rdata\[23\]    
+core_icache_rdata\[22\]    
+core_icache_rdata\[21\]    
+core_icache_rdata\[20\]    
+core_icache_rdata\[19\]    
+core_icache_rdata\[18\]    
+core_icache_rdata\[17\]    
+core_icache_rdata\[16\]    
+core_icache_rdata\[15\]    
+core_icache_rdata\[14\]    
+core_icache_rdata\[13\]    
+core_icache_rdata\[12\]    
+core_icache_rdata\[11\]    
+core_icache_rdata\[10\]    
+core_icache_rdata\[9\]    
+core_icache_rdata\[8\]    
+core_icache_rdata\[7\]    
+core_icache_rdata\[6\]    
+core_icache_rdata\[5\]    
+core_icache_rdata\[4\]    
+core_icache_rdata\[3\]    
+core_icache_rdata\[2\]    
+core_icache_rdata\[1\]    
+core_icache_rdata\[0\]    
+core_icache_resp\[1\]     
+core_icache_resp\[0\]     
+
+
+core_dcache_req_ack        100 0 2
+core_dcache_req      
+core_dcache_cmd      
+core_dcache_width\[1\]    
+core_dcache_width\[0\]    
+core_dcache_addr\[31\]     
+core_dcache_addr\[30\]     
+core_dcache_addr\[29\]     
+core_dcache_addr\[28\]     
+core_dcache_addr\[27\]     
+core_dcache_addr\[26\]     
+core_dcache_addr\[25\]     
+core_dcache_addr\[24\]     
+core_dcache_addr\[23\]     
+core_dcache_addr\[22\]     
+core_dcache_addr\[21\]     
+core_dcache_addr\[20\]     
+core_dcache_addr\[19\]     
+core_dcache_addr\[18\]     
+core_dcache_addr\[17\]     
+core_dcache_addr\[16\]     
+core_dcache_addr\[15\]     
+core_dcache_addr\[14\]     
+core_dcache_addr\[13\]     
+core_dcache_addr\[12\]     
+core_dcache_addr\[11\]     
+core_dcache_addr\[10\]     
+core_dcache_addr\[9\]     
+core_dcache_addr\[8\]     
+core_dcache_addr\[7\]     
+core_dcache_addr\[6\]     
+core_dcache_addr\[5\]     
+core_dcache_addr\[4\]     
+core_dcache_addr\[3\]     
+core_dcache_addr\[2\]     
+core_dcache_addr\[1\]     
+core_dcache_addr\[0\]     
+core_dcache_wdata\[31\]    
+core_dcache_wdata\[30\]    
+core_dcache_wdata\[29\]    
+core_dcache_wdata\[28\]    
+core_dcache_wdata\[27\]    
+core_dcache_wdata\[26\]    
+core_dcache_wdata\[25\]    
+core_dcache_wdata\[24\]    
+core_dcache_wdata\[23\]    
+core_dcache_wdata\[22\]    
+core_dcache_wdata\[21\]    
+core_dcache_wdata\[20\]    
+core_dcache_wdata\[19\]    
+core_dcache_wdata\[18\]    
+core_dcache_wdata\[17\]    
+core_dcache_wdata\[16\]    
+core_dcache_wdata\[15\]    
+core_dcache_wdata\[14\]    
+core_dcache_wdata\[13\]    
+core_dcache_wdata\[12\]    
+core_dcache_wdata\[11\]    
+core_dcache_wdata\[10\]    
+core_dcache_wdata\[9\]    
+core_dcache_wdata\[8\]    
+core_dcache_wdata\[7\]    
+core_dcache_wdata\[6\]    
+core_dcache_wdata\[5\]    
+core_dcache_wdata\[4\]    
+core_dcache_wdata\[3\]    
+core_dcache_wdata\[2\]    
+core_dcache_wdata\[1\]    
+core_dcache_wdata\[0\]    
+core_dcache_rdata\[31\]    
+core_dcache_rdata\[30\]    
+core_dcache_rdata\[29\]    
+core_dcache_rdata\[28\]    
+core_dcache_rdata\[27\]    
+core_dcache_rdata\[26\]    
+core_dcache_rdata\[25\]    
+core_dcache_rdata\[24\]    
+core_dcache_rdata\[23\]    
+core_dcache_rdata\[22\]    
+core_dcache_rdata\[21\]    
+core_dcache_rdata\[20\]    
+core_dcache_rdata\[19\]    
+core_dcache_rdata\[18\]    
+core_dcache_rdata\[17\]    
+core_dcache_rdata\[16\]    
+core_dcache_rdata\[15\]    
+core_dcache_rdata\[14\]    
+core_dcache_rdata\[13\]    
+core_dcache_rdata\[12\]    
+core_dcache_rdata\[11\]    
+core_dcache_rdata\[10\]    
+core_dcache_rdata\[9\]    
+core_dcache_rdata\[8\]    
+core_dcache_rdata\[7\]    
+core_dcache_rdata\[6\]    
+core_dcache_rdata\[5\]    
+core_dcache_rdata\[4\]    
+core_dcache_rdata\[3\]    
+core_dcache_rdata\[2\]    
+core_dcache_rdata\[1\]    
+core_dcache_rdata\[0\]    
+core_dcache_resp\[1\]     
+core_dcache_resp\[0\]     
+
+core_dmem_req_ack          0200 0 2
+core_dmem_req        
+core_dmem_cmd        
+core_dmem_width\[1\]      
+core_dmem_width\[0\]      
+core_dmem_addr\[31\]       
+core_dmem_addr\[30\]       
+core_dmem_addr\[29\]       
+core_dmem_addr\[28\]       
+core_dmem_addr\[27\]       
+core_dmem_addr\[26\]       
+core_dmem_addr\[25\]       
+core_dmem_addr\[24\]       
+core_dmem_addr\[23\]       
+core_dmem_addr\[22\]       
+core_dmem_addr\[21\]       
+core_dmem_addr\[20\]       
+core_dmem_addr\[19\]       
+core_dmem_addr\[18\]       
+core_dmem_addr\[17\]       
+core_dmem_addr\[16\]       
+core_dmem_addr\[15\]       
+core_dmem_addr\[14\]       
+core_dmem_addr\[13\]       
+core_dmem_addr\[12\]       
+core_dmem_addr\[11\]       
+core_dmem_addr\[10\]       
+core_dmem_addr\[9\]       
+core_dmem_addr\[8\]       
+core_dmem_addr\[7\]       
+core_dmem_addr\[6\]       
+core_dmem_addr\[5\]       
+core_dmem_addr\[4\]       
+core_dmem_addr\[3\]       
+core_dmem_addr\[2\]       
+core_dmem_addr\[1\]       
+core_dmem_addr\[0\]       
+core_dmem_wdata\[31\]      
+core_dmem_wdata\[30\]      
+core_dmem_wdata\[29\]      
+core_dmem_wdata\[28\]      
+core_dmem_wdata\[27\]      
+core_dmem_wdata\[26\]      
+core_dmem_wdata\[25\]      
+core_dmem_wdata\[24\]      
+core_dmem_wdata\[23\]      
+core_dmem_wdata\[22\]      
+core_dmem_wdata\[21\]      
+core_dmem_wdata\[20\]      
+core_dmem_wdata\[19\]      
+core_dmem_wdata\[18\]      
+core_dmem_wdata\[17\]      
+core_dmem_wdata\[16\]      
+core_dmem_wdata\[15\]      
+core_dmem_wdata\[14\]      
+core_dmem_wdata\[13\]      
+core_dmem_wdata\[12\]      
+core_dmem_wdata\[11\]      
+core_dmem_wdata\[10\]      
+core_dmem_wdata\[9\]      
+core_dmem_wdata\[8\]      
+core_dmem_wdata\[7\]      
+core_dmem_wdata\[6\]      
+core_dmem_wdata\[5\]      
+core_dmem_wdata\[4\]      
+core_dmem_wdata\[3\]      
+core_dmem_wdata\[2\]      
+core_dmem_wdata\[1\]      
+core_dmem_wdata\[0\]      
+core_dmem_rdata\[31\]      
+core_dmem_rdata\[30\]      
+core_dmem_rdata\[29\]      
+core_dmem_rdata\[28\]      
+core_dmem_rdata\[27\]      
+core_dmem_rdata\[26\]      
+core_dmem_rdata\[25\]      
+core_dmem_rdata\[24\]      
+core_dmem_rdata\[23\]      
+core_dmem_rdata\[22\]      
+core_dmem_rdata\[21\]      
+core_dmem_rdata\[20\]      
+core_dmem_rdata\[19\]      
+core_dmem_rdata\[18\]      
+core_dmem_rdata\[17\]      
+core_dmem_rdata\[16\]      
+core_dmem_rdata\[15\]      
+core_dmem_rdata\[14\]      
+core_dmem_rdata\[13\]      
+core_dmem_rdata\[12\]      
+core_dmem_rdata\[11\]      
+core_dmem_rdata\[10\]      
+core_dmem_rdata\[9\]      
+core_dmem_rdata\[8\]      
+core_dmem_rdata\[7\]      
+core_dmem_rdata\[6\]      
+core_dmem_rdata\[5\]      
+core_dmem_rdata\[4\]      
+core_dmem_rdata\[3\]      
+core_dmem_rdata\[2\]      
+core_dmem_rdata\[1\]      
+core_dmem_rdata\[0\]      
+core_dmem_resp\[1\]       
+core_dmem_resp\[0\]       
+
+cfg_dcache_force_flush
+cfg_sram_lphase\[1\]
+cfg_sram_lphase\[0\]
+
+
+riscv_debug\[63\]   300 0 2
+riscv_debug\[62\]
+riscv_debug\[61\]
+riscv_debug\[60\]
+riscv_debug\[59\]
+riscv_debug\[58\]
+riscv_debug\[57\]
+riscv_debug\[56\]
+riscv_debug\[55\]
+riscv_debug\[54\]
+riscv_debug\[53\]
+riscv_debug\[52\]
+riscv_debug\[51\]
+riscv_debug\[50\]
+riscv_debug\[49\]
+riscv_debug\[48\]
+riscv_debug\[47\]
+riscv_debug\[46\]
+riscv_debug\[45\]
+riscv_debug\[44\]
+riscv_debug\[43\]
+riscv_debug\[42\]
+riscv_debug\[41\]
+riscv_debug\[40\]
+riscv_debug\[39\]
+riscv_debug\[38\]
+riscv_debug\[37\]
+riscv_debug\[36\]
+riscv_debug\[35\]
+riscv_debug\[34\]
+riscv_debug\[33\]
+riscv_debug\[32\]
+riscv_debug\[31\]
+riscv_debug\[30\]
+riscv_debug\[29\]
+riscv_debug\[28\]
+riscv_debug\[27\]
+riscv_debug\[26\]
+riscv_debug\[25\]
+riscv_debug\[24\]
+riscv_debug\[23\]
+riscv_debug\[22\]
+riscv_debug\[21\]
+riscv_debug\[20\]
+riscv_debug\[19\]
+riscv_debug\[18\]
+riscv_debug\[17\]
+riscv_debug\[16\]
+riscv_debug\[15\]
+riscv_debug\[14\]
+riscv_debug\[13\]
+riscv_debug\[12\]
+riscv_debug\[11\]
+riscv_debug\[10\]
+riscv_debug\[9\]
+riscv_debug\[8\]
+riscv_debug\[7\]
+riscv_debug\[6\]
+riscv_debug\[5\]
+riscv_debug\[4\]
+riscv_debug\[3\]
+riscv_debug\[2\]
+riscv_debug\[1\]
+riscv_debug\[0\]
+
+core_irq_lines_i\[15\]
+core_irq_lines_i\[14\]
+core_irq_lines_i\[13\]
+core_irq_lines_i\[12\]
+core_irq_lines_i\[11\]
+core_irq_lines_i\[10\]
+core_irq_lines_i\[9\]
+core_irq_lines_i\[8\]
+core_irq_lines_i\[7\]
+core_irq_lines_i\[6\]
+core_irq_lines_i\[5\]
+core_irq_lines_i\[4\]
+core_irq_lines_i\[3\]
+core_irq_lines_i\[2\]
+core_irq_lines_i\[1\]
+core_irq_lines_i\[0\]
+core_irq_soft_i
+
+core_clk          
+rtc_clk
+pwrup_rst_n
+cpu_intf_rst_n
diff --git a/openlane/ycr_intf/base.sdc b/openlane/ycr_intf/base.sdc
new file mode 100644
index 0000000..2774794
--- /dev/null
+++ b/openlane/ycr_intf/base.sdc
@@ -0,0 +1,250 @@
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
+create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
+create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
+
+create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache mem clock0} [get_ports dcache_mem_clk0]
+create_generated_clock -name dcache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache mem clock1} [get_ports dcache_mem_clk1]
+create_generated_clock -name icache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache mem clock0} [get_ports icache_mem_clk0]
+create_generated_clock -name icache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache mem clock1} [get_ports icache_mem_clk1]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {core_clk dcache_mem_clk0 dcache_mem_clk1 icache_mem_clk0 icache_mem_clk1}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {wb_clk}] -comment {Async Clock group}
+
+#Assumed config are static
+set_false_path -from  [get_ports {cfg_dcache_force_flush}]
+set_false_path -from  [get_ports {cfg_dcache_pfet_dis}]
+set_false_path -from  [get_ports {cfg_icache_ntag_pfet_dis}]
+set_false_path -from  [get_ports {cfg_icache_pfet_dis}]
+set_false_path -from  [get_ports {cfg_cska_riscv[3]}]
+set_false_path -from  [get_ports {cfg_cska_riscv[2]}]
+set_false_path -from  [get_ports {cfg_cska_riscv[1]}]
+set_false_path -from  [get_ports {cfg_cska_riscv[0]}]
+set_false_path -from  [get_ports {cfg_sram_lphase[1]}]
+set_false_path -from  [get_ports {cfg_sram_lphase[0]}]
+
+#All reset has reset synchronization logic inside block ??
+set_false_path -from  [get_ports {cpu_intf_rst_n}]
+set_false_path -from  [get_ports {pwrup_rst_n}]
+set_false_path -from  [get_ports {wb_rst_n}]
+
+#CORE Instruction Memory Interface
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_resp[*]}]
+
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_bl[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_width[*]}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_bl[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_width[*]}]
+
+#Wishbone ICACHE I/F
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_sel_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_bl_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_bry_o}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_sel_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_bl_o[*]}]
+set_output_delay -max 2.5000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_bry_o}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_lack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_err_i}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_lack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_err_i}]
+
+
+
+# CORE Data Memory Interface
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_resp[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_width[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_wdata[*]}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_width[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_wdata[*]}]
+
+
+# Data memory interface from router to WB bridge
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_resp[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_width[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_wdata[*]}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_width[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_wdata[*]}]
+
+#WB Data Memory Interface
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_sel_o[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_dat_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_sel_o[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_err_i}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_err_i}]
+
+
+## ICACHE PORT-0 SRAM Memory I/F
+set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_csb0}]
+set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_web0}]
+set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_addr0[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_wmask0[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_din0[*]}]
+
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_csb0}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_web0}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_addr0[*]}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_wmask0[*]}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_din0[*]}]
+
+## ICACHE PORT-1 SRAM Memory I/F
+set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_csb1}]
+set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_addr1[*]}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_csb1}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_addr1[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_dout1[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_dout1[*]}]
+
+
+# Wishbone DCACHE I/F
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bl_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bry_o}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_cyc_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bl_o[*]}]
+set_output_delay -max 5.5000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bry_o}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_i[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_ack_i}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_lack_i}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_i[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_ack_i}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_lack_i}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
+
+## DCACHE PORT-0 SRAM I/F
+set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
+set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
+set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_din0[*]}]
+
+set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
+set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
+set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
+set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]
+set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_din0[*]}]
+
+set_input_delay  -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_dout0[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_dout0[*]}]
+
+
+## DCACHE PORT-1 SRAM I/F
+set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_csb1}]
+set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_addr1[*]}]
+
+set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_csb1}]
+set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_addr1[*]}]
+
+set_input_delay  -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_dout1[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_dout1[*]}]
+
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl
new file mode 100644
index 0000000..831ef54
--- /dev/null
+++ b/openlane/ycr_intf/config.tcl
@@ -0,0 +1,87 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(ROUTING_CORES) "6"
+
+set ::env(DESIGN_NAME) ycr_intf
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "wb_clk core_clk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+set ::env(LEC_ENABLE) 0
+
+set ::env(VERILOG_FILES) "\
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/clk_skew_adjust.gv                  \
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ctech_cells.sv                      \
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_top.sv            \
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv       \
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv       \
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_top.sv            \
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv        \
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ycr_async_wbb.sv                    \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_dmem_wb.sv                      \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_intf.sv                        \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_sram_mux.sv                   \
+        $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/async_fifo.sv                       \
+	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr_reset_cells.sv     \
+	"
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+## Floorplan
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 810 640 "
+set ::env(CELL_PAD) "6"
+
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
+set ::env(PL_TARGET_DENSITY) 0.37
+
+
+set ::env(RT_MAX_LAYER) {met4}
+#set ::env(GLB_RT_MAXLAYER) "5"
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 3
+
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
+
+#Need to cross-check why global timing opimization creating setup vio with hugh hold fix
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+
diff --git a/openlane/ycr_intf/pin_order.cfg b/openlane/ycr_intf/pin_order.cfg
new file mode 100644
index 0000000..6b93ea3
--- /dev/null
+++ b/openlane/ycr_intf/pin_order.cfg
@@ -0,0 +1,847 @@
+#BUS_SORT
+#MANUAL_PLACE
+
+#N
+
+core_icache_req_ack           000 0 2
+core_icache_req
+core_icache_cmd      
+core_icache_addr\[31\]     
+core_icache_addr\[30\]     
+core_icache_addr\[29\]     
+core_icache_addr\[28\]     
+core_icache_addr\[27\]     
+core_icache_addr\[26\]     
+core_icache_addr\[25\]     
+core_icache_addr\[24\]     
+core_icache_addr\[23\]     
+core_icache_addr\[22\]     
+core_icache_addr\[21\]     
+core_icache_addr\[20\]     
+core_icache_addr\[19\]     
+core_icache_addr\[18\]     
+core_icache_addr\[17\]     
+core_icache_addr\[16\]     
+core_icache_addr\[15\]     
+core_icache_addr\[14\]     
+core_icache_addr\[13\]     
+core_icache_addr\[12\]     
+core_icache_addr\[11\]     
+core_icache_addr\[10\]     
+core_icache_addr\[9\]     
+core_icache_addr\[8\]     
+core_icache_addr\[7\]     
+core_icache_addr\[6\]     
+core_icache_addr\[5\]     
+core_icache_addr\[4\]     
+core_icache_addr\[3\]     
+core_icache_addr\[2\]     
+core_icache_addr\[1\]     
+core_icache_addr\[0\]     
+core_icache_bl\[2\]      
+core_icache_bl\[1\]      
+core_icache_bl\[0\]      
+core_icache_width\[1\]    
+core_icache_width\[0\]    
+core_icache_rdata\[31\]    
+core_icache_rdata\[30\]    
+core_icache_rdata\[29\]    
+core_icache_rdata\[28\]    
+core_icache_rdata\[27\]    
+core_icache_rdata\[26\]    
+core_icache_rdata\[25\]    
+core_icache_rdata\[24\]    
+core_icache_rdata\[23\]    
+core_icache_rdata\[22\]    
+core_icache_rdata\[21\]    
+core_icache_rdata\[20\]    
+core_icache_rdata\[19\]    
+core_icache_rdata\[18\]    
+core_icache_rdata\[17\]    
+core_icache_rdata\[16\]    
+core_icache_rdata\[15\]    
+core_icache_rdata\[14\]    
+core_icache_rdata\[13\]    
+core_icache_rdata\[12\]    
+core_icache_rdata\[11\]    
+core_icache_rdata\[10\]    
+core_icache_rdata\[9\]    
+core_icache_rdata\[8\]    
+core_icache_rdata\[7\]    
+core_icache_rdata\[6\]    
+core_icache_rdata\[5\]    
+core_icache_rdata\[4\]    
+core_icache_rdata\[3\]    
+core_icache_rdata\[2\]    
+core_icache_rdata\[1\]    
+core_icache_rdata\[0\]    
+core_icache_resp\[1\]     
+core_icache_resp\[0\]     
+
+
+core_dcache_req_ack        100 0 2
+core_dcache_req      
+core_dcache_cmd      
+core_dcache_width\[1\]    
+core_dcache_width\[0\]    
+core_dcache_addr\[31\]     
+core_dcache_addr\[30\]     
+core_dcache_addr\[29\]     
+core_dcache_addr\[28\]     
+core_dcache_addr\[27\]     
+core_dcache_addr\[26\]     
+core_dcache_addr\[25\]     
+core_dcache_addr\[24\]     
+core_dcache_addr\[23\]     
+core_dcache_addr\[22\]     
+core_dcache_addr\[21\]     
+core_dcache_addr\[20\]     
+core_dcache_addr\[19\]     
+core_dcache_addr\[18\]     
+core_dcache_addr\[17\]     
+core_dcache_addr\[16\]     
+core_dcache_addr\[15\]     
+core_dcache_addr\[14\]     
+core_dcache_addr\[13\]     
+core_dcache_addr\[12\]     
+core_dcache_addr\[11\]     
+core_dcache_addr\[10\]     
+core_dcache_addr\[9\]     
+core_dcache_addr\[8\]     
+core_dcache_addr\[7\]     
+core_dcache_addr\[6\]     
+core_dcache_addr\[5\]     
+core_dcache_addr\[4\]     
+core_dcache_addr\[3\]     
+core_dcache_addr\[2\]     
+core_dcache_addr\[1\]     
+core_dcache_addr\[0\]     
+core_dcache_wdata\[31\]    
+core_dcache_wdata\[30\]    
+core_dcache_wdata\[29\]    
+core_dcache_wdata\[28\]    
+core_dcache_wdata\[27\]    
+core_dcache_wdata\[26\]    
+core_dcache_wdata\[25\]    
+core_dcache_wdata\[24\]    
+core_dcache_wdata\[23\]    
+core_dcache_wdata\[22\]    
+core_dcache_wdata\[21\]    
+core_dcache_wdata\[20\]    
+core_dcache_wdata\[19\]    
+core_dcache_wdata\[18\]    
+core_dcache_wdata\[17\]    
+core_dcache_wdata\[16\]    
+core_dcache_wdata\[15\]    
+core_dcache_wdata\[14\]    
+core_dcache_wdata\[13\]    
+core_dcache_wdata\[12\]    
+core_dcache_wdata\[11\]    
+core_dcache_wdata\[10\]    
+core_dcache_wdata\[9\]    
+core_dcache_wdata\[8\]    
+core_dcache_wdata\[7\]    
+core_dcache_wdata\[6\]    
+core_dcache_wdata\[5\]    
+core_dcache_wdata\[4\]    
+core_dcache_wdata\[3\]    
+core_dcache_wdata\[2\]    
+core_dcache_wdata\[1\]    
+core_dcache_wdata\[0\]    
+core_dcache_rdata\[31\]    
+core_dcache_rdata\[30\]    
+core_dcache_rdata\[29\]    
+core_dcache_rdata\[28\]    
+core_dcache_rdata\[27\]    
+core_dcache_rdata\[26\]    
+core_dcache_rdata\[25\]    
+core_dcache_rdata\[24\]    
+core_dcache_rdata\[23\]    
+core_dcache_rdata\[22\]    
+core_dcache_rdata\[21\]    
+core_dcache_rdata\[20\]    
+core_dcache_rdata\[19\]    
+core_dcache_rdata\[18\]    
+core_dcache_rdata\[17\]    
+core_dcache_rdata\[16\]    
+core_dcache_rdata\[15\]    
+core_dcache_rdata\[14\]    
+core_dcache_rdata\[13\]    
+core_dcache_rdata\[12\]    
+core_dcache_rdata\[11\]    
+core_dcache_rdata\[10\]    
+core_dcache_rdata\[9\]    
+core_dcache_rdata\[8\]    
+core_dcache_rdata\[7\]    
+core_dcache_rdata\[6\]    
+core_dcache_rdata\[5\]    
+core_dcache_rdata\[4\]    
+core_dcache_rdata\[3\]    
+core_dcache_rdata\[2\]    
+core_dcache_rdata\[1\]    
+core_dcache_rdata\[0\]    
+core_dcache_resp\[1\]     
+core_dcache_resp\[0\]     
+
+core_dmem_req_ack          0200 0 2
+core_dmem_req        
+core_dmem_cmd        
+core_dmem_width\[1\]      
+core_dmem_width\[0\]      
+core_dmem_addr\[31\]       
+core_dmem_addr\[30\]       
+core_dmem_addr\[29\]       
+core_dmem_addr\[28\]       
+core_dmem_addr\[27\]       
+core_dmem_addr\[26\]       
+core_dmem_addr\[25\]       
+core_dmem_addr\[24\]       
+core_dmem_addr\[23\]       
+core_dmem_addr\[22\]       
+core_dmem_addr\[21\]       
+core_dmem_addr\[20\]       
+core_dmem_addr\[19\]       
+core_dmem_addr\[18\]       
+core_dmem_addr\[17\]       
+core_dmem_addr\[16\]       
+core_dmem_addr\[15\]       
+core_dmem_addr\[14\]       
+core_dmem_addr\[13\]       
+core_dmem_addr\[12\]       
+core_dmem_addr\[11\]       
+core_dmem_addr\[10\]       
+core_dmem_addr\[9\]       
+core_dmem_addr\[8\]       
+core_dmem_addr\[7\]       
+core_dmem_addr\[6\]       
+core_dmem_addr\[5\]       
+core_dmem_addr\[4\]       
+core_dmem_addr\[3\]       
+core_dmem_addr\[2\]       
+core_dmem_addr\[1\]       
+core_dmem_addr\[0\]       
+core_dmem_wdata\[31\]      
+core_dmem_wdata\[30\]      
+core_dmem_wdata\[29\]      
+core_dmem_wdata\[28\]      
+core_dmem_wdata\[27\]      
+core_dmem_wdata\[26\]      
+core_dmem_wdata\[25\]      
+core_dmem_wdata\[24\]      
+core_dmem_wdata\[23\]      
+core_dmem_wdata\[22\]      
+core_dmem_wdata\[21\]      
+core_dmem_wdata\[20\]      
+core_dmem_wdata\[19\]      
+core_dmem_wdata\[18\]      
+core_dmem_wdata\[17\]      
+core_dmem_wdata\[16\]      
+core_dmem_wdata\[15\]      
+core_dmem_wdata\[14\]      
+core_dmem_wdata\[13\]      
+core_dmem_wdata\[12\]      
+core_dmem_wdata\[11\]      
+core_dmem_wdata\[10\]      
+core_dmem_wdata\[9\]      
+core_dmem_wdata\[8\]      
+core_dmem_wdata\[7\]      
+core_dmem_wdata\[6\]      
+core_dmem_wdata\[5\]      
+core_dmem_wdata\[4\]      
+core_dmem_wdata\[3\]      
+core_dmem_wdata\[2\]      
+core_dmem_wdata\[1\]      
+core_dmem_wdata\[0\]      
+core_dmem_rdata\[31\]      
+core_dmem_rdata\[30\]      
+core_dmem_rdata\[29\]      
+core_dmem_rdata\[28\]      
+core_dmem_rdata\[27\]      
+core_dmem_rdata\[26\]      
+core_dmem_rdata\[25\]      
+core_dmem_rdata\[24\]      
+core_dmem_rdata\[23\]      
+core_dmem_rdata\[22\]      
+core_dmem_rdata\[21\]      
+core_dmem_rdata\[20\]      
+core_dmem_rdata\[19\]      
+core_dmem_rdata\[18\]      
+core_dmem_rdata\[17\]      
+core_dmem_rdata\[16\]      
+core_dmem_rdata\[15\]      
+core_dmem_rdata\[14\]      
+core_dmem_rdata\[13\]      
+core_dmem_rdata\[12\]      
+core_dmem_rdata\[11\]      
+core_dmem_rdata\[10\]      
+core_dmem_rdata\[9\]      
+core_dmem_rdata\[8\]      
+core_dmem_rdata\[7\]      
+core_dmem_rdata\[6\]      
+core_dmem_rdata\[5\]      
+core_dmem_rdata\[4\]      
+core_dmem_rdata\[3\]      
+core_dmem_rdata\[2\]      
+core_dmem_rdata\[1\]      
+core_dmem_rdata\[0\]      
+core_dmem_resp\[1\]       
+core_dmem_resp\[0\]       
+
+cfg_dcache_force_flush
+
+#S
+icache_mem_clk0          
+icache_mem_csb0
+icache_mem_web0
+icache_mem_addr0\[0\]
+icache_mem_addr0\[1\]
+icache_mem_addr0\[2\]
+icache_mem_addr0\[3\]
+icache_mem_addr0\[4\]
+icache_mem_addr0\[5\]
+icache_mem_addr0\[6\]
+icache_mem_addr0\[7\]
+icache_mem_addr0\[8\]
+icache_mem_wmask0\[0\]
+icache_mem_wmask0\[1\]
+icache_mem_wmask0\[2\]
+icache_mem_wmask0\[3\]
+icache_mem_din0\[0\]
+icache_mem_din0\[1\]
+icache_mem_din0\[2\]
+icache_mem_din0\[3\]
+icache_mem_din0\[4\]
+icache_mem_din0\[5\]
+icache_mem_din0\[6\]
+icache_mem_din0\[7\]
+icache_mem_din0\[8\]
+icache_mem_din0\[9\]
+icache_mem_din0\[10\]
+icache_mem_din0\[11\]
+icache_mem_din0\[12\]
+icache_mem_din0\[13\]
+icache_mem_din0\[14\]
+icache_mem_din0\[15\]
+icache_mem_din0\[16\]
+icache_mem_din0\[17\]
+icache_mem_din0\[18\]
+icache_mem_din0\[19\]
+icache_mem_din0\[20\]
+icache_mem_din0\[21\]
+icache_mem_din0\[22\]
+icache_mem_din0\[23\]
+icache_mem_din0\[24\]
+icache_mem_din0\[25\]
+icache_mem_din0\[26\]
+icache_mem_din0\[27\]
+icache_mem_din0\[28\]
+icache_mem_din0\[29\]
+icache_mem_din0\[30\]
+icache_mem_din0\[31\]
+
+icache_mem_clk1          100 0 2
+icache_mem_csb1
+icache_mem_addr1\[8\]
+icache_mem_addr1\[7\]
+icache_mem_addr1\[6\]
+icache_mem_addr1\[5\]
+icache_mem_addr1\[4\]
+icache_mem_addr1\[3\]
+icache_mem_addr1\[2\]
+icache_mem_addr1\[1\]
+icache_mem_addr1\[0\]
+
+icache_mem_dout1\[0\]     150 0 2
+icache_mem_dout1\[1\]
+icache_mem_dout1\[2\]
+icache_mem_dout1\[3\]
+icache_mem_dout1\[4\]
+icache_mem_dout1\[5\]
+icache_mem_dout1\[6\]
+icache_mem_dout1\[7\]
+icache_mem_dout1\[8\]
+icache_mem_dout1\[9\]
+icache_mem_dout1\[10\]
+icache_mem_dout1\[11\]
+icache_mem_dout1\[12\]
+icache_mem_dout1\[13\]
+icache_mem_dout1\[14\]
+icache_mem_dout1\[15\]
+icache_mem_dout1\[16\]
+icache_mem_dout1\[17\]
+icache_mem_dout1\[18\]
+icache_mem_dout1\[19\]
+icache_mem_dout1\[20\]
+icache_mem_dout1\[21\]
+icache_mem_dout1\[22\]
+icache_mem_dout1\[23\]
+icache_mem_dout1\[24\]
+icache_mem_dout1\[25\]
+icache_mem_dout1\[26\]
+icache_mem_dout1\[27\]
+icache_mem_dout1\[28\]
+icache_mem_dout1\[29\]
+icache_mem_dout1\[30\]
+icache_mem_dout1\[31\]
+
+wb_rst_n                500 0
+pwrup_rst_n            
+core_clk
+cpu_intf_rst_n      
+
+#W
+dcache_mem_clk0            000 0 2
+dcache_mem_csb0
+dcache_mem_web0
+dcache_mem_addr0\[0\]
+dcache_mem_addr0\[1\]
+dcache_mem_addr0\[2\]
+dcache_mem_addr0\[3\]
+dcache_mem_addr0\[4\]
+dcache_mem_addr0\[5\]
+dcache_mem_addr0\[6\]
+dcache_mem_addr0\[7\]
+dcache_mem_addr0\[8\]
+dcache_mem_wmask0\[0\]
+dcache_mem_wmask0\[1\]
+dcache_mem_wmask0\[2\]
+dcache_mem_wmask0\[3\]
+dcache_mem_din0\[0\]
+dcache_mem_din0\[1\]
+dcache_mem_din0\[2\]
+dcache_mem_din0\[3\]
+dcache_mem_din0\[4\]
+dcache_mem_din0\[5\]
+dcache_mem_din0\[6\]
+dcache_mem_din0\[7\]
+dcache_mem_din0\[8\]
+dcache_mem_din0\[9\]
+dcache_mem_din0\[10\]
+dcache_mem_din0\[11\]
+dcache_mem_din0\[12\]
+dcache_mem_din0\[13\]
+dcache_mem_din0\[14\]
+dcache_mem_din0\[15\]
+dcache_mem_din0\[16\]
+dcache_mem_din0\[17\]
+dcache_mem_din0\[18\]
+dcache_mem_din0\[19\]
+dcache_mem_din0\[20\]
+dcache_mem_din0\[21\]
+dcache_mem_din0\[22\]
+dcache_mem_din0\[23\]
+dcache_mem_din0\[24\]
+dcache_mem_din0\[25\]
+dcache_mem_din0\[26\]
+dcache_mem_din0\[27\]
+dcache_mem_din0\[28\]
+dcache_mem_din0\[29\]
+dcache_mem_din0\[30\]
+dcache_mem_din0\[31\]
+
+
+dcache_mem_dout0\[0\]   100 0 2
+dcache_mem_dout0\[1\]
+dcache_mem_dout0\[2\]
+dcache_mem_dout0\[3\]
+dcache_mem_dout0\[4\]
+dcache_mem_dout0\[5\]
+dcache_mem_dout0\[6\]
+dcache_mem_dout0\[7\]
+dcache_mem_dout0\[8\]
+dcache_mem_dout0\[9\]
+dcache_mem_dout0\[10\]
+dcache_mem_dout0\[11\]
+dcache_mem_dout0\[12\]
+dcache_mem_dout0\[13\]
+dcache_mem_dout0\[14\]
+dcache_mem_dout0\[15\]
+dcache_mem_dout0\[16\]
+dcache_mem_dout0\[17\]
+dcache_mem_dout0\[18\]
+dcache_mem_dout0\[19\]
+dcache_mem_dout0\[20\]
+dcache_mem_dout0\[21\]
+dcache_mem_dout0\[22\]
+dcache_mem_dout0\[23\]
+dcache_mem_dout0\[24\]
+dcache_mem_dout0\[25\]
+dcache_mem_dout0\[26\]
+dcache_mem_dout0\[27\]
+dcache_mem_dout0\[28\]
+dcache_mem_dout0\[29\]
+dcache_mem_dout0\[30\]
+dcache_mem_dout0\[31\]
+
+dcache_mem_clk1         200 0 2
+dcache_mem_csb1
+dcache_mem_addr1\[8\]
+dcache_mem_addr1\[7\]
+dcache_mem_addr1\[6\]
+dcache_mem_addr1\[5\]
+dcache_mem_addr1\[4\]
+dcache_mem_addr1\[3\]
+dcache_mem_addr1\[2\]
+dcache_mem_addr1\[1\]
+dcache_mem_addr1\[0\]
+
+dcache_mem_dout1\[0\]   250 0 2
+dcache_mem_dout1\[1\]
+dcache_mem_dout1\[2\]
+dcache_mem_dout1\[3\]
+dcache_mem_dout1\[4\]
+dcache_mem_dout1\[5\]
+dcache_mem_dout1\[6\]
+dcache_mem_dout1\[7\]
+dcache_mem_dout1\[8\]
+dcache_mem_dout1\[9\]
+dcache_mem_dout1\[10\]
+dcache_mem_dout1\[11\]
+dcache_mem_dout1\[12\]
+dcache_mem_dout1\[13\]
+dcache_mem_dout1\[14\]
+dcache_mem_dout1\[15\]
+dcache_mem_dout1\[16\]
+dcache_mem_dout1\[17\]
+dcache_mem_dout1\[18\]
+dcache_mem_dout1\[19\]
+dcache_mem_dout1\[20\]
+dcache_mem_dout1\[21\]
+dcache_mem_dout1\[22\]
+dcache_mem_dout1\[23\]
+dcache_mem_dout1\[24\]
+dcache_mem_dout1\[25\]
+dcache_mem_dout1\[26\]
+dcache_mem_dout1\[27\]
+dcache_mem_dout1\[28\]
+dcache_mem_dout1\[29\]
+dcache_mem_dout1\[30\]
+dcache_mem_dout1\[31\]
+
+
+
+
+
+#E
+cfg_cska_riscv\[3\]     0000 0   2
+cfg_cska_riscv\[2\]
+cfg_cska_riscv\[1\]
+cfg_cska_riscv\[0\]
+wbd_clk_int
+wbd_clk_riscv
+wb_clk            
+
+wbd_dmem_stb_o         0100 0 2 
+wbd_dmem_we_o           
+wbd_dmem_adr_o\[31\]    
+wbd_dmem_adr_o\[30\]    
+wbd_dmem_adr_o\[29\]    
+wbd_dmem_adr_o\[28\]    
+wbd_dmem_adr_o\[27\]    
+wbd_dmem_adr_o\[26\]    
+wbd_dmem_adr_o\[25\]    
+wbd_dmem_adr_o\[24\]    
+wbd_dmem_adr_o\[23\]    
+wbd_dmem_adr_o\[22\]    
+wbd_dmem_adr_o\[21\]    
+wbd_dmem_adr_o\[20\]    
+wbd_dmem_adr_o\[19\]    
+wbd_dmem_adr_o\[18\]    
+wbd_dmem_adr_o\[17\]    
+wbd_dmem_adr_o\[16\]    
+wbd_dmem_adr_o\[15\]    
+wbd_dmem_adr_o\[14\]    
+wbd_dmem_adr_o\[13\]    
+wbd_dmem_adr_o\[12\]    
+wbd_dmem_adr_o\[11\]    
+wbd_dmem_adr_o\[10\]   
+wbd_dmem_adr_o\[9\]    
+wbd_dmem_adr_o\[8\]    
+wbd_dmem_adr_o\[7\]    
+wbd_dmem_adr_o\[6\]    
+wbd_dmem_adr_o\[5\]    
+wbd_dmem_adr_o\[4\]    
+wbd_dmem_adr_o\[3\]    
+wbd_dmem_adr_o\[2\]    
+wbd_dmem_adr_o\[1\]    
+wbd_dmem_adr_o\[0\]    
+wbd_dmem_sel_o\[3\]    
+wbd_dmem_sel_o\[2\]    
+wbd_dmem_sel_o\[1\]    
+wbd_dmem_sel_o\[0\]    
+wbd_dmem_dat_o\[31\]   
+wbd_dmem_dat_o\[30\]   
+wbd_dmem_dat_o\[29\]   
+wbd_dmem_dat_o\[28\]   
+wbd_dmem_dat_o\[27\]   
+wbd_dmem_dat_o\[26\]   
+wbd_dmem_dat_o\[25\]   
+wbd_dmem_dat_o\[24\]   
+wbd_dmem_dat_o\[23\]   
+wbd_dmem_dat_o\[22\]   
+wbd_dmem_dat_o\[21\]   
+wbd_dmem_dat_o\[20\]   
+wbd_dmem_dat_o\[19\]   
+wbd_dmem_dat_o\[18\]   
+wbd_dmem_dat_o\[17\]   
+wbd_dmem_dat_o\[16\]   
+wbd_dmem_dat_o\[15\]   
+wbd_dmem_dat_o\[14\]   
+wbd_dmem_dat_o\[13\]   
+wbd_dmem_dat_o\[12\]  
+wbd_dmem_dat_o\[11\]  
+wbd_dmem_dat_o\[10\]  
+wbd_dmem_dat_o\[9\]   
+wbd_dmem_dat_o\[8\]   
+wbd_dmem_dat_o\[7\]   
+wbd_dmem_dat_o\[6\]   
+wbd_dmem_dat_o\[5\]   
+wbd_dmem_dat_o\[4\]   
+wbd_dmem_dat_o\[3\]   
+wbd_dmem_dat_o\[2\]   
+wbd_dmem_dat_o\[1\]   
+wbd_dmem_dat_o\[0\]   
+wbd_dmem_dat_i\[31\]  
+wbd_dmem_dat_i\[30\]  
+wbd_dmem_dat_i\[29\]  
+wbd_dmem_dat_i\[28\]  
+wbd_dmem_dat_i\[27\]  
+wbd_dmem_dat_i\[26\]  
+wbd_dmem_dat_i\[25\]  
+wbd_dmem_dat_i\[24\]  
+wbd_dmem_dat_i\[23\]  
+wbd_dmem_dat_i\[22\]  
+wbd_dmem_dat_i\[21\]  
+wbd_dmem_dat_i\[20\]  
+wbd_dmem_dat_i\[19\]  
+wbd_dmem_dat_i\[18\]  
+wbd_dmem_dat_i\[17\]  
+wbd_dmem_dat_i\[16\]  
+wbd_dmem_dat_i\[15\]  
+wbd_dmem_dat_i\[14\]  
+wbd_dmem_dat_i\[13\]  
+wbd_dmem_dat_i\[12\]  
+wbd_dmem_dat_i\[11\]  
+wbd_dmem_dat_i\[10\]  
+wbd_dmem_dat_i\[9\]  
+wbd_dmem_dat_i\[8\]  
+wbd_dmem_dat_i\[7\]  
+wbd_dmem_dat_i\[6\]  
+wbd_dmem_dat_i\[5\]  
+wbd_dmem_dat_i\[4\]  
+wbd_dmem_dat_i\[3\]  
+wbd_dmem_dat_i\[2\]  
+wbd_dmem_dat_i\[1\]  
+wbd_dmem_dat_i\[0\]  
+wbd_dmem_ack_i       
+wbd_dmem_err_i       
+
+wb_dcache_stb_o       0300 0  2
+wb_dcache_we_o        
+wb_dcache_adr_o\[31\] 
+wb_dcache_adr_o\[30\] 
+wb_dcache_adr_o\[29\] 
+wb_dcache_adr_o\[28\] 
+wb_dcache_adr_o\[27\] 
+wb_dcache_adr_o\[26\] 
+wb_dcache_adr_o\[25\] 
+wb_dcache_adr_o\[24\] 
+wb_dcache_adr_o\[23\] 
+wb_dcache_adr_o\[22\] 
+wb_dcache_adr_o\[21\] 
+wb_dcache_adr_o\[20\] 
+wb_dcache_adr_o\[19\] 
+wb_dcache_adr_o\[18\] 
+wb_dcache_adr_o\[17\] 
+wb_dcache_adr_o\[16\] 
+wb_dcache_adr_o\[15\] 
+wb_dcache_adr_o\[14\] 
+wb_dcache_adr_o\[13\] 
+wb_dcache_adr_o\[12\] 
+wb_dcache_adr_o\[11\] 
+wb_dcache_adr_o\[10\] 
+wb_dcache_adr_o\[9\] 
+wb_dcache_adr_o\[8\] 
+wb_dcache_adr_o\[7\] 
+wb_dcache_adr_o\[6\] 
+wb_dcache_adr_o\[5\] 
+wb_dcache_adr_o\[4\] 
+wb_dcache_adr_o\[3\] 
+wb_dcache_adr_o\[2\] 
+wb_dcache_adr_o\[1\] 
+wb_dcache_adr_o\[0\] 
+wb_dcache_sel_o\[3\]  
+wb_dcache_sel_o\[2\]  
+wb_dcache_sel_o\[1\]  
+wb_dcache_sel_o\[0\]  
+wb_dcache_bl_o\[9\]  
+wb_dcache_bl_o\[8\]  
+wb_dcache_bl_o\[7\]  
+wb_dcache_bl_o\[6\]  
+wb_dcache_bl_o\[5\]  
+wb_dcache_bl_o\[4\]  
+wb_dcache_bl_o\[3\]  
+wb_dcache_bl_o\[2\]  
+wb_dcache_bl_o\[1\]  
+wb_dcache_bl_o\[0\]  
+wb_dcache_bry_o
+wb_dcache_dat_o\[31\] 
+wb_dcache_dat_o\[30\] 
+wb_dcache_dat_o\[29\] 
+wb_dcache_dat_o\[28\] 
+wb_dcache_dat_o\[27\] 
+wb_dcache_dat_o\[26\] 
+wb_dcache_dat_o\[25\] 
+wb_dcache_dat_o\[24\] 
+wb_dcache_dat_o\[23\] 
+wb_dcache_dat_o\[22\] 
+wb_dcache_dat_o\[21\] 
+wb_dcache_dat_o\[20\] 
+wb_dcache_dat_o\[19\] 
+wb_dcache_dat_o\[18\] 
+wb_dcache_dat_o\[17\] 
+wb_dcache_dat_o\[16\] 
+wb_dcache_dat_o\[15\] 
+wb_dcache_dat_o\[14\] 
+wb_dcache_dat_o\[13\] 
+wb_dcache_dat_o\[12\] 
+wb_dcache_dat_o\[11\] 
+wb_dcache_dat_o\[10\] 
+wb_dcache_dat_o\[9\]  
+wb_dcache_dat_o\[8\]  
+wb_dcache_dat_o\[7\]  
+wb_dcache_dat_o\[6\]  
+wb_dcache_dat_o\[5\]  
+wb_dcache_dat_o\[4\]  
+wb_dcache_dat_o\[3\]  
+wb_dcache_dat_o\[2\]  
+wb_dcache_dat_o\[1\]  
+wb_dcache_dat_o\[0\]  
+wb_dcache_dat_i\[31\] 
+wb_dcache_dat_i\[30\] 
+wb_dcache_dat_i\[29\] 
+wb_dcache_dat_i\[28\] 
+wb_dcache_dat_i\[27\] 
+wb_dcache_dat_i\[26\] 
+wb_dcache_dat_i\[25\] 
+wb_dcache_dat_i\[24\] 
+wb_dcache_dat_i\[23\] 
+wb_dcache_dat_i\[22\] 
+wb_dcache_dat_i\[21\] 
+wb_dcache_dat_i\[20\] 
+wb_dcache_dat_i\[19\] 
+wb_dcache_dat_i\[18\] 
+wb_dcache_dat_i\[17\] 
+wb_dcache_dat_i\[16\] 
+wb_dcache_dat_i\[15\] 
+wb_dcache_dat_i\[14\] 
+wb_dcache_dat_i\[13\] 
+wb_dcache_dat_i\[12\] 
+wb_dcache_dat_i\[11\] 
+wb_dcache_dat_i\[10\] 
+wb_dcache_dat_i\[9\] 
+wb_dcache_dat_i\[8\] 
+wb_dcache_dat_i\[7\] 
+wb_dcache_dat_i\[6\] 
+wb_dcache_dat_i\[5\] 
+wb_dcache_dat_i\[4\] 
+wb_dcache_dat_i\[3\] 
+wb_dcache_dat_i\[2\] 
+wb_dcache_dat_i\[1\] 
+wb_dcache_dat_i\[0\] 
+wb_dcache_ack_i      
+wb_dcache_lack_i      
+wb_dcache_err_i      
+wb_dcache_cyc_o       
+
+wb_icache_stb_o       500 0  2
+wb_icache_we_o        
+wb_icache_adr_o\[31\] 
+wb_icache_adr_o\[30\] 
+wb_icache_adr_o\[29\] 
+wb_icache_adr_o\[28\] 
+wb_icache_adr_o\[27\] 
+wb_icache_adr_o\[26\] 
+wb_icache_adr_o\[25\] 
+wb_icache_adr_o\[24\] 
+wb_icache_adr_o\[23\] 
+wb_icache_adr_o\[22\] 
+wb_icache_adr_o\[21\] 
+wb_icache_adr_o\[20\] 
+wb_icache_adr_o\[19\] 
+wb_icache_adr_o\[18\] 
+wb_icache_adr_o\[17\] 
+wb_icache_adr_o\[16\] 
+wb_icache_adr_o\[15\] 
+wb_icache_adr_o\[14\] 
+wb_icache_adr_o\[13\] 
+wb_icache_adr_o\[12\] 
+wb_icache_adr_o\[11\] 
+wb_icache_adr_o\[10\] 
+wb_icache_adr_o\[9\] 
+wb_icache_adr_o\[8\] 
+wb_icache_adr_o\[7\] 
+wb_icache_adr_o\[6\] 
+wb_icache_adr_o\[5\] 
+wb_icache_adr_o\[4\] 
+wb_icache_adr_o\[3\] 
+wb_icache_adr_o\[2\] 
+wb_icache_adr_o\[1\] 
+wb_icache_adr_o\[0\] 
+wb_icache_sel_o\[3\]  
+wb_icache_sel_o\[2\]  
+wb_icache_sel_o\[1\]  
+wb_icache_sel_o\[0\]  
+wb_icache_bl_o\[9\]  
+wb_icache_bl_o\[8\]  
+wb_icache_bl_o\[7\]  
+wb_icache_bl_o\[6\]  
+wb_icache_bl_o\[5\]  
+wb_icache_bl_o\[4\]  
+wb_icache_bl_o\[3\]  
+wb_icache_bl_o\[2\]  
+wb_icache_bl_o\[1\]  
+wb_icache_bl_o\[0\]  
+wb_icache_bry_o
+wb_icache_dat_i\[31\] 
+wb_icache_dat_i\[30\] 
+wb_icache_dat_i\[29\] 
+wb_icache_dat_i\[28\] 
+wb_icache_dat_i\[27\] 
+wb_icache_dat_i\[26\] 
+wb_icache_dat_i\[25\] 
+wb_icache_dat_i\[24\] 
+wb_icache_dat_i\[23\] 
+wb_icache_dat_i\[22\] 
+wb_icache_dat_i\[21\] 
+wb_icache_dat_i\[20\] 
+wb_icache_dat_i\[19\] 
+wb_icache_dat_i\[18\] 
+wb_icache_dat_i\[17\] 
+wb_icache_dat_i\[16\] 
+wb_icache_dat_i\[15\] 
+wb_icache_dat_i\[14\] 
+wb_icache_dat_i\[13\] 
+wb_icache_dat_i\[12\] 
+wb_icache_dat_i\[11\] 
+wb_icache_dat_i\[10\] 
+wb_icache_dat_i\[9\] 
+wb_icache_dat_i\[8\] 
+wb_icache_dat_i\[7\] 
+wb_icache_dat_i\[6\] 
+wb_icache_dat_i\[5\] 
+wb_icache_dat_i\[4\] 
+wb_icache_dat_i\[3\] 
+wb_icache_dat_i\[2\] 
+wb_icache_dat_i\[1\] 
+wb_icache_dat_i\[0\] 
+wb_icache_ack_i      
+wb_icache_lack_i      
+wb_icache_err_i      
+wb_icache_cyc_o
+
+cfg_icache_pfet_dis       
+cfg_icache_ntag_pfet_dis
+cfg_dcache_pfet_dis
+cfg_sram_lphase\[1\]
+cfg_sram_lphase\[0\]
diff --git a/openlane/yifive/base.sdc b/openlane/yifive/base.sdc
deleted file mode 100644
index d2293b6..0000000
--- a/openlane/yifive/base.sdc
+++ /dev/null
@@ -1,338 +0,0 @@
-###############################################################################
-# Timing Constraints
-###############################################################################
-create_clock -name core_clk -period 20.0000 [get_ports {core_clk}]
-create_clock -name core_clk_mclk -period 20.0000 [get_ports {core_clk_mclk}]
-create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
-create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
-
-create_generated_clock -name tcm_dffram_clk0 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {tcm clock0} [get_ports tcm_dffram_clk0]
-create_generated_clock -name tcm_dffram_clk1 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {tcm clock1} [get_ports tcm_dffram_clk1]
-
-create_generated_clock -name icache_dffram_clk0 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {icache clock0} [get_ports icache_dffram_clk0]
-create_generated_clock -name icache_dffram_clk1 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {icache clock1} [get_ports icache_dffram_clk1]
-
-create_generated_clock -name dcache_dffram_clk0 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {dcache clock0} [get_ports dcache_dffram_clk0]
-create_generated_clock -name dcache_dffram_clk1 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {dcache clock1} [get_ports dcache_dffram_clk1]
-
-set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
-set_clock_uncertainty -hold 0.2500 [all_clocks]
-
-set_propagated_clock [all_clocks]
-
-
-set ::env(SYNTH_TIMING_DERATE) 0.05
-puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
-set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
-set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
-
-set_clock_groups -name async_clock -asynchronous \
- -group [get_clocks {core_clk core_clk_mclk tcm_dffram_clk0 tcm_dffram_clk1 icache_dffram_clk0 icache_dffram_clk1 dcache_dffram_clk0 dcache_dffram_clk1} ]\
- -group [get_clocks {rtc_clk}]\
- -group [get_clocks {wb_clk}] -comment {Async Clock group}
-
-### ClkSkew Adjust
-set_case_analysis 0 [get_ports {cfg_cska_riscv[0]}]
-set_case_analysis 0 [get_ports {cfg_cska_riscv[1]}]
-set_case_analysis 0 [get_ports {cfg_cska_riscv[2]}]
-set_case_analysis 0 [get_ports {cfg_cska_riscv[3]}]
-
-
-set_max_delay   3.5 -from [get_ports {wbd_clk_int}]
-set_max_delay   2 -to   [get_ports {wbd_clk_riscv}]
-set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_riscv
-
-#TCM Memory
-set_input_delay -max 6.0000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_dout0[*]}]
-set_input_delay -min 3.0000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_dout0[*]}]
-
-set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_cs0}]
-set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_addr0[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_wmask0[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_din0[*]}]
-
-set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_cs0}]
-set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_addr0[*]}]
-set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_wmask0[*]}]
-set_output_delay -min -3.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_din0[*]}]
-
-# mem1
-set_input_delay -max 6.0000 -clock [get_clocks  {tcm_dffram_clk1}] -add_delay [get_ports  {tcm_dffram_dout1[*]}]
-set_input_delay -min 3.0000 -clock [get_clocks  {tcm_dffram_clk1}] -add_delay [get_ports  {tcm_dffram_dout1[*]}]
-
-set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports  {tcm_dffram_cs1}]
-set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports  {tcm_dffram_addr1[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports  {tcm_dffram_wmask1[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports  {tcm_dffram_din1[*]}]
-
-set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_cs1}]
-set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_addr1[*]}]
-set_output_delay -min -1.0000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_wmask1[*]}]
-set_output_delay -min -3.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_din1[*]}]
-
-#icache memory
-set_input_delay -max 6.0000 -clock [get_clocks   {icache_dffram_clk0}] -add_delay [get_ports  {icache_dffram_dout0[*]}]
-set_input_delay -min 3.0000 -clock [get_clocks   {icache_dffram_clk0}] -add_delay [get_ports  {icache_dffram_dout0[*]}]
-
-set_output_delay -max 4.5000 -clock [get_clocks  {icache_dffram_clk0}] -add_delay [get_ports  {icache_dffram_cs0}]
-set_output_delay -max 4.5000 -clock [get_clocks  {icache_dffram_clk0}] -add_delay [get_ports  {icache_dffram_addr0[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks  {icache_dffram_clk0}] -add_delay [get_ports  {icache_dffram_wmask0[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks  {icache_dffram_clk0}] -add_delay [get_ports  {icache_dffram_din0[*]}]
-
-set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports  {icache_dffram_cs0}]
-set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports  {icache_dffram_addr0[*]}]
-set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports  {icache_dffram_wmask0[*]}]
-set_output_delay -min -3.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports  {icache_dffram_din0[*]}]
-
-# mem1
-set_input_delay -max 6.0000 -clock [get_clocks   {icache_dffram_clk1}] -add_delay [get_ports  {icache_dffram_dout1[*]}]
-set_input_delay -min 3.0000 -clock [get_clocks   {icache_dffram_clk1}] -add_delay [get_ports  {icache_dffram_dout1[*]}]
-
-set_output_delay -max 4.5000 -clock [get_clocks  {icache_dffram_clk1}] -add_delay [get_ports  {icache_dffram_cs1}]
-set_output_delay -max 4.5000 -clock [get_clocks  {icache_dffram_clk1}] -add_delay [get_ports  {icache_dffram_addr1[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks  {icache_dffram_clk1}] -add_delay [get_ports  {icache_dffram_wmask1[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks  {icache_dffram_clk1}] -add_delay [get_ports  {icache_dffram_din1[*]}]
-
-set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports  {icache_dffram_cs1}]
-set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports  {icache_dffram_addr1[*]}]
-set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports  {icache_dffram_wmask1[*]}]
-set_output_delay -min -3.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports  {icache_dffram_din1[*]}]
-
-#dcache memory
-
-set_input_delay -max 6.0000 -clock [get_clocks   {dcache_dffram_clk0}] -add_delay [get_ports  {dcache_dffram_dout0[*]}]
-set_input_delay -min 3.0000 -clock [get_clocks   {dcache_dffram_clk0}] -add_delay [get_ports  {dcache_dffram_dout0[*]}]
-
-set_output_delay -max 4.5000 -clock [get_clocks  {dcache_dffram_clk0}] -add_delay [get_ports  {dcache_dffram_cs0}]
-set_output_delay -max 4.5000 -clock [get_clocks  {dcache_dffram_clk0}] -add_delay [get_ports  {dcache_dffram_addr0[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks  {dcache_dffram_clk0}] -add_delay [get_ports  {dcache_dffram_wmask0[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks  {dcache_dffram_clk0}] -add_delay [get_ports  {dcache_dffram_din0[*]}]
-
-set_output_delay -min -0.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports  {dcache_dffram_cs0}]
-set_output_delay -min -0.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports  {dcache_dffram_addr0[*]}]
-set_output_delay -min -2.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports  {dcache_dffram_wmask0[*]}]
-set_output_delay -min -3.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports  {dcache_dffram_din0[*]}]
-
-# mem1
-set_input_delay -max 6.0000 -clock [get_clocks   {dcache_dffram_clk1}] -add_delay [get_ports  {dcache_dffram_dout1[*]}]
-set_input_delay -min 3.0000 -clock [get_clocks   {dcache_dffram_clk1}] -add_delay [get_ports  {dcache_dffram_dout1[*]}]
-
-set_output_delay -max 4.5000 -clock [get_clocks  {dcache_dffram_clk1}] -add_delay [get_ports  {dcache_dffram_cs1}]
-set_output_delay -max 4.5000 -clock [get_clocks  {dcache_dffram_clk1}] -add_delay [get_ports  {dcache_dffram_addr1[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks  {dcache_dffram_clk1}] -add_delay [get_ports  {dcache_dffram_wmask1[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks  {dcache_dffram_clk1}] -add_delay [get_ports  {dcache_dffram_din1[*]}]
-
-set_output_delay -min -0.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports  {dcache_dffram_cs1}]
-set_output_delay -min -0.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports  {dcache_dffram_addr1[*]}]
-set_output_delay -min -2.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports  {dcache_dffram_wmask1[*]}]
-set_output_delay -min -3.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports  {dcache_dffram_din1[*]}]
-
-
-
-
-set_input_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_rst_n}]
-
-#Wishbone DMEM
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_err_i}]
-
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}]
-
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}]
-
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}]
-
-#Wishbone icache
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_lack_i}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_ack_i}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_dat_i[*]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_err_i}]
-
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_lack_i}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_ack_i}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_dat_i[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_dat_i[*]}]
-
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_adr_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_sel_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bl_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bry_o}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_stb_o}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_we_o}]
-
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_adr_o[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_sel_o[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bl_o[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bry_o}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_stb_o}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_we_o}]
-
-#Wishbone dcache
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_lack_i}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_ack_i}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_err_i}]
-
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_lack_i}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_ack_i}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}]
-
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_adr_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_sel_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bl_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bry_o}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_stb_o}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_we_o}]
-
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_adr_o[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_o[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_sel_o[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bl_o[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bry_o}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_stb_o}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_we_o}]
-
-set_false_path\
-    -from [get_ports {soft_irq}]
-set_false_path\
-    -to [list [get_ports {riscv_debug[0]}]\
-           [get_ports {riscv_debug[10]}]\
-           [get_ports {riscv_debug[11]}]\
-           [get_ports {riscv_debug[12]}]\
-           [get_ports {riscv_debug[13]}]\
-           [get_ports {riscv_debug[14]}]\
-           [get_ports {riscv_debug[15]}]\
-           [get_ports {riscv_debug[16]}]\
-           [get_ports {riscv_debug[17]}]\
-           [get_ports {riscv_debug[18]}]\
-           [get_ports {riscv_debug[19]}]\
-           [get_ports {riscv_debug[1]}]\
-           [get_ports {riscv_debug[20]}]\
-           [get_ports {riscv_debug[21]}]\
-           [get_ports {riscv_debug[22]}]\
-           [get_ports {riscv_debug[23]}]\
-           [get_ports {riscv_debug[24]}]\
-           [get_ports {riscv_debug[25]}]\
-           [get_ports {riscv_debug[26]}]\
-           [get_ports {riscv_debug[27]}]\
-           [get_ports {riscv_debug[28]}]\
-           [get_ports {riscv_debug[29]}]\
-           [get_ports {riscv_debug[2]}]\
-           [get_ports {riscv_debug[30]}]\
-           [get_ports {riscv_debug[31]}]\
-           [get_ports {riscv_debug[32]}]\
-           [get_ports {riscv_debug[33]}]\
-           [get_ports {riscv_debug[34]}]\
-           [get_ports {riscv_debug[35]}]\
-           [get_ports {riscv_debug[36]}]\
-           [get_ports {riscv_debug[37]}]\
-           [get_ports {riscv_debug[38]}]\
-           [get_ports {riscv_debug[39]}]\
-           [get_ports {riscv_debug[3]}]\
-           [get_ports {riscv_debug[40]}]\
-           [get_ports {riscv_debug[41]}]\
-           [get_ports {riscv_debug[42]}]\
-           [get_ports {riscv_debug[43]}]\
-           [get_ports {riscv_debug[44]}]\
-           [get_ports {riscv_debug[45]}]\
-           [get_ports {riscv_debug[46]}]\
-           [get_ports {riscv_debug[47]}]\
-           [get_ports {riscv_debug[48]}]\
-           [get_ports {riscv_debug[49]}]\
-           [get_ports {riscv_debug[4]}]\
-           [get_ports {riscv_debug[50]}]\
-           [get_ports {riscv_debug[51]}]\
-           [get_ports {riscv_debug[52]}]\
-           [get_ports {riscv_debug[53]}]\
-           [get_ports {riscv_debug[54]}]\
-           [get_ports {riscv_debug[55]}]\
-           [get_ports {riscv_debug[56]}]\
-           [get_ports {riscv_debug[57]}]\
-           [get_ports {riscv_debug[58]}]\
-           [get_ports {riscv_debug[59]}]\
-           [get_ports {riscv_debug[5]}]\
-           [get_ports {riscv_debug[60]}]\
-           [get_ports {riscv_debug[61]}]\
-           [get_ports {riscv_debug[62]}]\
-           [get_ports {riscv_debug[63]}]\
-           [get_ports {riscv_debug[6]}]\
-           [get_ports {riscv_debug[7]}]\
-           [get_ports {riscv_debug[8]}]\
-           [get_ports {riscv_debug[9]}]]
-
-set_false_path -from [get_ports {fuse_mhartid[0]}]
-set_false_path -from [get_ports {fuse_mhartid[10]}]
-set_false_path -from [get_ports {fuse_mhartid[11]}]
-set_false_path -from [get_ports {fuse_mhartid[12]}]
-set_false_path -from [get_ports {fuse_mhartid[13]}]
-set_false_path -from [get_ports {fuse_mhartid[14]}]
-set_false_path -from [get_ports {fuse_mhartid[15]}]
-set_false_path -from [get_ports {fuse_mhartid[16]}]
-set_false_path -from [get_ports {fuse_mhartid[17]}]
-set_false_path -from [get_ports {fuse_mhartid[18]}]
-set_false_path -from [get_ports {fuse_mhartid[19]}]
-set_false_path -from [get_ports {fuse_mhartid[1]}]
-set_false_path -from [get_ports {fuse_mhartid[20]}]
-set_false_path -from [get_ports {fuse_mhartid[21]}]
-set_false_path -from [get_ports {fuse_mhartid[22]}]
-set_false_path -from [get_ports {fuse_mhartid[23]}]
-set_false_path -from [get_ports {fuse_mhartid[24]}]
-set_false_path -from [get_ports {fuse_mhartid[25]}]
-set_false_path -from [get_ports {fuse_mhartid[26]}]
-set_false_path -from [get_ports {fuse_mhartid[27]}]
-set_false_path -from [get_ports {fuse_mhartid[28]}]
-set_false_path -from [get_ports {fuse_mhartid[29]}]
-set_false_path -from [get_ports {fuse_mhartid[2]}]
-set_false_path -from [get_ports {fuse_mhartid[30]}]
-set_false_path -from [get_ports {fuse_mhartid[31]}]
-set_false_path -from [get_ports {fuse_mhartid[3]}]
-set_false_path -from [get_ports {fuse_mhartid[4]}]
-set_false_path -from [get_ports {fuse_mhartid[5]}]
-set_false_path -from [get_ports {fuse_mhartid[6]}]
-set_false_path -from [get_ports {fuse_mhartid[7]}]
-set_false_path -from [get_ports {fuse_mhartid[8]}]
-set_false_path -from [get_ports {fuse_mhartid[9]}]
-set_false_path -from [get_ports {irq_lines[0]}]
-set_false_path -from [get_ports {irq_lines[10]}]
-set_false_path -from [get_ports {irq_lines[11]}]
-set_false_path -from [get_ports {irq_lines[12]}]
-set_false_path -from [get_ports {irq_lines[13]}]
-set_false_path -from [get_ports {irq_lines[14]}]
-set_false_path -from [get_ports {irq_lines[15]}]
-set_false_path -from [get_ports {irq_lines[1]}]
-set_false_path -from [get_ports {irq_lines[2]}]
-set_false_path -from [get_ports {irq_lines[3]}]
-set_false_path -from [get_ports {irq_lines[4]}]
-set_false_path -from [get_ports {irq_lines[5]}]
-set_false_path -from [get_ports {irq_lines[6]}]
-set_false_path -from [get_ports {irq_lines[7]}]
-set_false_path -from [get_ports {irq_lines[8]}]
-set_false_path -from [get_ports {irq_lines[9]}]
-set_false_path -from [get_ports {pwrup_rst_n}]
-set_false_path -from [get_ports {rst_n}]
-set_false_path -from [get_ports {soft_irq}]
-###############################################################################
-# Environment
-###############################################################################
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
-puts "\[INFO\]: Setting load to: $cap_load"
-set_load  $cap_load [all_outputs]
-
-###############################################################################
-# Design Rules
-###############################################################################
diff --git a/openlane/yifive/config.tcl b/openlane/yifive/config.tcl
deleted file mode 100755
index dc97db9..0000000
--- a/openlane/yifive/config.tcl
+++ /dev/null
@@ -1,149 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-# Global
-# ------
-
-set script_dir [file dirname [file normalize [info script]]]
-# Name
-set ::env(DESIGN_NAME) ycr1_top_wb
-
-set ::env(DESIGN_IS_CORE) "0"
-set ::env(FP_PDN_CORE_RING) "0"
-
-# Timing configuration
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "wb_clk core_clk"
-
-set ::env(SYNTH_MAX_FANOUT) 4
-
-## CTS BUFFER
-set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
-set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
-set ::env(CLOCK_BUFFER_FANOUT) "8"
-
-# Sources
-# -------
-
-# Local sources + no2usb sources
-set ::env(VERILOG_FILES) "\
-        $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_top.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_core_top.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_dm.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_tapc_synchronizer.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_clk_ctrl.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_scu.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_tapc.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_tapc_shift_reg.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_dmi.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr1_reset_cells.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_ifu.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_idu.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_exu.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_mprf.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_csr.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_ialu.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_mul.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_div.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_lsu.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_hdu.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_tdu.sv  \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_ipic.sv   \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_dmem_router.sv   \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_imem_router.sv   \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_icache_router.sv \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_dcache_router.sv \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_tcm_router.sv   \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_timer.sv   \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_top_wb.sv   \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_dmem_wb.sv   \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_imem_wb.sv   \
-	$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_intf.sv   \
-        $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_top.sv             \
-        $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv         \
-        $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv        \
-        $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv        \
-        $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_top.sv             \
-        $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ycr1_async_wbb.sv                    \
-        $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ycr1_arb.sv                          \
-        $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/sync_fifo.sv                         \
-        $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/async_fifo.sv                        \
-        $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ctech_cells.sv                       \
-	"
-
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
-#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ]
-
-set ::env(LEC_ENABLE) 0
-
-set ::env(VDD_PIN) [list {vccd1}]
-set ::env(GND_PIN) [list {vssd1}]
-
-
-# --------
-# Floorplanning
-# -------------
-
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) [list 0.0 0.0 815.0 1540.0]
-
-
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0
-
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
-
-
-set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.32"
-set ::env(FP_CORE_UTIL) "50"
-
-
-
-## Routing
-
-
-set ::env(GLB_RT_MAXLAYER) 5
-set ::env(RT_MAX_LAYER) {met4}
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-set ::env(DIODE_INSERTION_STRATEGY) 4
-
-
-set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
-set ::env(QUIT_ON_MAGIC_DRC) "1"
-set ::env(QUIT_ON_LVS_ERROR) "0"
-set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
-set ::env(QUIT_ON_SETUP_VIOLATIONS) "0"
-set ::env(QUIT_ON_HOLD_VIOLATIONS) "0"
-set ::env(QUIT_ON_ILLEGAL_OVERLAPS) "1"
-
-
-
-
-
-set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) "1"
-
-#Need to cross-check why global timing opimization creating setup vio with hugh hold fix
-set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1"
-
diff --git a/openlane/yifive/pdn.tcl b/openlane/yifive/pdn.tcl
deleted file mode 100644
index 1fe689b..0000000
--- a/openlane/yifive/pdn.tcl
+++ /dev/null
@@ -1,49 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-# Power nets
-set ::power_nets $::env(VDD_PIN)
-set ::ground_nets $::env(GND_PIN)
-
-set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
-
-pdngen::specify_grid stdcell {
-    name grid
-    rails {
-	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
-    }
-    straps {
-	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
-	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
-    }
-    connect {{met1 met4} {met4 met5}}
-}
-
-pdngen::specify_grid macro {
-    power_pins "VPWR"
-    ground_pins "VGND"
-    blockages "li1 met1 met2 met3 met4"
-    straps { 
-    } 
-    connect {{met4_PIN_ver met5}}
-}
-
-set ::halo 5
-
-# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
-set ::rails_start_with "POWER" ;
-
-# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
-set ::stripes_start_with "POWER" ;
diff --git a/openlane/yifive/pin_order.cfg b/openlane/yifive/pin_order.cfg
deleted file mode 100644
index c2fb874..0000000
--- a/openlane/yifive/pin_order.cfg
+++ /dev/null
@@ -1,896 +0,0 @@
-#BUS_SORT
-
-#MANUAL_PLACE
-
-
-#E
-soft_irq            0500 0 2
-irq_lines\[15\]     
-irq_lines\[14\]     
-irq_lines\[13\]     
-irq_lines\[12\]     
-irq_lines\[11\]     
-irq_lines\[10\]     
-irq_lines\[9\]     
-irq_lines\[8\]     
-irq_lines\[7\]     
-irq_lines\[6\]     
-irq_lines\[5\]     
-irq_lines\[4\]     
-irq_lines\[3\]     
-irq_lines\[2\]     
-irq_lines\[1\]     
-irq_lines\[0\]   
-cfg_cache_ctrl\[2\]  
-cfg_cache_ctrl\[1\]  
-cfg_cache_ctrl\[0\]  
-
-cfg_cska_riscv\[3\]    
-cfg_cska_riscv\[2\]
-cfg_cska_riscv\[1\]
-cfg_cska_riscv\[0\]
-wbd_clk_int
-wbd_clk_riscv
-wb_clk            
-
-
-wbd_dmem_stb_o          0700 0
-wbd_dmem_we_o           
-wbd_dmem_adr_o\[31\]    
-wbd_dmem_adr_o\[30\]    
-wbd_dmem_adr_o\[29\]    
-wbd_dmem_adr_o\[28\]    
-wbd_dmem_adr_o\[27\]    
-wbd_dmem_adr_o\[26\]    
-wbd_dmem_adr_o\[25\]    
-wbd_dmem_adr_o\[24\]    
-wbd_dmem_adr_o\[23\]    
-wbd_dmem_adr_o\[22\]    
-wbd_dmem_adr_o\[21\]    
-wbd_dmem_adr_o\[20\]    
-wbd_dmem_adr_o\[19\]    
-wbd_dmem_adr_o\[18\]    
-wbd_dmem_adr_o\[17\]    
-wbd_dmem_adr_o\[16\]    
-wbd_dmem_adr_o\[15\]    
-wbd_dmem_adr_o\[14\]    
-wbd_dmem_adr_o\[13\]    
-wbd_dmem_adr_o\[12\]    
-wbd_dmem_adr_o\[11\]    
-wbd_dmem_adr_o\[10\]   
-wbd_dmem_adr_o\[9\]    
-wbd_dmem_adr_o\[8\]    
-wbd_dmem_adr_o\[7\]    
-wbd_dmem_adr_o\[6\]    
-wbd_dmem_adr_o\[5\]    
-wbd_dmem_adr_o\[4\]    
-wbd_dmem_adr_o\[3\]    
-wbd_dmem_adr_o\[2\]    
-wbd_dmem_adr_o\[1\]    
-wbd_dmem_adr_o\[0\]    
-wbd_dmem_sel_o\[3\]    
-wbd_dmem_sel_o\[2\]    
-wbd_dmem_sel_o\[1\]    
-wbd_dmem_sel_o\[0\]    
-wbd_dmem_dat_o\[31\]   
-wbd_dmem_dat_o\[30\]   
-wbd_dmem_dat_o\[29\]   
-wbd_dmem_dat_o\[28\]   
-wbd_dmem_dat_o\[27\]   
-wbd_dmem_dat_o\[26\]   
-wbd_dmem_dat_o\[25\]   
-wbd_dmem_dat_o\[24\]   
-wbd_dmem_dat_o\[23\]   
-wbd_dmem_dat_o\[22\]   
-wbd_dmem_dat_o\[21\]   
-wbd_dmem_dat_o\[20\]   
-wbd_dmem_dat_o\[19\]   
-wbd_dmem_dat_o\[18\]   
-wbd_dmem_dat_o\[17\]   
-wbd_dmem_dat_o\[16\]   
-wbd_dmem_dat_o\[15\]   
-wbd_dmem_dat_o\[14\]   
-wbd_dmem_dat_o\[13\]   
-wbd_dmem_dat_o\[12\]  
-wbd_dmem_dat_o\[11\]  
-wbd_dmem_dat_o\[10\]  
-wbd_dmem_dat_o\[9\]   
-wbd_dmem_dat_o\[8\]   
-wbd_dmem_dat_o\[7\]   
-wbd_dmem_dat_o\[6\]   
-wbd_dmem_dat_o\[5\]   
-wbd_dmem_dat_o\[4\]   
-wbd_dmem_dat_o\[3\]   
-wbd_dmem_dat_o\[2\]   
-wbd_dmem_dat_o\[1\]   
-wbd_dmem_dat_o\[0\]   
-wbd_dmem_dat_i\[31\]  
-wbd_dmem_dat_i\[30\]  
-wbd_dmem_dat_i\[29\]  
-wbd_dmem_dat_i\[28\]  
-wbd_dmem_dat_i\[27\]  
-wbd_dmem_dat_i\[26\]  
-wbd_dmem_dat_i\[25\]  
-wbd_dmem_dat_i\[24\]  
-wbd_dmem_dat_i\[23\]  
-wbd_dmem_dat_i\[22\]  
-wbd_dmem_dat_i\[21\]  
-wbd_dmem_dat_i\[20\]  
-wbd_dmem_dat_i\[19\]  
-wbd_dmem_dat_i\[18\]  
-wbd_dmem_dat_i\[17\]  
-wbd_dmem_dat_i\[16\]  
-wbd_dmem_dat_i\[15\]  
-wbd_dmem_dat_i\[14\]  
-wbd_dmem_dat_i\[13\]  
-wbd_dmem_dat_i\[12\]  
-wbd_dmem_dat_i\[11\]  
-wbd_dmem_dat_i\[10\]  
-wbd_dmem_dat_i\[9\]  
-wbd_dmem_dat_i\[8\]  
-wbd_dmem_dat_i\[7\]  
-wbd_dmem_dat_i\[6\]  
-wbd_dmem_dat_i\[5\]  
-wbd_dmem_dat_i\[4\]  
-wbd_dmem_dat_i\[3\]  
-wbd_dmem_dat_i\[2\]  
-wbd_dmem_dat_i\[1\]  
-wbd_dmem_dat_i\[0\]  
-wbd_dmem_ack_i       
-wbd_dmem_err_i       
-
-wb_dcache_stb_o       0900 0  2
-wb_dcache_we_o        
-wb_dcache_adr_o\[31\] 
-wb_dcache_adr_o\[30\] 
-wb_dcache_adr_o\[29\] 
-wb_dcache_adr_o\[28\] 
-wb_dcache_adr_o\[27\] 
-wb_dcache_adr_o\[26\] 
-wb_dcache_adr_o\[25\] 
-wb_dcache_adr_o\[24\] 
-wb_dcache_adr_o\[23\] 
-wb_dcache_adr_o\[22\] 
-wb_dcache_adr_o\[21\] 
-wb_dcache_adr_o\[20\] 
-wb_dcache_adr_o\[19\] 
-wb_dcache_adr_o\[18\] 
-wb_dcache_adr_o\[17\] 
-wb_dcache_adr_o\[16\] 
-wb_dcache_adr_o\[15\] 
-wb_dcache_adr_o\[14\] 
-wb_dcache_adr_o\[13\] 
-wb_dcache_adr_o\[12\] 
-wb_dcache_adr_o\[11\] 
-wb_dcache_adr_o\[10\] 
-wb_dcache_adr_o\[9\] 
-wb_dcache_adr_o\[8\] 
-wb_dcache_adr_o\[7\] 
-wb_dcache_adr_o\[6\] 
-wb_dcache_adr_o\[5\] 
-wb_dcache_adr_o\[4\] 
-wb_dcache_adr_o\[3\] 
-wb_dcache_adr_o\[2\] 
-wb_dcache_adr_o\[1\] 
-wb_dcache_adr_o\[0\] 
-wb_dcache_sel_o\[3\]  
-wb_dcache_sel_o\[2\]  
-wb_dcache_sel_o\[1\]  
-wb_dcache_sel_o\[0\]  
-wb_dcache_bl_o\[9\]  
-wb_dcache_bl_o\[8\]  
-wb_dcache_bl_o\[7\]  
-wb_dcache_bl_o\[6\]  
-wb_dcache_bl_o\[5\]  
-wb_dcache_bl_o\[4\]  
-wb_dcache_bl_o\[3\]  
-wb_dcache_bl_o\[2\]  
-wb_dcache_bl_o\[1\]  
-wb_dcache_bl_o\[0\]  
-wb_dcache_bry_o
-wb_dcache_dat_o\[31\] 
-wb_dcache_dat_o\[30\] 
-wb_dcache_dat_o\[29\] 
-wb_dcache_dat_o\[28\] 
-wb_dcache_dat_o\[27\] 
-wb_dcache_dat_o\[26\] 
-wb_dcache_dat_o\[25\] 
-wb_dcache_dat_o\[24\] 
-wb_dcache_dat_o\[23\] 
-wb_dcache_dat_o\[22\] 
-wb_dcache_dat_o\[21\] 
-wb_dcache_dat_o\[20\] 
-wb_dcache_dat_o\[19\] 
-wb_dcache_dat_o\[18\] 
-wb_dcache_dat_o\[17\] 
-wb_dcache_dat_o\[16\] 
-wb_dcache_dat_o\[15\] 
-wb_dcache_dat_o\[14\] 
-wb_dcache_dat_o\[13\] 
-wb_dcache_dat_o\[12\] 
-wb_dcache_dat_o\[11\] 
-wb_dcache_dat_o\[10\] 
-wb_dcache_dat_o\[9\]  
-wb_dcache_dat_o\[8\]  
-wb_dcache_dat_o\[7\]  
-wb_dcache_dat_o\[6\]  
-wb_dcache_dat_o\[5\]  
-wb_dcache_dat_o\[4\]  
-wb_dcache_dat_o\[3\]  
-wb_dcache_dat_o\[2\]  
-wb_dcache_dat_o\[1\]  
-wb_dcache_dat_o\[0\]  
-wb_dcache_dat_i\[31\] 
-wb_dcache_dat_i\[30\] 
-wb_dcache_dat_i\[29\] 
-wb_dcache_dat_i\[28\] 
-wb_dcache_dat_i\[27\] 
-wb_dcache_dat_i\[26\] 
-wb_dcache_dat_i\[25\] 
-wb_dcache_dat_i\[24\] 
-wb_dcache_dat_i\[23\] 
-wb_dcache_dat_i\[22\] 
-wb_dcache_dat_i\[21\] 
-wb_dcache_dat_i\[20\] 
-wb_dcache_dat_i\[19\] 
-wb_dcache_dat_i\[18\] 
-wb_dcache_dat_i\[17\] 
-wb_dcache_dat_i\[16\] 
-wb_dcache_dat_i\[15\] 
-wb_dcache_dat_i\[14\] 
-wb_dcache_dat_i\[13\] 
-wb_dcache_dat_i\[12\] 
-wb_dcache_dat_i\[11\] 
-wb_dcache_dat_i\[10\] 
-wb_dcache_dat_i\[9\] 
-wb_dcache_dat_i\[8\] 
-wb_dcache_dat_i\[7\] 
-wb_dcache_dat_i\[6\] 
-wb_dcache_dat_i\[5\] 
-wb_dcache_dat_i\[4\] 
-wb_dcache_dat_i\[3\] 
-wb_dcache_dat_i\[2\] 
-wb_dcache_dat_i\[1\] 
-wb_dcache_dat_i\[0\] 
-wb_dcache_ack_i      
-wb_dcache_lack_i      
-wb_dcache_err_i      
-
-wb_icache_stb_o       1100 0  2
-wb_icache_we_o        
-wb_icache_adr_o\[31\] 
-wb_icache_adr_o\[30\] 
-wb_icache_adr_o\[29\] 
-wb_icache_adr_o\[28\] 
-wb_icache_adr_o\[27\] 
-wb_icache_adr_o\[26\] 
-wb_icache_adr_o\[25\] 
-wb_icache_adr_o\[24\] 
-wb_icache_adr_o\[23\] 
-wb_icache_adr_o\[22\] 
-wb_icache_adr_o\[21\] 
-wb_icache_adr_o\[20\] 
-wb_icache_adr_o\[19\] 
-wb_icache_adr_o\[18\] 
-wb_icache_adr_o\[17\] 
-wb_icache_adr_o\[16\] 
-wb_icache_adr_o\[15\] 
-wb_icache_adr_o\[14\] 
-wb_icache_adr_o\[13\] 
-wb_icache_adr_o\[12\] 
-wb_icache_adr_o\[11\] 
-wb_icache_adr_o\[10\] 
-wb_icache_adr_o\[9\] 
-wb_icache_adr_o\[8\] 
-wb_icache_adr_o\[7\] 
-wb_icache_adr_o\[6\] 
-wb_icache_adr_o\[5\] 
-wb_icache_adr_o\[4\] 
-wb_icache_adr_o\[3\] 
-wb_icache_adr_o\[2\] 
-wb_icache_adr_o\[1\] 
-wb_icache_adr_o\[0\] 
-wb_icache_sel_o\[3\]  
-wb_icache_sel_o\[2\]  
-wb_icache_sel_o\[1\]  
-wb_icache_sel_o\[0\]  
-wb_icache_bl_o\[9\]  
-wb_icache_bl_o\[8\]  
-wb_icache_bl_o\[7\]  
-wb_icache_bl_o\[6\]  
-wb_icache_bl_o\[5\]  
-wb_icache_bl_o\[4\]  
-wb_icache_bl_o\[3\]  
-wb_icache_bl_o\[2\]  
-wb_icache_bl_o\[1\]  
-wb_icache_bl_o\[0\]  
-wb_icache_bry_o
-wb_icache_dat_i\[31\] 
-wb_icache_dat_i\[30\] 
-wb_icache_dat_i\[29\] 
-wb_icache_dat_i\[28\] 
-wb_icache_dat_i\[27\] 
-wb_icache_dat_i\[26\] 
-wb_icache_dat_i\[25\] 
-wb_icache_dat_i\[24\] 
-wb_icache_dat_i\[23\] 
-wb_icache_dat_i\[22\] 
-wb_icache_dat_i\[21\] 
-wb_icache_dat_i\[20\] 
-wb_icache_dat_i\[19\] 
-wb_icache_dat_i\[18\] 
-wb_icache_dat_i\[17\] 
-wb_icache_dat_i\[16\] 
-wb_icache_dat_i\[15\] 
-wb_icache_dat_i\[14\] 
-wb_icache_dat_i\[13\] 
-wb_icache_dat_i\[12\] 
-wb_icache_dat_i\[11\] 
-wb_icache_dat_i\[10\] 
-wb_icache_dat_i\[9\] 
-wb_icache_dat_i\[8\] 
-wb_icache_dat_i\[7\] 
-wb_icache_dat_i\[6\] 
-wb_icache_dat_i\[5\] 
-wb_icache_dat_i\[4\] 
-wb_icache_dat_i\[3\] 
-wb_icache_dat_i\[2\] 
-wb_icache_dat_i\[1\] 
-wb_icache_dat_i\[0\] 
-wb_icache_ack_i      
-wb_icache_lack_i      
-wb_icache_err_i      
-
-#W
-
-tcm_dffram_clk0          0000 0 2
-tcm_dffram_cs0
-tcm_dffram_addr0\[7\]
-tcm_dffram_addr0\[6\]
-tcm_dffram_addr0\[5\]
-tcm_dffram_addr0\[4\]
-tcm_dffram_addr0\[3\]
-tcm_dffram_addr0\[2\]
-tcm_dffram_addr0\[1\]
-tcm_dffram_addr0\[0\]
-tcm_dffram_wmask0\[3\]
-tcm_dffram_wmask0\[2\]
-tcm_dffram_wmask0\[1\]
-tcm_dffram_wmask0\[0\]
-tcm_dffram_din0\[31\]
-tcm_dffram_din0\[30\]
-tcm_dffram_din0\[29\]
-tcm_dffram_din0\[28\]
-tcm_dffram_din0\[27\]
-tcm_dffram_din0\[26\]
-tcm_dffram_din0\[25\]
-tcm_dffram_din0\[24\]
-tcm_dffram_din0\[23\]
-tcm_dffram_din0\[22\]
-tcm_dffram_din0\[21\]
-tcm_dffram_din0\[20\]
-tcm_dffram_din0\[19\]
-tcm_dffram_din0\[18\]
-tcm_dffram_din0\[17\]
-tcm_dffram_din0\[16\]
-tcm_dffram_din0\[15\]
-tcm_dffram_din0\[14\]
-tcm_dffram_din0\[13\]
-tcm_dffram_din0\[12\]
-tcm_dffram_din0\[11\]
-tcm_dffram_din0\[10\]
-tcm_dffram_din0\[9\]
-tcm_dffram_din0\[8\]
-tcm_dffram_din0\[7\]
-tcm_dffram_din0\[6\]
-tcm_dffram_din0\[5\]
-tcm_dffram_din0\[4\]
-tcm_dffram_din0\[3\]
-tcm_dffram_din0\[2\]
-tcm_dffram_din0\[1\]
-tcm_dffram_din0\[0\]
-
-tcm_dffram_dout0\[31\]  750 0 2
-tcm_dffram_dout0\[30\]
-tcm_dffram_dout0\[29\]
-tcm_dffram_dout0\[28\]
-tcm_dffram_dout0\[27\]
-tcm_dffram_dout0\[26\]
-tcm_dffram_dout0\[25\]
-tcm_dffram_dout0\[24\]
-tcm_dffram_dout0\[23\]
-tcm_dffram_dout0\[22\]
-tcm_dffram_dout0\[21\]
-tcm_dffram_dout0\[20\]
-tcm_dffram_dout0\[19\]
-tcm_dffram_dout0\[18\]
-tcm_dffram_dout0\[17\]
-tcm_dffram_dout0\[16\]
-tcm_dffram_dout0\[15\]
-tcm_dffram_dout0\[14\]
-tcm_dffram_dout0\[13\]
-tcm_dffram_dout0\[12\]
-tcm_dffram_dout0\[11\]
-tcm_dffram_dout0\[10\]
-tcm_dffram_dout0\[9\]
-tcm_dffram_dout0\[8\]
-tcm_dffram_dout0\[7\]
-tcm_dffram_dout0\[6\]
-tcm_dffram_dout0\[5\]
-tcm_dffram_dout0\[4\]
-tcm_dffram_dout0\[3\]
-tcm_dffram_dout0\[2\]
-tcm_dffram_dout0\[1\]
-tcm_dffram_dout0\[0\]
-
-tcm_dffram_clk1          0800 0 2
-tcm_dffram_cs1
-tcm_dffram_addr1\[0\]
-tcm_dffram_addr1\[1\]
-tcm_dffram_addr1\[2\]
-tcm_dffram_addr1\[3\]
-tcm_dffram_addr1\[4\]
-tcm_dffram_addr1\[5\]
-tcm_dffram_addr1\[6\]
-tcm_dffram_addr1\[7\]
-tcm_dffram_wmask1\[0\]
-tcm_dffram_wmask1\[1\]
-tcm_dffram_wmask1\[2\]
-tcm_dffram_wmask1\[3\]
-tcm_dffram_din1\[0\]
-tcm_dffram_din1\[1\]
-tcm_dffram_din1\[2\]
-tcm_dffram_din1\[3\]
-tcm_dffram_din1\[4\]
-tcm_dffram_din1\[5\]
-tcm_dffram_din1\[6\]
-tcm_dffram_din1\[7\]
-tcm_dffram_din1\[8\]
-tcm_dffram_din1\[9\]
-tcm_dffram_din1\[10\]
-tcm_dffram_din1\[11\]
-tcm_dffram_din1\[12\]
-tcm_dffram_din1\[13\]
-tcm_dffram_din1\[14\]
-tcm_dffram_din1\[15\]
-tcm_dffram_din1\[16\]
-tcm_dffram_din1\[17\]
-tcm_dffram_din1\[18\]
-tcm_dffram_din1\[19\]
-tcm_dffram_din1\[20\]
-tcm_dffram_din1\[21\]
-tcm_dffram_din1\[22\]
-tcm_dffram_din1\[23\]
-tcm_dffram_din1\[24\]
-tcm_dffram_din1\[25\]
-tcm_dffram_din1\[26\]
-tcm_dffram_din1\[27\]
-tcm_dffram_din1\[28\]
-tcm_dffram_din1\[29\]
-tcm_dffram_din1\[30\]
-tcm_dffram_din1\[31\]
-
-tcm_dffram_dout1\[31\] 1450 0 2
-tcm_dffram_dout1\[30\]
-tcm_dffram_dout1\[29\]
-tcm_dffram_dout1\[28\]
-tcm_dffram_dout1\[27\]
-tcm_dffram_dout1\[26\]
-tcm_dffram_dout1\[25\]
-tcm_dffram_dout1\[24\]
-tcm_dffram_dout1\[23\]
-tcm_dffram_dout1\[22\]
-tcm_dffram_dout1\[21\]
-tcm_dffram_dout1\[20\]
-tcm_dffram_dout1\[19\]
-tcm_dffram_dout1\[18\]
-tcm_dffram_dout1\[17\]
-tcm_dffram_dout1\[16\]
-tcm_dffram_dout1\[15\]
-tcm_dffram_dout1\[14\]
-tcm_dffram_dout1\[13\]
-tcm_dffram_dout1\[12\]
-tcm_dffram_dout1\[11\]
-tcm_dffram_dout1\[10\]
-tcm_dffram_dout1\[9\]
-tcm_dffram_dout1\[8\]
-tcm_dffram_dout1\[7\]
-tcm_dffram_dout1\[6\]
-tcm_dffram_dout1\[5\]
-tcm_dffram_dout1\[4\]
-tcm_dffram_dout1\[3\]
-tcm_dffram_dout1\[2\]
-tcm_dffram_dout1\[1\]
-tcm_dffram_dout1\[0\]
-
-#N
-dcache_dffram_clk0          0000 0 2
-dcache_dffram_din0\[0\]
-dcache_dffram_din0\[1\]
-dcache_dffram_din0\[2\]
-dcache_dffram_din0\[3\]
-dcache_dffram_din0\[4\]
-dcache_dffram_din0\[5\]
-dcache_dffram_din0\[6\]
-dcache_dffram_din0\[7\]
-dcache_dffram_din0\[8\]
-dcache_dffram_din0\[9\]
-dcache_dffram_din0\[10\]
-dcache_dffram_din0\[11\]
-dcache_dffram_din0\[12\]
-dcache_dffram_din0\[13\]
-dcache_dffram_din0\[14\]
-dcache_dffram_din0\[15\]
-dcache_dffram_din0\[16\]
-dcache_dffram_din0\[17\]
-dcache_dffram_din0\[18\]
-dcache_dffram_din0\[19\]
-dcache_dffram_din0\[20\]
-dcache_dffram_din0\[21\]
-dcache_dffram_din0\[22\]
-dcache_dffram_din0\[23\]
-dcache_dffram_din0\[24\]
-dcache_dffram_din0\[25\]
-dcache_dffram_din0\[26\]
-dcache_dffram_din0\[27\]
-dcache_dffram_din0\[28\]
-dcache_dffram_din0\[29\]
-dcache_dffram_din0\[30\]
-dcache_dffram_din0\[31\]
-dcache_dffram_cs0
-dcache_dffram_addr0\[7\]
-dcache_dffram_addr0\[6\]
-dcache_dffram_addr0\[5\]
-dcache_dffram_addr0\[4\]
-dcache_dffram_addr0\[3\]
-dcache_dffram_addr0\[2\]
-dcache_dffram_addr0\[1\]
-dcache_dffram_addr0\[0\]
-dcache_dffram_wmask0\[3\]
-dcache_dffram_wmask0\[2\]
-dcache_dffram_wmask0\[1\]
-dcache_dffram_wmask0\[0\]
-dcache_dffram_dout0\[0\]
-dcache_dffram_dout0\[1\]
-dcache_dffram_dout0\[2\]
-dcache_dffram_dout0\[3\]
-dcache_dffram_dout0\[4\]
-dcache_dffram_dout0\[5\]
-dcache_dffram_dout0\[6\]
-dcache_dffram_dout0\[7\]
-dcache_dffram_dout0\[8\]
-dcache_dffram_dout0\[9\]
-dcache_dffram_dout0\[10\]
-dcache_dffram_dout0\[11\]
-dcache_dffram_dout0\[12\]
-dcache_dffram_dout0\[13\]
-dcache_dffram_dout0\[14\]
-dcache_dffram_dout0\[15\]
-dcache_dffram_dout0\[16\]
-dcache_dffram_dout0\[17\]
-dcache_dffram_dout0\[18\]
-dcache_dffram_dout0\[19\]
-dcache_dffram_dout0\[20\]
-dcache_dffram_dout0\[21\]
-dcache_dffram_dout0\[22\]
-dcache_dffram_dout0\[23\]
-dcache_dffram_dout0\[24\]
-dcache_dffram_dout0\[25\]
-dcache_dffram_dout0\[26\]
-dcache_dffram_dout0\[27\]
-dcache_dffram_dout0\[28\]
-dcache_dffram_dout0\[29\]
-dcache_dffram_dout0\[30\]
-dcache_dffram_dout0\[31\]
-
-dcache_dffram_clk1          0300 0 2
-dcache_dffram_din1\[0\]
-dcache_dffram_din1\[1\]
-dcache_dffram_din1\[2\]
-dcache_dffram_din1\[3\]
-dcache_dffram_din1\[4\]
-dcache_dffram_din1\[5\]
-dcache_dffram_din1\[6\]
-dcache_dffram_din1\[7\]
-dcache_dffram_din1\[8\]
-dcache_dffram_din1\[9\]
-dcache_dffram_din1\[10\]
-dcache_dffram_din1\[11\]
-dcache_dffram_din1\[12\]
-dcache_dffram_din1\[13\]
-dcache_dffram_din1\[14\]
-dcache_dffram_din1\[15\]
-dcache_dffram_din1\[16\]
-dcache_dffram_din1\[17\]
-dcache_dffram_din1\[18\]
-dcache_dffram_din1\[19\]
-dcache_dffram_din1\[20\]
-dcache_dffram_din1\[21\]
-dcache_dffram_din1\[22\]
-dcache_dffram_din1\[23\]
-dcache_dffram_din1\[24\]
-dcache_dffram_din1\[25\]
-dcache_dffram_din1\[26\]
-dcache_dffram_din1\[27\]
-dcache_dffram_din1\[28\]
-dcache_dffram_din1\[29\]
-dcache_dffram_din1\[30\]
-dcache_dffram_din1\[31\]
-dcache_dffram_cs1
-dcache_dffram_addr1\[7\]
-dcache_dffram_addr1\[6\]
-dcache_dffram_addr1\[5\]
-dcache_dffram_addr1\[4\]
-dcache_dffram_addr1\[3\]
-dcache_dffram_addr1\[2\]
-dcache_dffram_addr1\[1\]
-dcache_dffram_addr1\[0\]
-dcache_dffram_wmask1\[3\]
-dcache_dffram_wmask1\[2\]
-dcache_dffram_wmask1\[1\]
-dcache_dffram_wmask1\[0\]
-dcache_dffram_dout1\[0\]
-dcache_dffram_dout1\[1\]
-dcache_dffram_dout1\[2\]
-dcache_dffram_dout1\[3\]
-dcache_dffram_dout1\[4\]
-dcache_dffram_dout1\[5\]
-dcache_dffram_dout1\[6\]
-dcache_dffram_dout1\[7\]
-dcache_dffram_dout1\[8\]
-dcache_dffram_dout1\[9\]
-dcache_dffram_dout1\[10\]
-dcache_dffram_dout1\[11\]
-dcache_dffram_dout1\[12\]
-dcache_dffram_dout1\[13\]
-dcache_dffram_dout1\[14\]
-dcache_dffram_dout1\[15\]
-dcache_dffram_dout1\[16\]
-dcache_dffram_dout1\[17\]
-dcache_dffram_dout1\[18\]
-dcache_dffram_dout1\[19\]
-dcache_dffram_dout1\[20\]
-dcache_dffram_dout1\[21\]
-dcache_dffram_dout1\[22\]
-dcache_dffram_dout1\[23\]
-dcache_dffram_dout1\[24\]
-dcache_dffram_dout1\[25\]
-dcache_dffram_dout1\[26\]
-dcache_dffram_dout1\[27\]
-dcache_dffram_dout1\[28\]
-dcache_dffram_dout1\[29\]
-dcache_dffram_dout1\[30\]
-dcache_dffram_dout1\[31\]
-
-#S
-icache_dffram_clk0        0000 0 2
-icache_dffram_dout0\[0\]  
-icache_dffram_dout0\[1\]
-icache_dffram_dout0\[2\]
-icache_dffram_dout0\[3\]
-icache_dffram_dout0\[4\]
-icache_dffram_dout0\[5\]
-icache_dffram_dout0\[6\]
-icache_dffram_dout0\[7\]
-icache_dffram_dout0\[8\]
-icache_dffram_dout0\[9\]
-icache_dffram_dout0\[10\]
-icache_dffram_dout0\[11\]
-icache_dffram_dout0\[12\]
-icache_dffram_dout0\[13\]
-icache_dffram_dout0\[14\]
-icache_dffram_dout0\[15\]
-icache_dffram_dout0\[16\]
-icache_dffram_dout0\[17\]
-icache_dffram_dout0\[18\]
-icache_dffram_dout0\[19\]
-icache_dffram_dout0\[20\]
-icache_dffram_dout0\[21\]
-icache_dffram_dout0\[22\]
-icache_dffram_dout0\[23\]
-icache_dffram_dout0\[24\]
-icache_dffram_dout0\[25\]
-icache_dffram_dout0\[26\]
-icache_dffram_dout0\[27\]
-icache_dffram_dout0\[28\]
-icache_dffram_dout0\[29\]
-icache_dffram_dout0\[30\]
-icache_dffram_dout0\[31\]
-icache_dffram_cs0
-icache_dffram_addr0\[7\]
-icache_dffram_addr0\[6\]
-icache_dffram_addr0\[5\]
-icache_dffram_addr0\[4\]
-icache_dffram_addr0\[3\]
-icache_dffram_addr0\[2\]
-icache_dffram_addr0\[1\]
-icache_dffram_addr0\[0\]
-icache_dffram_wmask0\[3\]
-icache_dffram_wmask0\[2\]
-icache_dffram_wmask0\[1\]
-icache_dffram_wmask0\[0\]
-icache_dffram_din0\[0\]
-icache_dffram_din0\[1\]
-icache_dffram_din0\[2\]
-icache_dffram_din0\[3\]
-icache_dffram_din0\[4\]
-icache_dffram_din0\[5\]
-icache_dffram_din0\[6\]
-icache_dffram_din0\[7\]
-icache_dffram_din0\[8\]
-icache_dffram_din0\[9\]
-icache_dffram_din0\[10\]
-icache_dffram_din0\[11\]
-icache_dffram_din0\[12\]
-icache_dffram_din0\[13\]
-icache_dffram_din0\[14\]
-icache_dffram_din0\[15\]
-icache_dffram_din0\[16\]
-icache_dffram_din0\[17\]
-icache_dffram_din0\[18\]
-icache_dffram_din0\[19\]
-icache_dffram_din0\[20\]
-icache_dffram_din0\[21\]
-icache_dffram_din0\[22\]
-icache_dffram_din0\[23\]
-icache_dffram_din0\[24\]
-icache_dffram_din0\[25\]
-icache_dffram_din0\[26\]
-icache_dffram_din0\[27\]
-icache_dffram_din0\[28\]
-icache_dffram_din0\[29\]
-icache_dffram_din0\[30\]
-icache_dffram_din0\[31\]
-
-icache_dffram_clk1          0300 0 2
-icache_dffram_dout1\[0\]
-icache_dffram_dout1\[1\]
-icache_dffram_dout1\[2\]
-icache_dffram_dout1\[3\]
-icache_dffram_dout1\[4\]
-icache_dffram_dout1\[5\]
-icache_dffram_dout1\[6\]
-icache_dffram_dout1\[7\]
-icache_dffram_dout1\[8\]
-icache_dffram_dout1\[9\]
-icache_dffram_dout1\[10\]
-icache_dffram_dout1\[11\]
-icache_dffram_dout1\[12\]
-icache_dffram_dout1\[13\]
-icache_dffram_dout1\[14\]
-icache_dffram_dout1\[15\]
-icache_dffram_dout1\[16\]
-icache_dffram_dout1\[17\]
-icache_dffram_dout1\[18\]
-icache_dffram_dout1\[19\]
-icache_dffram_dout1\[20\]
-icache_dffram_dout1\[21\]
-icache_dffram_dout1\[22\]
-icache_dffram_dout1\[23\]
-icache_dffram_dout1\[24\]
-icache_dffram_dout1\[25\]
-icache_dffram_dout1\[26\]
-icache_dffram_dout1\[27\]
-icache_dffram_dout1\[28\]
-icache_dffram_dout1\[29\]
-icache_dffram_dout1\[30\]
-icache_dffram_dout1\[31\]
-icache_dffram_cs1
-icache_dffram_addr1\[7\]
-icache_dffram_addr1\[6\]
-icache_dffram_addr1\[5\]
-icache_dffram_addr1\[4\]
-icache_dffram_addr1\[3\]
-icache_dffram_addr1\[2\]
-icache_dffram_addr1\[1\]
-icache_dffram_addr1\[0\]
-icache_dffram_wmask1\[3\]
-icache_dffram_wmask1\[2\]
-icache_dffram_wmask1\[1\]
-icache_dffram_wmask1\[0\]
-icache_dffram_din1\[0\]
-icache_dffram_din1\[1\]
-icache_dffram_din1\[2\]
-icache_dffram_din1\[3\]
-icache_dffram_din1\[4\]
-icache_dffram_din1\[5\]
-icache_dffram_din1\[6\]
-icache_dffram_din1\[7\]
-icache_dffram_din1\[8\]
-icache_dffram_din1\[9\]
-icache_dffram_din1\[10\]
-icache_dffram_din1\[11\]
-icache_dffram_din1\[12\]
-icache_dffram_din1\[13\]
-icache_dffram_din1\[14\]
-icache_dffram_din1\[15\]
-icache_dffram_din1\[16\]
-icache_dffram_din1\[17\]
-icache_dffram_din1\[18\]
-icache_dffram_din1\[19\]
-icache_dffram_din1\[20\]
-icache_dffram_din1\[21\]
-icache_dffram_din1\[22\]
-icache_dffram_din1\[23\]
-icache_dffram_din1\[24\]
-icache_dffram_din1\[25\]
-icache_dffram_din1\[26\]
-icache_dffram_din1\[27\]
-icache_dffram_din1\[28\]
-icache_dffram_din1\[29\]
-icache_dffram_din1\[30\]
-icache_dffram_din1\[31\]
-
-riscv_debug\[0\]      600  0 2
-riscv_debug\[1\]
-riscv_debug\[2\]
-riscv_debug\[3\]
-riscv_debug\[4\]
-riscv_debug\[5\]
-riscv_debug\[6\]
-riscv_debug\[7\]
-riscv_debug\[8\]
-riscv_debug\[9\]
-riscv_debug\[10\]
-riscv_debug\[11\]
-riscv_debug\[12\]
-riscv_debug\[13\]
-riscv_debug\[14\]
-riscv_debug\[15\]
-riscv_debug\[16\]
-riscv_debug\[17\]
-riscv_debug\[18\]
-riscv_debug\[19\]
-riscv_debug\[20\]
-riscv_debug\[21\]
-riscv_debug\[22\]
-riscv_debug\[23\]
-riscv_debug\[24\]
-riscv_debug\[25\]
-riscv_debug\[26\]
-riscv_debug\[27\]
-riscv_debug\[28\]
-riscv_debug\[29\]
-riscv_debug\[30\]
-riscv_debug\[31\]
-riscv_debug\[32\]
-riscv_debug\[33\]
-riscv_debug\[34\]
-riscv_debug\[35\]
-riscv_debug\[36\]
-riscv_debug\[37\]
-riscv_debug\[38\]
-riscv_debug\[39\]
-riscv_debug\[40\]
-riscv_debug\[41\]
-riscv_debug\[42\]
-riscv_debug\[43\]
-riscv_debug\[44\]
-riscv_debug\[45\]
-riscv_debug\[46\]
-riscv_debug\[47\]
-riscv_debug\[48\]
-riscv_debug\[49\]
-riscv_debug\[50\]
-riscv_debug\[51\]
-riscv_debug\[52\]
-riscv_debug\[53\]
-riscv_debug\[54\]
-riscv_debug\[55\]
-riscv_debug\[56\]
-riscv_debug\[57\]
-riscv_debug\[58\]
-riscv_debug\[59\]
-riscv_debug\[60\]
-riscv_debug\[61\]
-riscv_debug\[62\]
-riscv_debug\[63\]
-
-
-wb_rst_n          700 0 2
-pwrup_rst_n       
-rst_n        
-core_clk              
-core_clk_mclk              
-rtc_clk             
-cpu_rst_n           
diff --git a/openlane/yifive/sta.tcl b/openlane/yifive/sta.tcl
deleted file mode 100644
index 8168d16..0000000
--- a/openlane/yifive/sta.tcl
+++ /dev/null
@@ -1,95 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
-set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
-set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
-set ::env(CURRENT_NETLIST) ../user_project_wrapper/netlist/syntacore.v
-set ::env(DESIGN_NAME) "scr1_top_wb"
-set ::env(CURRENT_SPEF) ../../spef/scr1_top_wb.spef
-set ::env(BASE_SDC_FILE) "base.sdc"
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
-set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-set ::env(SYNTH_CAP_LOAD) "17.65"
-set ::env(WIRE_RC_LAYER) "met1"
-
-
-set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
-define_corners wc bc tt
-read_liberty -corner bc $::env(LIB_FASTEST)
-read_liberty -corner wc $::env(LIB_SLOWEST)
-read_liberty -corner tt $::env(LIB_TYPICAL)
-
-read_verilog $::env(CURRENT_NETLIST)
-link_design  $::env(DESIGN_NAME)
-
-read_spef  $::env(CURRENT_SPEF)
-
-read_sdc -echo $::env(BASE_SDC_FILE)
-
-# check for missing constraints
-check_setup  -verbose > unconstraints.rpt
-
-set_operating_conditions -analysis_type single
-# Propgate the clock
-set_propagated_clock [all_clocks]
-
-report_tns
-report_wns
-#report_power 
-
-echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_ss_max.rpt
-report_checks -unique -path_delay max -slack_max -0.0 -group_count 100   -corner wc  -format full_clock_expanded >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group  wbm_clk_i   -corner wc  -format full_clock_expanded >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group  wbs_clk_i   -corner wc  -format full_clock_expanded >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group  cpu_clk     -corner wc  -format full_clock_expanded >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group  rtc_clk     -corner wc  -format full_clock_expanded >> timing_ss_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group  line_clk    -corner wc  -format full_clock_expanded >> timing_ss_max.rpt
-report_checks -path_delay max   -corner wc >> timing_ff_max.rpt
-
-echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_ff_min.rpt
-report_checks -unique -path_delay min -slack_min -0.0 -group_count 100   -corner bc  -format full_clock_expanded >> timing_ff_min.rpt
-report_checks -group_count 100  -path_delay min -path_group  wbm_clk_i   -corner bc  -format full_clock_expanded >> timing_ff_min.rpt
-report_checks -group_count 100  -path_delay min -path_group  wbs_clk_i   -corner bc  -format full_clock_expanded >> timing_ff_min.rpt
-report_checks -group_count 100  -path_delay min -path_group  cpu_clk     -corner bc  -format full_clock_expanded >> timing_ff_min.rpt
-report_checks -group_count 100  -path_delay min -path_group  rtc_clk     -corner bc  -format full_clock_expanded >> timing_ff_min.rpt
-report_checks -group_count 100  -path_delay min -path_group  line_clk    -corner bc  -format full_clock_expanded >> timing_ff_min.rpt
-report_checks -path_delay min  -corner bc >> timing_min.rpt
-
-echo "################ CORNER : TT (MAX) TIMING Report ###################" > timing_tt_max.rpt 
-report_checks -unique -path_delay max -slack_min -0.0 -group_count 100 -corner tt  -format full_clock_expanded >> timing_tt_max.rpt
-report_checks -group_count 100  -path_delay max -path_group wbm_clk_i  -corner tt  -format full_clock_expanded >> timing_tt_max.rpt
-report_checks -group_count 100  -path_delay max -path_group wbs_clk_i  -corner tt  -format full_clock_expanded >> timing_tt_max.rpt
-report_checks -group_count 100  -path_delay max -path_group cpu_clk    -corner tt  -format full_clock_expanded >> timing_tt_max.rpt
-report_checks -group_count 100  -path_delay max -path_group rtc_clk    -corner tt  -format full_clock_expanded >> timing_tt_max.rpt
-report_checks -group_count 100  -path_delay max -path_group line_clk   -corner tt  -format full_clock_expanded >> timing_tt_max.rpt
-report_checks -path_delay max  -corner tt >> timing_tt_max.rpt
-
-echo "################ CORNER : TT (MIN) TIMING Report ###################" > timing_tt_min.rpt
-report_checks -unique -path_delay min -slack_min -0.0 -group_count 100   -corner tt  -format full_clock_expanded >> timing_tt_min.rpt
-report_checks -group_count 100  -path_delay min -path_group  wbm_clk_i   -corner tt  -format full_clock_expanded >> timing_tt_min.rpt
-report_checks -group_count 100  -path_delay min -path_group  wbs_clk_i   -corner tt  -format full_clock_expanded >> timing_tt_min.rpt
-report_checks -group_count 100  -path_delay min -path_group  cpu_clk     -corner tt  -format full_clock_expanded >> timing_tt_min.rpt
-report_checks -group_count 100  -path_delay min -path_group  rtc_clk     -corner tt  -format full_clock_expanded >> timing_tt_min.rpt
-report_checks -group_count 100  -path_delay min -path_group  line_clk    -corner tt  -format full_clock_expanded >> timing_tt_min.rpt
-report_checks -path_delay min  -corner tt >> timing_tt_min.rpt
-
-
-
-
-report_checks -path_delay min_max 
-
-#exit