diff --git a/openlane/syntacore/base.sdc b/openlane/syntacore/base.sdc
index 508d423..c200e4b 100644
--- a/openlane/syntacore/base.sdc
+++ b/openlane/syntacore/base.sdc
@@ -63,6 +63,9 @@
 set all_inputs_wo_wb_clk_rst [lreplace [all_inputs] $wb_clk_indx $wb_rst_indx]
 set all_outputs_wb [all_outputs]
 
+set_false_path -to riscv_debug*
+set_false_path -from soft_irq
+
 set_input_delay $wb_input_delay_value  -clock [get_clocks $::env(WB_CLOCK_NAME)] $all_inputs_wo_wb_clk_rst
 set_input_delay 5.0 -clock [get_clocks $::env(WB_CLOCK_NAME)] {wb_rst_n}
 set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_NAME)] $all_outputs_wb
diff --git a/openlane/syntacore/sta.tcl b/openlane/syntacore/sta.tcl
index d23ac5a..0a63ab5 100644
--- a/openlane/syntacore/sta.tcl
+++ b/openlane/syntacore/sta.tcl
@@ -14,11 +14,11 @@
 # SPDX-License-Identifier: Apache-2.0
 # SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
 
-set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
-set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
-set ::env(CURRENT_NETLIST) /project/openlane/syntacore/runs/syntacore/results/lvs/scr1_top_wb.lvs.powered.v
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(CURRENT_NETLIST) ../user_project_wrapper/netlist/syntacore.v
 set ::env(DESIGN_NAME) "scr1_top_wb"
-set ::env(CURRENT_SPEF) /project/openlane/syntacore/runs/syntacore/results/routing/scr1_top_wb.spef
+set ::env(CURRENT_SPEF) ../../spef/scr1_top_wb.spef
 set ::env(BASE_SDC_FILE) "/project/openlane/syntacore/base.sdc"
 set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
 set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index d84a6e7..96e390e 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,1h1m47s,0h39m1s,34498.88888888888,1.8,17249.44444444444,23,1212.41,31049,0,0,0,0,0,0,0,95,10,-1,0,1627641,253589,-4.82,-4.82,-4.79,-4.79,-4.89,-38.56,-38.56,-38.91,-38.91,-39.32,1349556396,0.0,18.61,16.76,4.8,0.61,-1,30872,31173,2777,3078,0,0,0,31049,637,0,695,2031,3988,2108,1314,7432,2838,2808,95,866,22836,0,23702,67.15916722632639,14.89,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h36m28s,0h16m19s,27778.888888888887,1.8,13889.444444444443,18,1131.94,25001,0,0,0,0,0,0,0,74,3,-1,0,1325964,199950,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1100394978,0.0,14.95,14.15,2.89,0.96,-1,24824,25125,2879,3180,0,0,0,25001,532,68,543,604,2798,755,155,7438,2872,2842,106,866,22836,0,23702,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index b025532..d82e1f3 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h39m39s,0h4m47s,3.3079078455790785,10.2784,1.6539539227895392,0,555.97,17,0,0,0,0,0,0,0,0,1,-1,-1,1189476,3936,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.26,4.31,0.72,1.81,-1,848,1466,848,1466,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h36m12s,0h3m45s,3.3079078455790785,10.2784,1.6539539227895392,0,552.84,17,0,0,0,0,0,0,0,0,1,-1,-1,1189440,3984,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.27,4.31,0.7,1.74,-1,848,1466,848,1466,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 3edeaba..85c0aa7 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -149,7 +149,8 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("risc_boot.vcd");
-	   	$dumpvars(4, user_uart_tb);
+	   	$dumpvars(1, user_uart_tb);
+	   	$dumpvars(0, user_uart_tb.u_top.u_riscv_top);
 	   end
        `endif
 
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
index 8ce42c3..433ed93 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
@@ -845,26 +845,41 @@
 assign mprf_rs2_req = exu_queue_vd & idu2exu_use_rs2_i;
 `else // SCR1_NO_EXE_STAGE
  `ifdef  SCR1_MPRF_RAM
-assign mprf_rs1_req = exu_queue_en
-                    ? (exu_queue_vd_next & idu2exu_use_rs1_i)
-                    : (exu_queue_vd      & idu2exu_use_rs1_ff);
-assign mprf_rs2_req = exu_queue_en
-                    ? (exu_queue_vd_next & idu2exu_use_rs2_i)
-                    : (exu_queue_vd      & idu2exu_use_rs2_ff);
+     assign mprf_rs1_req = exu_queue_en
+                         ? (exu_queue_vd_next & idu2exu_use_rs1_i)
+                         : (exu_queue_vd      & idu2exu_use_rs1_ff);
+     assign mprf_rs2_req = exu_queue_en
+                         ? (exu_queue_vd_next & idu2exu_use_rs2_i)
+                         : (exu_queue_vd      & idu2exu_use_rs2_ff);
  `else // SCR1_MPRF_RAM
-assign mprf_rs1_req = exu_queue_vd & idu2exu_use_rs1_ff;
-assign mprf_rs2_req = exu_queue_vd & idu2exu_use_rs2_ff;
- `endif // SCR1_MPRF_RAM
+    `ifdef  SCRC1_MPRF_STAGE // ADD FF Stage at MRPF
+        assign mprf_rs1_req = exu_queue_en
+                            ? (exu_queue_vd_next & idu2exu_use_rs1_i)
+                            : (exu_queue_vd      & idu2exu_use_rs1_ff);
+        assign mprf_rs2_req = exu_queue_en
+                            ? (exu_queue_vd_next & idu2exu_use_rs2_i)
+                            : (exu_queue_vd      & idu2exu_use_rs2_ff);
+
+     `else
+          assign mprf_rs1_req = exu_queue_vd & idu2exu_use_rs1_ff;
+          assign mprf_rs2_req = exu_queue_vd & idu2exu_use_rs2_ff;
+     `endif // SCR1_MPRF_RAM
+  `endif
 `endif // SCR1_NO_EXE_STAGE
 
 // If exu_queue isn't enabled we need previous addresses and usage flags because
 // RAM blocks read operation is SYNCHRONOUS
 `ifdef SCR1_MPRF_RAM
-assign mprf_rs1_addr = exu_queue_en ? idu2exu_cmd_i.rs1_addr : exu_queue.rs1_addr;
-assign mprf_rs2_addr = exu_queue_en ? idu2exu_cmd_i.rs2_addr : exu_queue.rs2_addr;
+     assign mprf_rs1_addr = exu_queue_en ? idu2exu_cmd_i.rs1_addr : exu_queue.rs1_addr;
+     assign mprf_rs2_addr = exu_queue_en ? idu2exu_cmd_i.rs2_addr : exu_queue.rs2_addr;
 `else // SCR1_MPRF_RAM
-assign mprf_rs1_addr = exu_queue.rs1_addr;
-assign mprf_rs2_addr = exu_queue.rs2_addr;
+    `ifdef SCRC1_MPRF_STAGE
+        assign mprf_rs1_addr = exu_queue_en ? idu2exu_cmd_i.rs1_addr : exu_queue.rs1_addr;
+        assign mprf_rs2_addr = exu_queue_en ? idu2exu_cmd_i.rs2_addr : exu_queue.rs2_addr;
+    `else
+        assign mprf_rs1_addr = exu_queue.rs1_addr;
+        assign mprf_rs2_addr = exu_queue.rs2_addr;
+     `endif
 `endif // SCR1_MPRF_RAM
 
 assign exu2mprf_rs1_addr_o = mprf_rs1_req ? `SCR1_MPRF_AWIDTH'(mprf_rs1_addr) : '0;
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
index 9b4b167..ee9164e 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
@@ -49,6 +49,24 @@
 logic                        rs1_addr_vd;
 logic                        rs2_addr_vd;
 
+`ifdef SCRC1_MPRF_STAGE
+logic                        rs1_addr_vd_ff;
+logic                        rs2_addr_vd_ff;
+
+logic                        rs1_new_data_req;
+logic                        rs2_new_data_req;
+logic                        rs1_new_data_req_ff;
+logic                        rs2_new_data_req_ff;
+logic                        read_new_data_req;
+
+logic    [`SCR1_XLEN-1:0]    rd_data_ff;
+
+logic    [`SCR1_XLEN-1:0]    rs1_data_ff;
+logic    [`SCR1_XLEN-1:0]    rs2_data_ff;
+
+
+`endif
+
 `ifdef  SCR1_MPRF_RAM
 logic                        rs1_addr_vd_ff;
 logic                        rs2_addr_vd_ff;
@@ -147,8 +165,43 @@
 //------------------------------------------------------------------------------
 
 // asynchronous read operation
-assign  mprf2exu_rs1_data_o = ( rs1_addr_vd ) ? mprf_int[exu2mprf_rs1_addr_i] : '0;
-assign  mprf2exu_rs2_data_o = ( rs2_addr_vd ) ? mprf_int[exu2mprf_rs2_addr_i] : '0;
+//
+`ifdef SCRC1_MPRF_STAGE
+   assign  rs1_new_data_req    =   wr_req_vd & ( exu2mprf_rs1_addr_i == exu2mprf_rd_addr_i );
+   assign  rs2_new_data_req    =   wr_req_vd & ( exu2mprf_rs2_addr_i == exu2mprf_rd_addr_i );
+   assign  read_new_data_req   =   rs1_new_data_req | rs2_new_data_req;
+
+// bypass new wr_data to the read output if write/read collision occurs
+   assign  mprf2exu_rs1_data_o   =   ( rs1_new_data_req_ff ) ? rd_data_ff
+                                   : (( rs1_addr_vd_ff )     ? rs1_data_ff
+                                                               : '0 );
+   
+   assign  mprf2exu_rs2_data_o   =   ( rs2_new_data_req_ff ) ? rd_data_ff
+                                   : (( rs2_addr_vd_ff )     ? rs2_data_ff
+                                                               : '0 );
+
+   
+   always_ff @( posedge clk ) begin
+      if ( read_new_data_req ) begin
+          rd_data_ff     <=  exu2mprf_rd_data_i;
+      end
+   end
+
+   always_ff @( posedge clk ) begin
+       rs1_addr_vd_ff          <=  rs1_addr_vd;
+       rs2_addr_vd_ff          <=  rs2_addr_vd;
+       rs1_new_data_req_ff     <=  rs1_new_data_req;
+       rs2_new_data_req_ff     <=  rs2_new_data_req;
+   end
+   always_ff @( posedge clk ) begin
+      rs1_data_ff   <=   mprf_int[exu2mprf_rs1_addr_i];
+      rs2_data_ff   <=   mprf_int[exu2mprf_rs2_addr_i];
+   end
+
+`else 
+    assign  mprf2exu_rs1_data_o = ( rs1_addr_vd ) ? mprf_int[exu2mprf_rs1_addr_i] : '0;
+    assign  mprf2exu_rs2_data_o = ( rs2_addr_vd ) ? mprf_int[exu2mprf_rs2_addr_i] : '0;
+`endif
 
 // write operation
  `ifdef SCR1_MPRF_RST_EN
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
index 36179a8..a96c617 100644
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
+++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
@@ -88,17 +88,19 @@
   `define SCR1_RVM_EXT
   `define SCR1_RVC_EXT
   parameter int unsigned SCR1_MTVEC_BASE_WR_BITS = 26;
-  `define SCR1_MTVEC_MODE_EN
-  `define SCR1_FAST_MUL
+  `define SCR1_MTVEC_MODE_EN          // enable writable MTVEC.mode field to allow vectored irq mode, otherwise only direct mode is possible
+// `define SCR1_FAST_MUL               // enable fast one-cycle multiplication, otherwise multiplication takes 32 cycles
 //`define SCR1_MPRF_RST_EN - yosys fix, two dimensional array init not allowed
-  `define SCR1_MCOUNTEN_EN
-//  `define SCR1_DBG_EN
-  `define SCR1_TDU_EN
-  parameter int unsigned SCR1_TDU_TRIG_NUM = 4;
-  `define SCR1_TDU_ICOUNT_EN
-  `define SCR1_IPIC_EN
-  `define SCR1_IPIC_SYNC_EN
+  `define SCR1_MCOUNTEN_EN            // enable custom MCOUNTEN CSR for counter control
+//`define SCR1_DBG_EN                 // enable Debug Subsystem (TAPC, DM, SCU, HDU)
+//`define SCR1_TDU_EN                 // enable Trigger Debug Unit (hardware breakpoints)
+//  parameter int unsigned SCR1_TDU_TRIG_NUM = 4;
+// `define SCR1_TDU_ICOUNT_EN          // enable hardware triggers on instruction counter
+  `define SCR1_IPIC_EN                // enable Integrated Programmable Interrupt Controller
+  `define SCR1_IPIC_SYNC_EN           // enable IPIC synchronizer
 //  `define SCR1_TCM_EN
+  `define SCR1_NEW_PC_REG             // enable register in IFU for New_PC value
+  `define SCRC1_MPRF_STAGE            // enabled register at Read path of MPRF
 `elsif  SCR1_CFG_RV32IC_BASE
   `define SCR1_RVI_EXT
   `define SCR1_RVC_EXT
diff --git a/verilog/rtl/syntacore/scr1/synth/base.sdc b/verilog/rtl/syntacore/scr1/synth/base.sdc
new file mode 100644
index 0000000..e47298c
--- /dev/null
+++ b/verilog/rtl/syntacore/scr1/synth/base.sdc
@@ -0,0 +1,89 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+set_units -time ns
+#Wishbone Clock
+set ::env(WB_CLOCK_PERIOD)    "10"
+set ::env(WB_CLOCK_PORT)      "wb_clk"
+set ::env(WB_CLOCK_NAME)      "wb_clk"
+
+#Risc Core Clock
+set ::env(CORE_CLOCK_PERIOD) "20"
+set ::env(CORE_CLOCK_PORT)   "core_clk"
+set ::env(CORE_CLOCK_NAME)   "core_clk"
+
+#RTC Core Clock
+set ::env(RTC_CLOCK_PERIOD) "40"
+set ::env(RTC_CLOCK_PORT)   "rtc_clk"
+set ::env(RTC_CLOCK_NAME)   "rtc_clk"
+
+######################################
+# CORE Clock domain input output
+######################################
+create_clock [get_ports $::env(CORE_CLOCK_PORT)]  -name $::env(CORE_CLOCK_NAME)  -period $::env(CORE_CLOCK_PERIOD)
+set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
+set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting core output delay to: $core_output_delay_value"
+puts "\[INFO\]: Setting core input delay to: $core_input_delay_value"
+set core_clk_indx [lsearch [all_inputs] [get_port $::env(CORE_CLOCK_NAME)]]
+set core_rst_indx [lsearch [all_inputs] [get_port cpu_rst_n]]
+set all_inputs_wo_core_clk_rst [lreplace [all_inputs] $core_clk_indx $core_rst_indx]
+set all_outputs_core [all_outputs] 
+
+set_input_delay $core_input_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] $all_inputs_wo_core_clk_rst
+set_input_delay 5.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {cpu_rst_n}
+set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] $all_outputs_core
+
+create_clock [get_ports $::env(RTC_CLOCK_PORT)]  -name $::env(RTC_CLOCK_NAME)  -period $::env(RTC_CLOCK_PERIOD)
+
+######################################
+# WB Clock domain input output
+######################################
+create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_NAME)  -period $::env(WB_CLOCK_PERIOD)
+set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+set wb_clk_indx [lsearch [all_inputs] [get_port $::env(WB_CLOCK_NAME)]]
+set wb_rst_indx [lsearch [all_inputs] [get_port wb_rst_n]]
+set all_inputs_wo_wb_clk_rst [lreplace [all_inputs] $wb_clk_indx $wb_rst_indx]
+set all_outputs_wb [all_outputs]
+
+set_false_path -to riscv_debug*
+set_false_path -from soft_irq
+
+set_input_delay $wb_input_delay_value  -clock [get_clocks $::env(WB_CLOCK_NAME)] $all_inputs_wo_wb_clk_rst
+set_input_delay 5.0 -clock [get_clocks $::env(WB_CLOCK_NAME)] {wb_rst_n}
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_NAME)] $all_outputs_wb
+
+#### Clock Async Defination
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_NAME)] -group [get_clocks $::env(CORE_CLOCK_NAME)] -group [get_clocks $::env(RTC_CLOCK_NAME)]
+
+set_clock_uncertainty -from $::env(WB_CLOCK_NAME)    -to $::env(WB_CLOCK_NAME)    -setup 0.400
+set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)  -to $::env(CORE_CLOCK_NAME)   -setup 0.400
+set_clock_uncertainty -from $::env(RTC_CLOCK_NAME)   -to $::env(RTC_CLOCK_NAME)   -setup 0.400
+
+set_clock_uncertainty -from $::env(WB_CLOCK_NAME)    -to $::env(WB_CLOCK_NAME)    -hold 0.050
+set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)  -to $::env(CORE_CLOCK_NAME)   -hold 0.050
+set_clock_uncertainty -from $::env(RTC_CLOCK_NAME)   -to $::env(RTC_CLOCK_NAME)   -hold 0.050
+
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
diff --git a/verilog/rtl/syntacore/scr1/synth/sta.tcl b/verilog/rtl/syntacore/scr1/synth/sta.tcl
new file mode 100644
index 0000000..bddbb8d
--- /dev/null
+++ b/verilog/rtl/syntacore/scr1/synth/sta.tcl
@@ -0,0 +1,54 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(CURRENT_NETLIST) netlist/scr1_top_wb.gv
+set ::env(DESIGN_NAME) "scr1_top_wb"
+set ::env(BASE_SDC_FILE) "base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+read_liberty -min $::env(LIB_FASTEST)
+read_liberty -max $::env(LIB_SLOWEST)
+read_verilog $::env(CURRENT_NETLIST)
+link_design  $::env(DESIGN_NAME)
+
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup  -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+report_power 
+report_checks -unique -slack_max -0.0 -group_count 100 
+report_checks -unique -slack_min -0.0 -group_count 100 
+report_checks -path_delay min_max 
+report_checks -group_count 100  -slack_max -0.01  > timing.rpt
+
+report_checks -group_count 100  -slack_min -0.01 >> timing.rpt
+
+
diff --git a/verilog/rtl/syntacore/scr1/synth/synth.tcl b/verilog/rtl/syntacore/scr1/synth/synth.tcl
index 1499a8c..4375c58 100755
--- a/verilog/rtl/syntacore/scr1/synth/synth.tcl
+++ b/verilog/rtl/syntacore/scr1/synth/synth.tcl
@@ -55,7 +55,7 @@
 	../src/top/scr1_top_wb.sv   \
 	../src/top/scr1_dmem_wb.sv   \
 	../src/top/scr1_imem_wb.sv   \
-	../../../lib/sync_fifo.sv  ]
+	../../../lib/async_fifo.sv  ]
 
 #set ::env(VERILOG_FILES_BLACKBOX) [glob  \
 #            $::env(DESIGN_DIR)/src/top/scr1_dp_memory.sv ]
@@ -69,27 +69,23 @@
 set ::env(LIB_SYNTH)  ./tmp/trimmed.lib
 
 
-#set ::env(SDC_FILE) "./designs/aes128/src/aes128.sdc"
+set ::env(SDC_FILE) "base.sdc"
 
 # Fill this
 set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_PORT) "wb_clk core_clk rtc_clk"
 set ::env(CLOCK_TREE_SYNTH) 0
 
-set ::env(RUN_SIMPLE_CTS) 0
-set ::env(SYNTH_BUFFERING) 0
-set ::env(SYNTH_SIZING) 0
+set ::env(SYNTH_BUFFERING) 1
+set ::env(SYNTH_SIZING) 1
 
 set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
 set ::env(SYNTH_CAP_LOAD) "17.65"
 set ::env(SYNTH_MAX_TRAN) "[expr {0.1*10.0}]"
 
 set ::env(SYNTH_MAX_FANOUT) 6
-set ::env(FP_CORE_UTIL) 50
-set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
-set ::env(CELL_PAD) 4
 
-set ::env(SYNTH_NO_FLAT) "0"
+set ::env(SYNTH_NO_FLAT) "1"
 
 
 set ::env(SYNTH_STRATEGY) "AREA 0"
@@ -119,7 +115,7 @@
 yosys -import
 
 set vtop $::env(DESIGN_NAME)
-#set sdc_file $::env(SDC_FILE)
+set sdc_file $::env(SDC_FILE)
 set sclib $::env(LIB_SYNTH)
 
 if { [info exists ::env(SYNTH_DEFINES) ] } {
@@ -178,12 +174,12 @@
 
 
 # get old sdc, add library specific stuff for abc scripts
-set sdc_file $::env(yosys_tmp_file_tag).sdc
-set outfile [open ${sdc_file} w]
+#set sdc_file $::env(yosys_tmp_file_tag).sdc
+#set outfile [open ${sdc_file} w]
 #puts $outfile $sdc_data
-puts $outfile "set_driving_cell ${driver}"
-puts $outfile "set_load ${cload}"
-close $outfile
+#puts $outfile "set_driving_cell ${driver}"
+#puts $outfile "set_load ${cload}"
+#close $outfile
 
 
 # ABC Scrips
@@ -404,14 +400,14 @@
 	write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
 }
 
-if { $::env(SYNTH_NO_FLAT) } {
-	design -reset
-	file copy -force $::env(SAVE_NETLIST) $::env(yosys_tmp_file_tag)_unflat.v
-	read_verilog -sv $::env(SAVE_NETLIST)
-	synth -top $vtop -flatten
-	splitnets
-	opt_clean -purge
-	insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
-	write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
-	tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check
-}
+#if { $::env(SYNTH_NO_FLAT) } {
+#	design -reset
+#	file copy -force $::env(SAVE_NETLIST) $::env(yosys_tmp_file_tag)_unflat.v
+#	read_verilog -sv $::env(SAVE_NETLIST)
+#	synth -top $vtop -flatten
+#	splitnets
+#	opt_clean -purge
+#	insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
+#	write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
+#	tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check
+#}