diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index bc570fe..749e090 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec
+PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec user_cache_bypass
 
 all:  ${PATTERNS}
 	for i in ${PATTERNS}; do \
diff --git a/verilog/dv/firmware/link.ld b/verilog/dv/firmware/link.ld
index 222363d..b2a0030 100644
--- a/verilog/dv/firmware/link.ld
+++ b/verilog/dv/firmware/link.ld
@@ -25,7 +25,7 @@
 ENTRY(_start)
 
 MEMORY {
-  ROM (rxx) : ORIGIN = 0x0, LENGTH = 64K
+  ROM (rxx) : ORIGIN = 0x0, LENGTH = 128K
   RAM (rwx) : ORIGIN = 0x08000000, LENGTH = 64K
   TCM (rwx) : ORIGIN = 0x0C480000, LENGTH = 2K
 }
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 1face2a..27fd494 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -278,8 +278,8 @@
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
 	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343);
-	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h0306_2022);
-	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_5000);
+	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h1306_2022);
+	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_6000);
 
       end
    
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 7bab960..2d972d8 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -716,7 +716,7 @@
 //-----------------------------------------
 // Software Reg-2, Release date: <DAY><MONTH><YEAR>
 // ----------------------------------------
-gen_32b_reg  #(32'h0306_2022) u_reg_23	(
+gen_32b_reg  #(32'h1306_2022) u_reg_23	(
 	      //List of Inputs
 	      .reset_n    (h_reset_n     ),
 	      .clk        (mclk          ),
@@ -729,9 +729,9 @@
 	      );
 
 //-----------------------------------------
-// Software Reg-3: Poject Revison 4.5 = 0004500
+// Software Reg-3: Poject Revison 4.6 = 0004600
 // ----------------------------------------
-gen_32b_reg  #(32'h0004_5000) u_reg_24	(
+gen_32b_reg  #(32'h0004_6000) u_reg_24	(
 	      //List of Inputs
 	      .reset_n    (h_reset_n     ),
 	      .clk        (mclk          ),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index d022dad..f8c579f 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -212,6 +212,8 @@
 ////           @digitial io [33] port                             ////
 ////    4.5  June 2 2022, Dinesh A                                ////
 ////         1. DFFRAM Replaced by SRAM                           ////
+////    4.6  June 13 2022, Dinesh A                               ////
+////         1. icache and dcache bypass config addded            ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -362,8 +364,11 @@
 wire                           wbd_riscv_dmem_we_i                    ; // write
 wire   [WB_WIDTH-1:0]          wbd_riscv_dmem_dat_i                   ; // data output
 wire   [3:0]                   wbd_riscv_dmem_sel_i                   ; // byte enable
+wire   [2:0]                   wbd_riscv_dmem_bl_i                    ; // byte enable
+wire                           wbd_riscv_dmem_bry_i                   ; // burst access ready
 wire   [WB_WIDTH-1:0]          wbd_riscv_dmem_dat_o                   ; // data input
 wire                           wbd_riscv_dmem_ack_o                   ; // acknowlegement
+wire                           wbd_riscv_dmem_lack_o                  ; // acknowlegement
 wire                           wbd_riscv_dmem_err_o                   ; // error
 
 //---------------------------------------------------------------------
@@ -614,6 +619,8 @@
 wire [3:0]                     cfg_riscv_sram_lphase   = cfg_riscv_ctrl[3:0];
 wire [2:0]                     cfg_riscv_cache_ctrl    = cfg_riscv_ctrl[6:4];
 wire [1:0]                     cfg_riscv_debug_sel     = cfg_riscv_ctrl[9:8];
+wire                           cfg_bypass_icache       = cfg_riscv_ctrl[10];
+wire                           cfg_bypass_dcache       = cfg_riscv_ctrl[11];
 
 /////////////////////////////////////////////////////////
 // Clock Skew Ctrl
@@ -734,6 +741,8 @@
           .riscv_debug             (riscv_debug             ),
 	  .cfg_sram_lphase         (cfg_riscv_sram_lphase   ),
 	  .cfg_cache_ctrl          (cfg_riscv_cache_ctrl    ),
+	  .cfg_bypass_icache       (cfg_bypass_icache       ),
+	  .cfg_bypass_dcache       (cfg_bypass_dcache       ),
 
     // Clock
           .core_clk                (cpu_clk                 ),
@@ -843,8 +852,11 @@
           .wbd_dmem_we_o           (wbd_riscv_dmem_we_i     ), 
           .wbd_dmem_dat_o          (wbd_riscv_dmem_dat_i    ),
           .wbd_dmem_sel_o          (wbd_riscv_dmem_sel_i    ),
+          .wbd_dmem_bl_o           (wbd_riscv_dmem_bl_i     ),
+          .wbd_dmem_bry_o          (wbd_riscv_dmem_bry_i    ),
           .wbd_dmem_dat_i          (wbd_riscv_dmem_dat_o    ),
           .wbd_dmem_ack_i          (wbd_riscv_dmem_ack_o    ),
+          .wbd_dmem_lack_i         (wbd_riscv_dmem_lack_o   ),
           .wbd_dmem_err_i          (wbd_riscv_dmem_err_o    ) 
 );
 
@@ -1051,11 +1063,14 @@
           .m1_wbd_dat_i            (wbd_riscv_dmem_dat_i    ),
           .m1_wbd_adr_i            (wbd_riscv_dmem_adr_i    ),
           .m1_wbd_sel_i            (wbd_riscv_dmem_sel_i    ),
+          .m1_wbd_bl_i             (wbd_riscv_dmem_bl_i    ),
+          .m1_wbd_bry_i            (wbd_riscv_dmem_bry_i    ),
           .m1_wbd_we_i             (wbd_riscv_dmem_we_i     ),
           .m1_wbd_cyc_i            (wbd_riscv_dmem_stb_i    ),
           .m1_wbd_stb_i            (wbd_riscv_dmem_stb_i    ),
           .m1_wbd_dat_o            (wbd_riscv_dmem_dat_o    ),
           .m1_wbd_ack_o            (wbd_riscv_dmem_ack_o    ),
+          .m1_wbd_lack_o           (wbd_riscv_dmem_lack_o   ),
           .m1_wbd_err_o            (wbd_riscv_dmem_err_o    ),
          
          // Master 2 Interface
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index 8ab9487..9fb6344 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -136,6 +136,8 @@
          input	logic [31:0]	m1_wbd_dat_i,
          input	logic [31:0]	m1_wbd_adr_i,
          input	logic [3:0]	m1_wbd_sel_i,
+         input	logic [2:0]	m1_wbd_bl_i,
+         input	logic    	m1_wbd_bry_i,
          input	logic 	        m1_wbd_we_i,
          input	logic 	        m1_wbd_cyc_i,
          input	logic 	        m1_wbd_stb_i,
@@ -363,6 +365,8 @@
           .m1_wbd_dat_i            (m1_wbd_dat_i           ),
           .m1_wbd_adr_i            (m1_wbd_adr_i           ),
           .m1_wbd_sel_i            (m1_wbd_sel_i           ),
+          .m1_wbd_bl_i             (m1_wbd_bl_i            ),
+          .m1_wbd_bry_i            (m1_wbd_bry_i           ),
           .m1_wbd_we_i             (m1_wbd_we_i            ),
           .m1_wbd_cyc_i            (m1_wbd_cyc_i           ),
           .m1_wbd_stb_i            (m1_wbd_stb_i           ),
@@ -441,6 +445,8 @@
           .m1_wbd_dat_i            (m1_wbd_dat_i           ),
           .m1_wbd_adr_i            (m1_wbd_adr_i           ),
           .m1_wbd_sel_i            (m1_wbd_sel_i           ),
+          .m1_wbd_bl_i             (m1_wbd_bl_i            ),
+          .m1_wbd_bry_i            (m1_wbd_bry_i           ),
           .m1_wbd_we_i             (m1_wbd_we_i            ),
           .m1_wbd_cyc_i            (m1_wbd_cyc_i           ),
           .m1_wbd_stb_i            (m1_wbd_stb_i           ),
@@ -519,6 +525,8 @@
           .m1_wbd_dat_i            (m1_wbd_dat_i           ),
           .m1_wbd_adr_i            (m1_wbd_adr_i           ),
           .m1_wbd_sel_i            (m1_wbd_sel_i           ),
+          .m1_wbd_bl_i             (m1_wbd_bl_i            ),
+          .m1_wbd_bry_i            (m1_wbd_bry_i           ),
           .m1_wbd_we_i             (m1_wbd_we_i            ),
           .m1_wbd_cyc_i            (m1_wbd_cyc_i           ),
           .m1_wbd_stb_i            (m1_wbd_stb_i           ),
diff --git a/verilog/rtl/wb_interconnect/src/wb_slave_port.sv b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
index 87f0d4a..bc70ea2 100644
--- a/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
@@ -61,6 +61,8 @@
          input	logic [31:0]	m1_wbd_dat_i,
          input	logic [31:0]	m1_wbd_adr_i,
          input	logic [3:0]	m1_wbd_sel_i,
+         input	logic [2:0]	m1_wbd_bl_i,
+         input	logic    	m1_wbd_bry_i,
          input	logic 	        m1_wbd_we_i,
          input	logic 	        m1_wbd_cyc_i,
          input	logic 	        m1_wbd_stb_i,
@@ -172,8 +174,8 @@
 assign m1_wb_wr.wbd_dat = m1_wbd_dat_i;
 assign m1_wb_wr.wbd_adr = {m1_wbd_adr_i[31:2],2'b00};
 assign m1_wb_wr.wbd_sel = m1_wbd_sel_i;
-assign m1_wb_wr.wbd_bl  = 'h1;
-assign m1_wb_wr.wbd_bry = 'b1;
+assign m1_wb_wr.wbd_bl  = {7'b0,m1_wbd_bl_i};
+assign m1_wb_wr.wbd_bry = m1_wbd_bry_i;
 assign m1_wb_wr.wbd_we  = m1_wbd_we_i;
 assign m1_wb_wr.wbd_cyc = m1_wbd_cyc_i;
 assign m1_wb_wr.wbd_stb = m1_stb_i;
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c
index d7a1662..a7ce700 160000
--- a/verilog/rtl/yifive/ycr1c
+++ b/verilog/rtl/yifive/ycr1c
@@ -1 +1 @@
-Subproject commit d7a16620e3212cf1d2777a8040fc4f2cf4598764
+Subproject commit a7ce700b3004622c78c52c0ee22bf740bc6c86e5