diff --git a/.gitmodules b/.gitmodules
index dbec024..948b37f 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -4,6 +4,6 @@
 [submodule "verilog/rtl/yifive/ycr1c"]
 	path = verilog/rtl/yifive/ycr1c
 	url = https://github.com/dineshannayya/ycr1cr.git
-[submodule "verilog/dv/common/riscduino_board1"]
+[submodule "verilog/dv/common/riscduino_board"]
 	path = verilog/dv/common/riscduino_board
 	url = https://github.com/dineshannayya/riscduino_board.git
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 774a95c..9b0d5f6 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -189,7 +189,7 @@
 set ::env(TAP_DECAP_INSERTION) 0
 set ::env(CLOCK_TREE_SYNTH) 0
 
-set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_LVS_ERROR) "1"
 set ::env(QUIT_ON_MAGIC_DRC) "0"
 set ::env(QUIT_ON_NEGATIVE_WNS) "0"
 set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/verilog/dv/agents/uart_agent.v b/verilog/dv/agents/uart_agent.v
index 9d647c8..c9f11b4 100644
--- a/verilog/dv/agents/uart_agent.v
+++ b/verilog/dv/agents/uart_agent.v
@@ -414,6 +414,81 @@
 
 endtask
 
+
+// Read Task without Timeout
+task read_char3;
+output [7:0]	rxd_data;
+reg	[7:0] rxd_data;
+integer i;
+reg 	[7:0] data;
+reg	parity;
+
+begin
+	data <= 8'h0;
+	parity <= 1;
+
+
+fork	
+   begin : loop_2
+
+// start cycle
+	@(negedge rxd) 
+	 read <= 1;
+
+// data cycle
+	@(posedge uart_rx_clk);
+	 for (i = 0; i < data_bit_number; i = i + 1)
+	  begin
+	    @(posedge uart_rx_clk)
+	    data[i] <=  rxd;
+	    parity <= parity ^ rxd;
+	  end		
+
+// parity cycle
+	if(control_setup.parity_en)
+	begin
+          @(posedge uart_rx_clk);
+	  if ((control_setup.even_odd_parity && (rxd == parity)) ||
+	     (!control_setup.even_odd_parity && (rxd != parity)))
+	     begin
+		$display ("%m: >>>>>  Parity Error");	
+ 		-> error_detected;
+		-> uart_parity_error;
+	     end
+	end
+
+// stop cycle 1
+        @(posedge uart_rx_clk);	
+	  if (!rxd)
+	     begin
+		$display ("%m: >>>>>  Stop signal 1 Error");	
+ 		-> error_detected;
+		-> uart_stop_error1;
+	     end
+
+// stop cycle 2
+	if (control_setup.stop_bit_number)
+	begin
+	      @(posedge uart_rx_clk);	// stop cycle 2
+		if (!rxd)
+		  begin
+		    $display ("%m: >>>>>  Stop signal 2 Error");	
+ 		    -> error_detected;
+		    -> uart_stop_error2;
+		  end
+	end
+
+	read <= 0;
+	-> uart_read_done;
+
+	rxd_data = data;
+   end
+join
+
+end
+
+endtask
+
 ////////////////////////////////////////////////////////////////////////////////
 task write_char;
 input [7:0] data;
diff --git a/verilog/dv/arudino_risc_boot/Makefile b/verilog/dv/arudino_risc_boot/Makefile
index 935f53e..6e6738d 100644
--- a/verilog/dv/arudino_risc_boot/Makefile
+++ b/verilog/dv/arudino_risc_boot/Makefile
@@ -27,6 +27,7 @@
 TOOLS?=/opt/riscv64i/
 
 export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?=  $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
 ## YIFIVE FIRMWARE
 YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
 GCC64_PREFIX?=riscv64-unknown-elf
diff --git a/verilog/dv/arudino_risc_boot/arudino_risc_boot.ino.cpp b/verilog/dv/arudino_risc_boot/arudino_risc_boot.ino.cpp
index 67dcf28..ca5efa0 100644
--- a/verilog/dv/arudino_risc_boot/arudino_risc_boot.ino.cpp
+++ b/verilog/dv/arudino_risc_boot/arudino_risc_boot.ino.cpp
@@ -1,5 +1,4 @@
 #include <Arduino.h>
-#line 1 "/tmp/.arduinoIDE-unsaved2022521-1233968-h2rhfb.1e1mr/sketch_jun21a/sketch_jun21a.ino"
 #define uint32_t  long
 
 #define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x10020000)
diff --git a/verilog/dv/firmware/crt.S b/verilog/dv/firmware/crt.S
index d50cb6b..c1ffa33 100644
--- a/verilog/dv/firmware/crt.S
+++ b/verilog/dv/firmware/crt.S
@@ -60,7 +60,7 @@
 
     // Timer init
     li      t0, mtime_ctrl
-    li      t1, (1 << YCR1_MTIME_CTRL_EN)   // enable, use internal clock
+    li      t1, (1 << YCR_MTIME_CTRL_EN)   // enable, use internal clock
     sw      t1, (t0)
     li      t0, mtime_div
     li      t1, (100-1)                     // divide by 100
diff --git a/verilog/dv/firmware/riscv_csr_encoding.h b/verilog/dv/firmware/riscv_csr_encoding.h
index 09f5abb..bf7736a 100644
--- a/verilog/dv/firmware/riscv_csr_encoding.h
+++ b/verilog/dv/firmware/riscv_csr_encoding.h
@@ -1486,4 +1486,4 @@
 DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT)
 #endif
 
-#include "ycr1_specific.h"
+#include "ycr_specific.h"
diff --git a/verilog/dv/firmware/sc_print.c b/verilog/dv/firmware/sc_print.c
index b736d42..f2a1192 100644
--- a/verilog/dv/firmware/sc_print.c
+++ b/verilog/dv/firmware/sc_print.c
@@ -20,16 +20,37 @@
 #include <stdarg.h>
 #include "sc_print.h"
 
-#define SC_SIM_OUTPORT (0xf0000000)
-#define CHAR_BIT (8)
+#define SC_SIM_OUTPORT            (0xf0000000)
+#define REG_MPRJ_UART_CTRL        (0x10010000)
+#define REG_MPRJ_UART_INTR_STAT   (0x10010004)
+#define REG_MPRJ_UART_BAUD_CTRL1  (0x10010008)
+#define REG_MPRJ_UART_BAUD_CTRL2  (0x1001000C)
+#define REG_MPRJ_UART_STAT        (0x10010010)
+#define REG_MPRJ_UART_TXDATA      (0x10010014)
+#define REG_MPRJ_UART_RXDATA      (0x10010018)
+#define REG_MPRJ_UART_TFIFO_STAT  (0x1001001C)
+#define REG_MPRJ_UART_RFIFO_STAT  (0x10010020)
 
-static void
-sc_puts(long str, long strlen) {
+#define CHAR_BIT (8)
+/**
+static void sc_puts(long str, long strlen) {
 	volatile char *out_ptr = (volatile char*)SC_SIM_OUTPORT;
 	const char *in_ptr = (const char*)str;
 	for (long len = strlen; len > 0; --len)
 	  *out_ptr = *in_ptr++;
 }
+**/
+static void sc_puts(long str, long strlen) {
+	volatile char *out_ptr = (volatile char*)REG_MPRJ_UART_TXDATA;
+	volatile char *status  = (volatile char*)REG_MPRJ_UART_STAT;
+	const char *in_ptr = (const char*)str;
+	for (long len = strlen; len > 0; --len) {
+	  //if((*status & 0x1) != 0x1) {  // check UART TX fifo is not full
+	   *out_ptr = *in_ptr++;
+          //}
+	}
+
+}
 
 #undef putchar
 int
diff --git a/verilog/dv/firmware/ycr_specific.h b/verilog/dv/firmware/ycr_specific.h
index 4c8c583..04201e5 100644
--- a/verilog/dv/firmware/ycr_specific.h
+++ b/verilog/dv/firmware/ycr_specific.h
@@ -16,8 +16,8 @@
 // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>           ////
 //////////////////////////////////////////////////////////////////////////////
 
-#ifndef __YCR1__SPECIFIC
-#define __YCR1__SPECIFIC
+#ifndef __YCR__SPECIFIC
+#define __YCR__SPECIFIC
 
 #define mcounten        0x7E0
 
@@ -29,10 +29,10 @@
 #define mtimecmp        0x0C490010
 #define mtimecmph       0x0C490014
 
-#define YCR1_MTIME_CTRL_EN          0
-#define YCR1_MTIME_CTRL_CLKSRC      1
+#define YCR_MTIME_CTRL_EN          0
+#define YCR_MTIME_CTRL_CLKSRC      1
 
-#define YCR1_MTIME_CTRL_WR_MASK     0x3
-#define YCR1_MTIME_DIV_WR_MASK      0x3FF
+#define YCR_MTIME_CTRL_WR_MASK     0x3
+#define YCR_MTIME_DIV_WR_MASK      0x3FF
 
 #endif // _YCR1__SPECIFIC
diff --git a/verilog/dv/user_risc_boot/run_iverilog b/verilog/dv/user_risc_boot/run_iverilog
index f083d6d..4b1efe0 100755
--- a/verilog/dv/user_risc_boot/run_iverilog
+++ b/verilog/dv/user_risc_boot/run_iverilog
@@ -16,17 +16,13 @@
 # // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
 # // //////////////////////////////////////////////////////////////////////////
 
-riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common  user_risc_boot.c -o user_risc_boot.o
+/home/dinesha/.arduino15/packages/riscduino/tools/riscv32-unknown-elf-gcc/3f7b3696217548bc31aeccf9a0c89bdfa4e16a8f/bin/riscv32-unknown-elf-g++ -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I../../../verilog/dv/firmware  user_risc_boot.c -o user_risc_boot.o
+/home/dinesha/.arduino15/packages/riscduino/tools/riscv32-unknown-elf-gcc/3f7b3696217548bc31aeccf9a0c89bdfa4e16a8f/bin/riscv32-unknown-elf-g++ -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I../../../verilog/dv/firmware  ../../../verilog/dv/firmware/crt.S -o crt.o
+/home/dinesha/.arduino15/packages/riscduino/tools/riscv32-unknown-elf-gcc/3f7b3696217548bc31aeccf9a0c89bdfa4e16a8f/bin/riscv32-unknown-elf-g++ -o user_risc_boot.elf -T ../../../verilog/dv/firmware/link.ld user_risc_boot.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+/home/dinesha/.arduino15/packages/riscduino/tools/riscv32-unknown-elf-gcc/3f7b3696217548bc31aeccf9a0c89bdfa4e16a8f/bin/riscv32-unknown-elf-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex
+/home/dinesha/.arduino15/packages/riscduino/tools/riscv32-unknown-elf-gcc/3f7b3696217548bc31aeccf9a0c89bdfa4e16a8f/bin/riscv32-unknown-elf-objcopy -D user_risc_boot.elf > user_risc_boot.dump
+rm crt.o user_risc_boot.o
 
-riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/  ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
-
-riscv64-unknown-elf-gcc -o user_risc_boot.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32
-
-riscv64-unknown-elf-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex
-
-riscv64-unknown-elf-objdump -D user_risc_boot.elf > user_risc_boot.dump
-
-rm crt_tcm.o user_risc_boot.o
 
 #iverilog with waveform dump
 iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH -I  ../../../caravel/verilog/rtl  -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_risc_boot_tb.v -o user_risc_boot_tb.vvp
diff --git a/verilog/dv/user_uart/user_uart.c b/verilog/dv/user_uart/user_uart.c
index 99e0204..4a82878 100644
--- a/verilog/dv/user_uart/user_uart.c
+++ b/verilog/dv/user_uart/user_uart.c
@@ -34,7 +34,8 @@
 
     while(1) {
        // Check UART RX fifo has data, if available loop back the data
-       if(reg_mprj_uart_reg8 != 0) { 
+       // Also check txfifo is not full
+       if((reg_mprj_uart_reg8 != 0) && ((reg_mprj_uart_reg4 & 0x1) != 0x1)) { 
 	   reg_mprj_uart_reg5 = reg_mprj_uart_reg6;
        }
     }
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c
index a7ce700..03ba3e8 160000
--- a/verilog/rtl/yifive/ycr1c
+++ b/verilog/rtl/yifive/ycr1c
@@ -1 +1 @@
-Subproject commit a7ce700b3004622c78c52c0ee22bf740bc6c86e5
+Subproject commit 03ba3e83768d0c61c3da561183aadf6d13418bc5