diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index a8d2721..61609a0 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -16,7 +16,6 @@
 # Base Configurations. Don't Touch
 # section begin
 
-set ::env(PDK) "sky130A"
 set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
 
 # YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS 
@@ -78,7 +77,7 @@
 	    $::env(DESIGN_DIR)/../../verilog/gl/ycr_iconnect.v \
 	    $::env(DESIGN_DIR)/../../verilog/gl/digital_pll.v \
 	    $::env(DESIGN_DIR)/../../verilog/rtl/sar_adc_10b/sar_adc_10b.v \
-	    $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+	    $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
 	    "
 
 set ::env(EXTRA_LEFS) "\
@@ -91,7 +90,7 @@
 	$lef_root/ycr_core_top.lef \
 	$lef_root/ycr_iconnect.lef \
 	$lef_root/digital_pll.lef \
-	$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
+	$::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
 	"
 
 set ::env(EXTRA_GDS_FILES) "\
@@ -104,7 +103,7 @@
 	$gds_root/ycr_core_top.gds \
 	$gds_root/ycr_iconnect.gds \
 	$gds_root/digital_pll.gds \
-	$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
+	$::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
 	"
 
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -181,9 +180,22 @@
 set ::env(QUIT_ON_NEGATIVE_WNS) "0"
 set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
-set ::env(FP_PDN_IRDROP) "0"
+
+set ::env(FP_PDN_IRDROP) "1"
 set ::env(FP_PDN_HORIZONTAL_HALO) "10"
 set ::env(FP_PDN_VERTICAL_HALO) "10"
+
+#
+
+set ::env(FP_PDN_CORE_RING_HOFFSET) {12.45}
+set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_HWIDTH) {3.1}
+
+set ::env(FP_PDN_CORE_RING_VOFFSET) {12.45}
+set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_VWIDTH) {3.1}
+
+
 set ::env(FP_PDN_VOFFSET) "5"
 set ::env(FP_PDN_VPITCH) "80"
 set ::env(FP_PDN_VSPACING) "15.5"
diff --git a/openlane/ycr_core_top/base.sdc b/openlane/ycr_core_top/base.sdc
index 5e26d19..f804cf0 100644
--- a/openlane/ycr_core_top/base.sdc
+++ b/openlane/ycr_core_top/base.sdc
@@ -4,7 +4,7 @@
 create_clock -name core_clk -period 10.0000 [get_ports {clk}]
 
 set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
 set_clock_uncertainty -hold  0.2500 [all_clocks]
 
 set ::env(SYNTH_TIMING_DERATE) 0.05
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl
index d669b67..ea5b60a 100644
--- a/openlane/ycr_core_top/config.tcl
+++ b/openlane/ycr_core_top/config.tcl
@@ -74,9 +74,9 @@
 ## Floorplan
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 550 950 "
+set ::env(DIE_AREA) "0 0 540 950 "
 
-set ::env(PL_TARGET_DENSITY) 0.42
+set ::env(PL_TARGET_DENSITY) 0.43
 set ::env(CELL_PAD) "4"
 
 ## Routing
diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION
index 078e9d2..d5588cd 100644
--- a/signoff/ycr_core_top/OPENLANE_VERSION
+++ b/signoff/ycr_core_top/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/ycr_core_top/PDK_SOURCES
+++ b/signoff/ycr_core_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/ycr_iconnect/OPENLANE_VERSION b/signoff/ycr_iconnect/OPENLANE_VERSION
index 6aa8d2d..d5588cd 100644
--- a/signoff/ycr_iconnect/OPENLANE_VERSION
+++ b/signoff/ycr_iconnect/OPENLANE_VERSION
@@ -1 +1 @@
-openlane f9b5781f5ef0bbdf39ab1c2bbd78be8db11b27f2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/ycr_iconnect/PDK_SOURCES b/signoff/ycr_iconnect/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/ycr_iconnect/PDK_SOURCES
+++ b/signoff/ycr_iconnect/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION
index 078e9d2..d5588cd 100644
--- a/signoff/ycr_intf/OPENLANE_VERSION
+++ b/signoff/ycr_intf/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/ycr_intf/PDK_SOURCES
+++ b/signoff/ycr_intf/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066