diff --git a/openlane/Makefile b/openlane/Makefile
index 48e5b4a..0dbb3a1 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -1 +1,85 @@
-../caravel/openlane/Makefile
\ No newline at end of file
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+BLOCKS = $(shell find * -maxdepth 0 -type d)
+CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
+CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
+
+OPENLANE_TAG ?= v0.15
+OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
+OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
+OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl"
+
+all: $(BLOCKS)
+
+$(CONFIG) :
+	@echo "Missing $@. Please create a configuration for that design"
+	@exit 1
+
+$(BLOCKS) : % : ./%/config.tcl FORCE
+ifeq ($(OPENLANE_ROOT),)
+	@echo "Please export OPENLANE_ROOT"
+	@exit 1
+endif
+ifeq ($(PDK_ROOT),)
+	@echo "Please export PDK_ROOT"
+	@exit 1
+endif
+	@echo "###############################################"
+	@sleep 1
+
+	@if [ -f ./$*/interactive.tcl ]; then\
+		docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(PWD)/..:/project \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
+	else\
+		docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(PWD)/..:/project \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
+	fi
+	mkdir -p ../signoff/$*/
+	cp $*/runs/$*/OPENLANE_VERSION ../signoff/$*/
+	cp $*/runs/$*/PDK_SOURCES ../signoff/$*/
+	cp $*/runs/$*/reports/final_summary_report.csv ../signoff/$*/
+
+.PHONY: openlane
+openlane:
+ifeq ($(OPENLANE_ROOT),)
+	@echo "Please export OPENLANE_ROOT"
+	@exit 1
+endif
+	git clone https://github.com/efabless/openlane.git --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
+		cd $(OPENLANE_ROOT) && \
+		make openlane
+
+FORCE:
+
+clean:
+	@echo "Use clean_all to clean everything :)"
+
+clean_all: $(CLEAN)
+
+$(CLEAN): clean-% :
+	rm -rf runs/$*
+	rm -rf ../gds/$**
+	rm -rf ../mag/$**
+	rm -rf ../lef/$**
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
new file mode 100755
index 0000000..f1d6458
--- /dev/null
+++ b/openlane/syntacore/config.tcl
@@ -0,0 +1,138 @@
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) scr1_top_axi
+
+# This is macro
+set ::env(DESIGN_IS_CORE) 0
+
+# Diode insertion
+	#  Spray
+set ::env(DIODE_INSERTION_STRATEGY) 0
+
+	# Smart-"ish"
+#set ::env(DIODE_INSERTION_STRATEGY) 3
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "clk"
+
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_top.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_core_top.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_dm.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc_synchronizer.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_clk_ctrl.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_scu.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc_shift_reg.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_dmi.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/primitives/scr1_reset_cells.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ifu.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_exu.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_mprf.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ialu.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_lsu.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_hdu.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_tdu.sv  \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv   \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_dmem_router.sv   \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_imem_router.sv   \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_tcm.sv   \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_timer.sv   \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_top_axi.sv   \
+	$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_mem_axi.sv "
+
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore_scr1/src/includes ]
+
+#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ]
+
+
+# Need blackbox for cells
+set ::env(SYNTH_READ_BLACKBOX_LIB) 0
+
+
+# Floorplanning
+# -------------
+
+# Fixed area and pin position
+set ::env(FP_SIZING) "absolute"
+#actual die area is 0 0 2920 3520, given 500 micron extra margin
+set ::env(DIE_AREA) [list 0.0 0.0 2000.0 1200.0]
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+# Halo around the Macros
+set ::env(FP_HORIZONTAL_HALO) 25
+set ::env(FP_VERTICAL_HALO) 20
+
+#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+
+
+
+# Placement
+# ---------
+
+set ::env(PL_TARGET_DENSITY) 0.40
+
+#set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro_placement.cfg
+
+
+# Routing
+# -------
+
+#| `ROUTING_CORES` | Specifies the number of threads to be used in TritonRoute. <br> (Default: `4`) |
+set ::env(ROUTING_CORES) 4
+
+#| `GLB_RT_ALLOW_CONGESTION` | Allow congestion in the resultign guides. 0 = false, 1 = true <br> (Default: `0`) |
+set ::env(GLB_RT_ALLOW_CONGESTION) 0
+
+# | `GLB_RT_MINLAYER` | The number of lowest layer to be used in routing. <br> (Default: `1`)|
+set ::env(GLB_RT_MINLAYER) 1
+
+# | `GLB_RT_MAXLAYER` | The number of highest layer to be used in routing. <br> (Default: `6`)|
+set ::env(GLB_RT_MAXLAYER) 6
+
+# Obstructions
+    # li1 over the SRAM areas
+	# met5 over the whole design
+#set ::env(GLB_RT_OBS) "li1 0.00 22.68 1748.00 486.24, li1 0.00 851.08 1748.00 486.24, met5 0.0 0.0 1748.0 1360.0"
+
+#| `ROUTING_OPT_ITERS` | Specifies the maximum number of optimization iterations during Detailed Routing in TritonRoute. <br> (Default: `64`) |
+set ::env(ROUTING_OPT_ITERS) "64"
+
+#| `GLOBAL_ROUTER` | Specifies which global router to use. Values: `fastroute` or `cugr`. <br> (Default: `fastroute`) |
+set ::env(GLOBAL_ROUTER) "fastroute"
+
+#| `DETAILED_ROUTER` | Specifies which detailed router to use. Values: `tritonroute`, `tritonroute_or`, or `drcu`. <br> (Default: `tritonroute`) |
+set ::env(DETAILED_ROUTER) "tritonroute"
+
+# DRC
+# ---
+
+
+set ::env(MAGIC_DRC_USE_GDS) 1
+
+
+# Tape Out
+# --------
+
+set ::env(MAGIC_ZEROIZE_ORIGIN) 0
+
+
+# Cell library specific config
+# ----------------------------
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+	source $filename
+}
diff --git a/openlane/syntacore/pin_order.cfg b/openlane/syntacore/pin_order.cfg
new file mode 100644
index 0000000..032b46c
--- /dev/null
+++ b/openlane/syntacore/pin_order.cfg
@@ -0,0 +1,115 @@
+#BUS_SORT
+#E
+clk
+cpu_rst_n
+irq_lines.*
+pwrup_rst_n
+rst_n
+rtc_clk
+soft_irq
+sys_rdc_qlfy_o
+sys_rst_n_o
+fuse_idcode.*
+fuse_mhartid.*
+
+#W
+tck
+tdi
+tdo
+tdo_en
+test_mode
+test_rst_n
+tms
+trst_n
+
+#S
+io_axi_imem_araddr.*
+io_axi_imem_arburst.*
+io_axi_imem_arcache.*
+io_axi_imem_arid.*
+io_axi_imem_arlen.*
+io_axi_imem_arlock
+io_axi_imem_arprot.*
+io_axi_imem_arqos.*
+io_axi_imem_arready
+io_axi_imem_arregion.*
+io_axi_imem_arsize.*
+io_axi_imem_aruser.*
+io_axi_imem_arvalid
+io_axi_imem_awaddr.*
+io_axi_imem_awburst.*
+io_axi_imem_awcache.*
+io_axi_imem_awid.*
+io_axi_imem_awlen.*
+io_axi_imem_awlock
+io_axi_imem_awprot.*
+io_axi_imem_awqos.*
+io_axi_imem_awready
+io_axi_imem_awregion.*
+io_axi_imem_awsize.*
+io_axi_imem_awuser.*
+io_axi_imem_awvalid
+io_axi_imem_bid.*
+io_axi_imem_bready
+io_axi_imem_bresp.*
+io_axi_imem_buser.*
+io_axi_imem_bvalid
+io_axi_imem_rdata.*
+io_axi_imem_rid.*
+io_axi_imem_rlast
+io_axi_imem_rready
+io_axi_imem_rresp.*
+io_axi_imem_ruser.*
+io_axi_imem_rvalid
+io_axi_imem_wdata.*
+io_axi_imem_wlast
+io_axi_imem_wready
+io_axi_imem_wstrb.*
+io_axi_imem_wuser.*
+io_axi_imem_wvalid
+
+io_axi_dmem_araddr.*
+io_axi_dmem_arburst.*
+io_axi_dmem_arid.*
+io_axi_dmem_arlen.*
+io_axi_dmem_arlock
+io_axi_dmem_arprot.*
+io_axi_dmem_arqos.*
+io_axi_dmem_arready
+io_axi_dmem_arregion.*
+io_axi_dmem_arsize.*
+io_axi_dmem_aruser.*
+io_axi_dmem_arvalid
+io_axi_dmem_arcache.*
+io_axi_dmem_awaddr.*
+io_axi_dmem_awburst.*
+io_axi_dmem_awid.*
+io_axi_dmem_awlen.*
+io_axi_dmem_awlock
+io_axi_dmem_awprot.*
+io_axi_dmem_awqos.*
+io_axi_dmem_awready
+io_axi_dmem_awregion.*
+io_axi_dmem_awsize.*
+io_axi_dmem_awuser.*
+io_axi_dmem_awvalid
+io_axi_dmem_awcache.*
+io_axi_dmem_bid.*
+io_axi_dmem_bready
+io_axi_dmem_bresp.*
+io_axi_dmem_buser.*
+io_axi_dmem_bvalid
+io_axi_dmem_rdata.*
+io_axi_dmem_rid.*
+io_axi_dmem_rlast
+io_axi_dmem_rready
+io_axi_dmem_rresp.*
+io_axi_dmem_ruser.*
+io_axi_dmem_rvalid
+io_axi_dmem_wdata.*
+io_axi_dmem_wlast
+io_axi_dmem_wready
+io_axi_dmem_wstrb.*
+io_axi_dmem_wuser.*
+io_axi_dmem_wvalid
+