diff --git a/openlane/Makefile b/openlane/Makefile
index 928af55..18c4a16 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -19,8 +19,8 @@
 CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
 CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
 
-OPENLANE_TAG = mpw3
-OPENLANE_IMAGE_NAME ?= dineshannayya/openlane:$(OPENLANE_TAG)
+OPENLANE_TAG = mpw4
+OPENLANE_IMAGE_NAME = dineshannayya/openlane:$(OPENLANE_TAG)
 OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
 OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
 
diff --git a/openlane/pinmux/interactive.tcl b/openlane/pinmux/interactive.tcl
new file mode 100644
index 0000000..b44b517
--- /dev/null
+++ b/openlane/pinmux/interactive.tcl
@@ -0,0 +1,219 @@
+#!/usr/bin/tclsh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# Copyright 2020 Efabless Corporation
+# Copyright 2020 Sylvain Munaut
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+package require openlane;
+
+
+proc run_placement_step {args} {
+    # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
+    # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
+    # set_def $pdndef
+    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+    }
+
+    run_placement
+}
+
+proc run_cts_step {args} {
+    # set_def $::env(opendp_result_file_tag).def
+    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+    }
+
+    run_cts
+    run_resizer_timing
+}
+
+proc run_routing_step {args} {
+    # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
+    # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
+    # set_def $resizerdef
+    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+    }
+    run_routing
+}
+
+proc run_diode_insertion_2_5_step {args} {
+    # set_def $::env(tritonRoute_result_file_tag).def
+    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+    }
+	if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+		run_antenna_check
+		heal_antenna_violators; # modifies the routed DEF
+	}
+
+}
+
+proc run_power_pins_insertion_step {args} {
+    # set_def $::env(tritonRoute_result_file_tag).def
+    if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
+        set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
+    }
+    if { $::env(LVS_INSERT_POWER_PINS) } {
+		write_powered_verilog
+		set_netlist $::env(lvs_result_file_tag).powered.v
+    }
+
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+    # set_def $::env(tritonRoute_result_file_tag).def
+    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+    }
+	if { $lvs_enabled } {
+		run_magic_spice_export
+		run_lvs; # requires run_magic_spice_export
+	}
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+    }
+	if { $drc_enabled } {
+		run_magic_drc
+		run_klayout_drc
+	}
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+    }
+	if { $antenna_check_enabled } {
+		run_antenna_check
+	}
+}
+
+proc run_flow {args} {
+       set script_dir [file dirname [file normalize [info script]]]
+
+		set options {
+		{-design required}
+		{-save_path optional}
+		{-no_lvs optional}
+	    {-no_drc optional}
+	    {-no_antennacheck optional}
+	}
+	set flags {-save}
+	parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
+
+	prep {*}$args
+
+        set LVS_ENABLED 1
+        set DRC_ENABLED 0
+        set ANTENNACHECK_ENABLED 1
+
+        set steps [dict create "synthesis" {run_synthesis "" } \
+                "floorplan" {run_floorplan ""} \
+                "placement" {run_placement_step ""} \
+                "cts" {run_cts_step ""} \
+                "routing" {run_routing_step ""}\
+                "diode_insertion" {run_diode_insertion_2_5_step ""} \
+                "power_pins_insertion" {run_power_pins_insertion_step ""} \
+                "gds_magic" {run_magic ""} \
+                "gds_drc_klayout" {run_klayout ""} \
+                "gds_xor_klayout" {run_klayout_gds_xor ""} \
+                "lvs" "run_lvs_step $LVS_ENABLED" \
+                "drc" "run_drc_step $DRC_ENABLED" \
+                "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
+                "cvc" {run_lef_cvc}
+        ]
+
+       set_if_unset arg_values(-to) "cvc";
+
+       if {  [info exists ::env(CURRENT_STEP) ] } {
+           puts "\[INFO\]:Picking up where last execution left off"
+           puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
+       } else {
+           set ::env(CURRENT_STEP) "synthesis";
+       }
+       set_if_unset arg_values(-from) $::env(CURRENT_STEP);
+       set exe 0;
+       dict for {step_name step_exe} $steps {
+           if { [ string equal $arg_values(-from) $step_name ] } {
+               set exe 1;
+           }
+
+           if { $exe } {
+               # For when it fails
+               set ::env(CURRENT_STEP) $step_name
+               [lindex $step_exe 0] [lindex $step_exe 1] ;
+           }
+
+           if { [ string equal $arg_values(-to) $step_name ] } {
+               set exe 0:
+               break;
+           }
+
+       }
+
+       # for when it resumes
+       set steps_as_list [dict keys $steps]
+       set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+       set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+	if {  [info exists flags_map(-save) ] } {
+		if { ! [info exists arg_values(-save_path)] } {
+			set arg_values(-save_path) ""
+		}
+		save_views 	-lef_path $::env(magic_result_file_tag).lef \
+			-def_path $::env(CURRENT_DEF) \
+			-gds_path $::env(magic_result_file_tag).gds \
+			-mag_path $::env(magic_result_file_tag).mag \
+			-maglef_path $::env(magic_result_file_tag).lef.mag \
+			-spice_path $::env(magic_result_file_tag).spice \
+			-spef_path $::env(CURRENT_SPEF) \
+			-verilog_path $::env(CURRENT_NETLIST) \
+			-save_path $arg_values(-save_path) \
+			-tag $::env(RUN_TAG)
+	}
+
+
+	calc_total_runtime
+	save_state
+	generate_final_summary_report
+	
+	check_timing_violations
+
+	puts_success "Flow Completed Without Fatal Errors."
+
+}
+
+run_flow {*}$argv
diff --git a/openlane/qspim/config.tcl b/openlane/qspim/config.tcl
index 192d47c..fc9f6f7 100755
--- a/openlane/qspim/config.tcl
+++ b/openlane/qspim/config.tcl
@@ -64,7 +64,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 650"
+set ::env(DIE_AREA) "0 0 400 550"
 
 set ::env(PL_TIME_DRIVEN) 1
 set ::env(PL_TARGET_DENSITY) "0.40"
diff --git a/openlane/qspim/interactive.tcl b/openlane/qspim/interactive.tcl
new file mode 100644
index 0000000..b44b517
--- /dev/null
+++ b/openlane/qspim/interactive.tcl
@@ -0,0 +1,219 @@
+#!/usr/bin/tclsh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# Copyright 2020 Efabless Corporation
+# Copyright 2020 Sylvain Munaut
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+package require openlane;
+
+
+proc run_placement_step {args} {
+    # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
+    # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
+    # set_def $pdndef
+    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+    }
+
+    run_placement
+}
+
+proc run_cts_step {args} {
+    # set_def $::env(opendp_result_file_tag).def
+    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+    }
+
+    run_cts
+    run_resizer_timing
+}
+
+proc run_routing_step {args} {
+    # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
+    # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
+    # set_def $resizerdef
+    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+    }
+    run_routing
+}
+
+proc run_diode_insertion_2_5_step {args} {
+    # set_def $::env(tritonRoute_result_file_tag).def
+    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+    }
+	if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+		run_antenna_check
+		heal_antenna_violators; # modifies the routed DEF
+	}
+
+}
+
+proc run_power_pins_insertion_step {args} {
+    # set_def $::env(tritonRoute_result_file_tag).def
+    if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
+        set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
+    }
+    if { $::env(LVS_INSERT_POWER_PINS) } {
+		write_powered_verilog
+		set_netlist $::env(lvs_result_file_tag).powered.v
+    }
+
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+    # set_def $::env(tritonRoute_result_file_tag).def
+    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+    }
+	if { $lvs_enabled } {
+		run_magic_spice_export
+		run_lvs; # requires run_magic_spice_export
+	}
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+    }
+	if { $drc_enabled } {
+		run_magic_drc
+		run_klayout_drc
+	}
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+    }
+	if { $antenna_check_enabled } {
+		run_antenna_check
+	}
+}
+
+proc run_flow {args} {
+       set script_dir [file dirname [file normalize [info script]]]
+
+		set options {
+		{-design required}
+		{-save_path optional}
+		{-no_lvs optional}
+	    {-no_drc optional}
+	    {-no_antennacheck optional}
+	}
+	set flags {-save}
+	parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
+
+	prep {*}$args
+
+        set LVS_ENABLED 1
+        set DRC_ENABLED 0
+        set ANTENNACHECK_ENABLED 1
+
+        set steps [dict create "synthesis" {run_synthesis "" } \
+                "floorplan" {run_floorplan ""} \
+                "placement" {run_placement_step ""} \
+                "cts" {run_cts_step ""} \
+                "routing" {run_routing_step ""}\
+                "diode_insertion" {run_diode_insertion_2_5_step ""} \
+                "power_pins_insertion" {run_power_pins_insertion_step ""} \
+                "gds_magic" {run_magic ""} \
+                "gds_drc_klayout" {run_klayout ""} \
+                "gds_xor_klayout" {run_klayout_gds_xor ""} \
+                "lvs" "run_lvs_step $LVS_ENABLED" \
+                "drc" "run_drc_step $DRC_ENABLED" \
+                "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
+                "cvc" {run_lef_cvc}
+        ]
+
+       set_if_unset arg_values(-to) "cvc";
+
+       if {  [info exists ::env(CURRENT_STEP) ] } {
+           puts "\[INFO\]:Picking up where last execution left off"
+           puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
+       } else {
+           set ::env(CURRENT_STEP) "synthesis";
+       }
+       set_if_unset arg_values(-from) $::env(CURRENT_STEP);
+       set exe 0;
+       dict for {step_name step_exe} $steps {
+           if { [ string equal $arg_values(-from) $step_name ] } {
+               set exe 1;
+           }
+
+           if { $exe } {
+               # For when it fails
+               set ::env(CURRENT_STEP) $step_name
+               [lindex $step_exe 0] [lindex $step_exe 1] ;
+           }
+
+           if { [ string equal $arg_values(-to) $step_name ] } {
+               set exe 0:
+               break;
+           }
+
+       }
+
+       # for when it resumes
+       set steps_as_list [dict keys $steps]
+       set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+       set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+	if {  [info exists flags_map(-save) ] } {
+		if { ! [info exists arg_values(-save_path)] } {
+			set arg_values(-save_path) ""
+		}
+		save_views 	-lef_path $::env(magic_result_file_tag).lef \
+			-def_path $::env(CURRENT_DEF) \
+			-gds_path $::env(magic_result_file_tag).gds \
+			-mag_path $::env(magic_result_file_tag).mag \
+			-maglef_path $::env(magic_result_file_tag).lef.mag \
+			-spice_path $::env(magic_result_file_tag).spice \
+			-spef_path $::env(CURRENT_SPEF) \
+			-verilog_path $::env(CURRENT_NETLIST) \
+			-save_path $arg_values(-save_path) \
+			-tag $::env(RUN_TAG)
+	}
+
+
+	calc_total_runtime
+	save_state
+	generate_final_summary_report
+	
+	check_timing_violations
+
+	puts_success "Flow Completed Without Fatal Errors."
+
+}
+
+run_flow {*}$argv
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index c5da11a..15b5632 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl
@@ -88,7 +88,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) [list 0.0 0.0 1250.0 900.0]
+set ::env(DIE_AREA) [list 0.0 0.0 1000.0 900.0]
 
 
 # If you're going to use multiple power domains, then keep this disabled.
@@ -98,7 +98,7 @@
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.30"
+set ::env(PL_TARGET_DENSITY) "0.35"
 
 # helps in anteena fix
 set ::env(USE_ARC_ANTENNA_CHECK) "0"
diff --git a/openlane/syntacore/interactive.tcl b/openlane/syntacore/interactive.tcl
index 33bd21b..b44b517 100644
--- a/openlane/syntacore/interactive.tcl
+++ b/openlane/syntacore/interactive.tcl
@@ -44,35 +44,6 @@
     run_resizer_timing
 }
 
-proc run_resizer_timing {args} {
-    if { $::env(PL_RESIZER_TIMING_OPTIMIZATIONS) == 1} {
-        puts_info "Running Resizer Timing Optimizations..."
-        TIMER::timer_start
-        set ::env(SAVE_DEF) [index_file $::env(resizer_tmp_file_tag)_timing.def 0]
-        set ::env(SAVE_SDC) [index_file $::env(resizer_tmp_file_tag)_timing.sdc 0]
-        try_catch $::env(OPENROAD_BIN) -exit $::env(SCRIPTS_DIR)/openroad/or_resizer_timing.tcl |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(resizer_log_file_tag)_timing_optimization.log 0]
-        set_def $::env(SAVE_DEF)
-        set ::env(CURRENT_SDC) $::env(SAVE_SDC)
-
-        TIMER::timer_stop
-        exec echo "[TIMER::get_runtime]" >> [index_file $::env(resizer_log_file_tag)_timing_optimization_runtime.txt 0]
-
-        write_verilog $::env(yosys_result_file_tag)_optimized.v
-        write_verilog $::env(yosys_result_file_tag)_resizer.v
-        set_netlist $::env(yosys_result_file_tag)_optimized.v
-
-        if { $::env(LEC_ENABLE) && [file exists $::env(PREV_NETLIST)] } {
-            logic_equiv_check -rhs $::env(PREV_NETLIST) -lhs $::env(CURRENT_NETLIST)
-        }
-
-        set output_log [index_file $::env(resizer_log_file_tag)_timing_optimization_sta 0] 
-        set runtime_log [index_file $::env(resizer_log_file_tag)_timing_optimization_sta_runtime.txt 0] 
-        run_sta -placement_parasitics -output_log $output_log -runtime_log $runtime_log 
-    } else {
-        puts_info "Skipping Resizer Timing Optimizations."
-    }
-}
-
 proc run_routing_step {args} {
     # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
     # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
@@ -85,117 +56,6 @@
     run_routing
 }
 
-proc run_routing {args} {
-    puts_info "Routing..."
-
-    # |----------------------------------------------------|
-    # |----------------   5. ROUTING ----------------------|
-    # |----------------------------------------------------|
-    set ::env(CURRENT_STAGE) routing
-
-	run_resizer_timing_routing
-	
-	if { [info exists ::env(DIODE_CELL)] && ($::env(DIODE_CELL) ne "") } {
-		if { ($::env(DIODE_INSERTION_STRATEGY) == 1) || ($::env(DIODE_INSERTION_STRATEGY) == 2) } {
-			ins_diode_cells_1
-		}
-		if { ($::env(DIODE_INSERTION_STRATEGY) == 4) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
-			ins_diode_cells_4
-		}
-    }
-
-	# if diode insertion does *not* happen as part of global routing, then
-	# we can insert fill cells early on
-	if { $::env(DIODE_INSERTION_STRATEGY) != 3 } {
-		ins_fill_cells
-	}
-
-    use_original_lefs
-
-    add_route_obs
-
-	#legalize if not yet legalized
-	if { ($::env(DIODE_INSERTION_STRATEGY) != 4) && ($::env(DIODE_INSERTION_STRATEGY) != 5) } {
-		detailed_placement_or
-	}
-	
-    global_routing
-
-	if { $::env(DIODE_INSERTION_STRATEGY) == 3 } {
-		# Doing this here can be problematic and is something that needs to be
-		# addressed in FastRoute since fill cells *might* occupy some of the
-		# resources that were already used during global routing causing the
-		# detailed router to suffer later.
-		ins_fill_cells
-	}
-
-    # for LVS
-    write_verilog $::env(yosys_result_file_tag)_preroute.v
-    set_netlist $::env(yosys_result_file_tag)_preroute.v
-    if { $::env(LEC_ENABLE) } {
-		logic_equiv_check -rhs $::env(PREV_NETLIST) -lhs $::env(CURRENT_NETLIST)
-    }
-
-
-    # detailed routing
-    detailed_routing
-	scrot_klayout -layout $::env(CURRENT_DEF)
-
-	# spef extraction at the three corners 
-	set ::env(SPEF_SLOWEST) [file rootname $::env(CURRENT_DEF)].ss.spef;
-	set ::env(SPEF_TYPICAL) [file rootname $::env(CURRENT_DEF)].tt.spef;
-	set ::env(SPEF_FASTEST) [file rootname $::env(CURRENT_DEF)].ff.spef;
-
-    run_spef_extraction -rcx_lib $::env(LIB_SYNTH_COMPLETE) -output_spef $::env(SPEF_TYPICAL)
-
-	# run sta at the typical corner using the extracted spef
-	set output_log [index_file $::env(rcx_log_file_tag)_extraction_sta 0] 
-	set runtime_log [index_file  $::env(rcx_log_file_tag)_extraction_sta_runtime.txt 0] 
-	set ::env(FINAL_TIMING_REPORT_TAG) [index_file $::env(rcx_report_file_tag)_extraction_sta 0]
-	set ::env(SAVE_SDF) [file rootname $::env(CURRENT_DEF)].sdf
-	run_sta -output_log $output_log -runtime_log $runtime_log 
-
-    run_spef_extraction -rcx_lib $::env(LIB_SLOWEST) -output_spef $::env(SPEF_SLOWEST)
-    run_spef_extraction -rcx_lib $::env(LIB_FASTEST) -output_spef $::env(SPEF_FASTEST)
-	
-	# run sta at the three corners 
-	set output_log [index_file $::env(rcx_log_file_tag)_extraction_multi_corner_sta 0] 
-	set runtime_log [index_file  $::env(rcx_log_file_tag)_extraction_multi_corner_sta_runtime.txt 0] 
-	run_sta -output_log $output_log -runtime_log $runtime_log -multi_corner
-
-	## Calculate Runtime To Routing
-	calc_total_runtime -status "Routing completed" -report $::env(REPORTS_DIR)/routed_runtime.txt
-}
-
-proc run_resizer_timing_routing {args} {
-    if { $::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) == 1} {
-        puts_info "Running Resizer Timing Optimizations..."
-        TIMER::timer_start
-        set ::env(SAVE_DEF) [index_file $::env(resizer_tmp_file_tag)_timing.def 0]
-	    set ::env(SAVE_SDC) [index_file $::env(resizer_tmp_file_tag)_timing.sdc 0]
-        try_catch $::env(OPENROAD_BIN) -exit $::env(SCRIPTS_DIR)/openroad/or_resizer_routing_timing.tcl |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(glb_resizer_log_file_tag)_timing_optimization.log 0]
-        set_def $::env(SAVE_DEF)
-		set ::env(CURRENT_SDC) $::env(SAVE_SDC)
-		
-        TIMER::timer_stop
-        exec echo "[TIMER::get_runtime]" >> [index_file $::env(resizer_log_file_tag)_timing_optimization_runtime.txt 0]
-
-        write_verilog $::env(yosys_result_file_tag)_optimized.v
-        write_verilog $::env(yosys_result_file_tag)_resizer_timing.v
-        set_netlist $::env(yosys_result_file_tag)_optimized.v
-
-        if { $::env(LEC_ENABLE) && [file exists $::env(PREV_NETLIST)] } {
-            logic_equiv_check -rhs $::env(PREV_NETLIST) -lhs $::env(CURRENT_NETLIST)
-        }
-
-		set output_log [index_file $::env(glb_resizer_log_file_tag)_timing_optimization_sta 0] 
-        set runtime_log  [index_file $::env(glb_resizer_log_file_tag)_timing_optimization_sta_runtime.txt 0] 
-        run_sta -placement_parasitics -output_log $output_log -runtime_log $runtime_log 
-    } else {
-        puts_info "Skipping Resizer Timing Optimizations."
-    }
-}
-
 proc run_diode_insertion_2_5_step {args} {
     # set_def $::env(tritonRoute_result_file_tag).def
     if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
diff --git a/openlane/syntacore/pin_order.cfg b/openlane/syntacore/pin_order.cfg
index 11940db..99853b7 100644
--- a/openlane/syntacore/pin_order.cfg
+++ b/openlane/syntacore/pin_order.cfg
@@ -232,7 +232,7 @@
 wbd_dmem_ack_i      
 wbd_dmem_err_i      
 
-irq_lines\[15\]     1000 0  2
+irq_lines\[15\]     800 0  2
 irq_lines\[14\]     
 irq_lines\[13\]     
 irq_lines\[12\]     
@@ -381,7 +381,7 @@
 sram_dout0\[1\]
 sram_dout0\[0\]
 
-sram_din0\[31\] 800 0  4
+sram_din0\[31\] 700 0  4
 sram_din0\[30\]
 sram_din0\[29\]
 sram_din0\[28\]
@@ -429,7 +429,7 @@
 sram_addr0\[1\]
 sram_addr0\[0\]
 
-sram_csb1             1000 0 4
+sram_csb1             900 0 4
 sram_addr1\[8\]
 sram_addr1\[7\]
 sram_addr1\[6\]
diff --git a/openlane/uart_i2cm_usb_spi/config.tcl b/openlane/uart_i2cm_usb_spi/config.tcl
index 24685b6..c23e79b 100644
--- a/openlane/uart_i2cm_usb_spi/config.tcl
+++ b/openlane/uart_i2cm_usb_spi/config.tcl
@@ -83,7 +83,7 @@
 
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 set ::env(FP_SIZING) "absolute"
-set ::env(DIE_AREA) [list 0.0 0.0 550.0 700.0]
+set ::env(DIE_AREA) [list 0.0 0.0 500.0 700.0]
 
 
 
@@ -111,9 +111,6 @@
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
-#To fix the metal density issue in tapeout check -recommded by jeffdi 
-#set ::env(DECAP_CELL) "sky130_ef_sc_hd__decap_12 sky130_fd_sc_hd__decap_3 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_8"
-
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"
 set ::env(QUIT_ON_LVS_ERROR) "0"
diff --git a/openlane/uart_i2cm_usb_spi/interactive.tcl b/openlane/uart_i2cm_usb_spi/interactive.tcl
new file mode 100644
index 0000000..b44b517
--- /dev/null
+++ b/openlane/uart_i2cm_usb_spi/interactive.tcl
@@ -0,0 +1,219 @@
+#!/usr/bin/tclsh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# Copyright 2020 Efabless Corporation
+# Copyright 2020 Sylvain Munaut
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+package require openlane;
+
+
+proc run_placement_step {args} {
+    # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
+    # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
+    # set_def $pdndef
+    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+    }
+
+    run_placement
+}
+
+proc run_cts_step {args} {
+    # set_def $::env(opendp_result_file_tag).def
+    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+    }
+
+    run_cts
+    run_resizer_timing
+}
+
+proc run_routing_step {args} {
+    # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
+    # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
+    # set_def $resizerdef
+    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+    }
+    run_routing
+}
+
+proc run_diode_insertion_2_5_step {args} {
+    # set_def $::env(tritonRoute_result_file_tag).def
+    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+    }
+	if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+		run_antenna_check
+		heal_antenna_violators; # modifies the routed DEF
+	}
+
+}
+
+proc run_power_pins_insertion_step {args} {
+    # set_def $::env(tritonRoute_result_file_tag).def
+    if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
+        set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
+    }
+    if { $::env(LVS_INSERT_POWER_PINS) } {
+		write_powered_verilog
+		set_netlist $::env(lvs_result_file_tag).powered.v
+    }
+
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+    # set_def $::env(tritonRoute_result_file_tag).def
+    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+    }
+	if { $lvs_enabled } {
+		run_magic_spice_export
+		run_lvs; # requires run_magic_spice_export
+	}
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+    }
+	if { $drc_enabled } {
+		run_magic_drc
+		run_klayout_drc
+	}
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+    }
+	if { $antenna_check_enabled } {
+		run_antenna_check
+	}
+}
+
+proc run_flow {args} {
+       set script_dir [file dirname [file normalize [info script]]]
+
+		set options {
+		{-design required}
+		{-save_path optional}
+		{-no_lvs optional}
+	    {-no_drc optional}
+	    {-no_antennacheck optional}
+	}
+	set flags {-save}
+	parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
+
+	prep {*}$args
+
+        set LVS_ENABLED 1
+        set DRC_ENABLED 0
+        set ANTENNACHECK_ENABLED 1
+
+        set steps [dict create "synthesis" {run_synthesis "" } \
+                "floorplan" {run_floorplan ""} \
+                "placement" {run_placement_step ""} \
+                "cts" {run_cts_step ""} \
+                "routing" {run_routing_step ""}\
+                "diode_insertion" {run_diode_insertion_2_5_step ""} \
+                "power_pins_insertion" {run_power_pins_insertion_step ""} \
+                "gds_magic" {run_magic ""} \
+                "gds_drc_klayout" {run_klayout ""} \
+                "gds_xor_klayout" {run_klayout_gds_xor ""} \
+                "lvs" "run_lvs_step $LVS_ENABLED" \
+                "drc" "run_drc_step $DRC_ENABLED" \
+                "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
+                "cvc" {run_lef_cvc}
+        ]
+
+       set_if_unset arg_values(-to) "cvc";
+
+       if {  [info exists ::env(CURRENT_STEP) ] } {
+           puts "\[INFO\]:Picking up where last execution left off"
+           puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
+       } else {
+           set ::env(CURRENT_STEP) "synthesis";
+       }
+       set_if_unset arg_values(-from) $::env(CURRENT_STEP);
+       set exe 0;
+       dict for {step_name step_exe} $steps {
+           if { [ string equal $arg_values(-from) $step_name ] } {
+               set exe 1;
+           }
+
+           if { $exe } {
+               # For when it fails
+               set ::env(CURRENT_STEP) $step_name
+               [lindex $step_exe 0] [lindex $step_exe 1] ;
+           }
+
+           if { [ string equal $arg_values(-to) $step_name ] } {
+               set exe 0:
+               break;
+           }
+
+       }
+
+       # for when it resumes
+       set steps_as_list [dict keys $steps]
+       set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+       set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+	if {  [info exists flags_map(-save) ] } {
+		if { ! [info exists arg_values(-save_path)] } {
+			set arg_values(-save_path) ""
+		}
+		save_views 	-lef_path $::env(magic_result_file_tag).lef \
+			-def_path $::env(CURRENT_DEF) \
+			-gds_path $::env(magic_result_file_tag).gds \
+			-mag_path $::env(magic_result_file_tag).mag \
+			-maglef_path $::env(magic_result_file_tag).lef.mag \
+			-spice_path $::env(magic_result_file_tag).spice \
+			-spef_path $::env(CURRENT_SPEF) \
+			-verilog_path $::env(CURRENT_NETLIST) \
+			-save_path $arg_values(-save_path) \
+			-tag $::env(RUN_TAG)
+	}
+
+
+	calc_total_runtime
+	save_state
+	generate_final_summary_report
+	
+	check_timing_violations
+
+	puts_success "Flow Completed Without Fatal Errors."
+
+}
+
+run_flow {*}$argv
diff --git a/openlane/uart_i2cm_usb_spi/pin_order.cfg b/openlane/uart_i2cm_usb_spi/pin_order.cfg
index 07237d6..860fa18 100644
--- a/openlane/uart_i2cm_usb_spi/pin_order.cfg
+++ b/openlane/uart_i2cm_usb_spi/pin_order.cfg
@@ -83,7 +83,7 @@
 reg_rdata\[0\]         
 reg_ack                
 
-cfg_cska_uart\[3\]     0500 0  2
+cfg_cska_uart\[3\]     0400 0  2
 cfg_cska_uart\[2\]
 cfg_cska_uart\[1\]
 cfg_cska_uart\[0\]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 1455224..a6ec28b 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -107,12 +107,15 @@
 
 ## Internal Macros
 ### Macro PDN Connections
-#set ::env(FP_PDN_ENABLE_MACROS_GRID) "0"
-#set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
+set ::env(FP_PDN_ENABLE_MACROS_GRID) "1"
+set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
 
 set ::env(VDD_NETS) "vccd1 vccd2 vdda1 vdda2"
 set ::env(GND_NETS) "vssd1 vssd2 vssa1 vssa2"
 
+set ::env(VDD_PIN) "vccd1 vccd2 vdda1 vdda2"
+set ::env(GND_PIN) "vssd1 vssd2 vssa1 vssa2"
+
 set ::env(GLB_RT_OBS) " li1  1200 200  1883.1 616.54,\
                         met1 1200 200  1883.1 616.54,\
 	                met2 1200 200  1883.1 616.54,\
@@ -120,7 +123,7 @@
 			met4 1200 200  1883.1 616.54,\
 	                met5 0 0 2920 3520"
 
-set ::env(FP_PDN_MACROS) "\
+set ::env(FP_PDN_MACRO_HOOKS) "\
 	u_adc vccd1 vssd1 \
 	u_adc vccd2 vssd2 \
 	u_intercon vccd1 vssd1 \
@@ -157,3 +160,7 @@
 set ::env(QUIT_ON_TR_DRC) "0"
 
 
+set ::env(FP_PDN_HPITCH) "140"
+set ::env(FP_PDN_VPITCH) "140"
+
+
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index b44b517..4483faf 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -121,6 +121,191 @@
 	}
 }
 
+proc gen_pdn {args} {
+    puts_info "Generating PDN..."
+    TIMER::timer_start
+	
+    set ::env(SAVE_DEF) [index_file $::env(pdn_tmp_file_tag).def]
+    set ::env(PGA_RPT_FILE) [index_file $::env(pdn_report_file_tag).pga.rpt]
+
+    try_catch $::env(OPENROAD_BIN) -exit $::env(SCRIPTS_DIR)/openroad/pdn.tcl \
+	|& tee $::env(TERMINAL_OUTPUT) [index_file $::env(pdn_log_file_tag).log 0]
+
+
+    TIMER::timer_stop
+    exec echo "[TIMER::get_runtime]" >> [index_file $::env(pdn_log_file_tag)_runtime.txt 0]
+
+	quit_on_unconnected_pdn_nodes
+
+    set_def $::env(SAVE_DEF)
+}
+
+proc run_power_grid_generation {args} {
+	if { [info exists ::env(VDD_NETS)] || [info exists ::env(GND_NETS)] } {
+		# they both must exist and be equal in length
+		# current assumption: they cannot have a common ground
+		if { ! [info exists ::env(VDD_NETS)] || ! [info exists ::env(GND_NETS)] } {
+			puts_err "VDD_NETS and GND_NETS must *both* either be defined or undefined"
+			return -code error
+		}
+		# standard cell power and ground nets are assumed to be the first net 
+		set ::env(VDD_PIN) [lindex $::env(VDD_NETS) 0]
+		set ::env(GND_PIN) [lindex $::env(GND_NETS) 0]
+	} elseif { [info exists ::env(SYNTH_USE_PG_PINS_DEFINES)] } {
+		set ::env(VDD_NETS) [list]
+		set ::env(GND_NETS) [list]
+		# get the pins that are in $yosys_tmp_file_tag.pg_define.v
+		# that are not in $yosys_result_file_tag.v
+		#
+		set full_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_tmp_file_tag).pg_define.v]
+		puts_info $full_pins
+
+		set non_pg_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_result_file_tag).v]
+		puts_info $non_pg_pins
+
+		# assumes the pins are ordered correctly (e.g., vdd1, vss1, vcc1, vss1, ...)
+		foreach {vdd gnd} $full_pins {
+			if { $vdd ne "" && $vdd ni $non_pg_pins } {
+				lappend ::env(VDD_NETS) $vdd
+			}
+			if { $gnd ne "" && $gnd ni $non_pg_pins } {
+				lappend ::env(GND_NETS) $gnd
+			}
+		}
+	} else {
+		set ::env(VDD_NETS) $::env(VDD_PIN)
+		set ::env(GND_NETS) $::env(GND_PIN)
+	}
+
+	puts_info "Power planning the following nets"
+	puts_info "Power: $::env(VDD_NETS)"
+	puts_info "Ground: $::env(GND_NETS)"
+
+	if { [llength $::env(VDD_NETS)] != [llength $::env(GND_NETS)] } {
+		puts_err "VDD_NETS and GND_NETS must be of equal lengths"
+		return -code error
+	}
+
+	# internal macros power connections 
+	if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} {
+		set macro_hooks [dict create]
+		set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
+		foreach pdn_hook $pdn_hooks {
+			set instance_name [lindex $pdn_hook 0]
+			set power_net [lindex $pdn_hook 1]
+			set ground_net [lindex $pdn_hook 2]
+			dict append macro_hooks $instance_name [subst {$power_net $ground_net}]
+		        set power_net_indx [lsearch $::env(VDD_NETS) $power_net]
+		        set ground_net_indx [lsearch $::env(GND_NETS) $ground_net]
+
+		        # make sure that the specified power domains exist.
+		        if { $power_net_indx == -1  || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } {
+		        	puts_err "Can't find $power_net and $ground_net domain. \
+		        	Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)." 
+		        } 
+		}
+		
+	}
+	
+	# generate multiple power grids per pair of (VDD,GND)
+	# offseted by WIDTH + SPACING
+	foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
+		set ::env(VDD_NET) $vdd
+		set ::env(GND_NET) $gnd
+	        puts_info "Connecting Power: $vdd & gnd to All internal macros."
+
+		# internal macros power connections
+		set ::env(FP_PDN_MACROS) ""
+		if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 } {
+			# if macros connections to power are explicitly set
+			# default behavoir macro pins will be connected to the first power domain
+			if { [info exists ::env(FP_PDN_MACRO_HOOKS)] } {
+				set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
+				foreach {instance_name hooks} $macro_hooks {
+					set power [lindex $hooks 0]
+					set ground [lindex $hooks 1]			 
+					if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } {
+						set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
+						puts_info "Connecting $instance_name to $power and $ground nets."
+						lappend ::env(FP_PDN_MACROS) $instance_name
+					}
+				}
+			} 
+		} else {
+			puts_warn "All internal macros will not be connected to power $vdd & $gnd."
+		}
+		
+		gen_pdn
+
+		set ::env(FP_PDN_ENABLE_RAILS) 0
+		set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
+
+		# allow failure until open_pdks is up to date...
+		catch {set ::env(FP_PDN_VOFFSET) [expr $::env(FP_PDN_VOFFSET)+$::env(FP_PDN_VWIDTH)+$::env(FP_PDN_VSPACING)]}
+		catch {set ::env(FP_PDN_HOFFSET) [expr $::env(FP_PDN_HOFFSET)+$::env(FP_PDN_HWIDTH)+$::env(FP_PDN_HSPACING)]}
+
+		catch {set ::env(FP_PDN_CORE_RING_VOFFSET) \
+			[expr $::env(FP_PDN_CORE_RING_VOFFSET)\
+			+2*($::env(FP_PDN_CORE_RING_VWIDTH)\
+			+max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
+		catch {set ::env(FP_PDN_CORE_RING_HOFFSET) [expr $::env(FP_PDN_CORE_RING_HOFFSET)\
+			+2*($::env(FP_PDN_CORE_RING_HWIDTH)+\
+			max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
+
+		puts "FP_PDN_VOFFSET: $::env(FP_PDN_VOFFSET)"
+		puts "FP_PDN_HOFFSET: $::env(FP_PDN_VOFFSET)"
+		puts "FP_PDN_CORE_RING_VOFFSET: $::env(FP_PDN_CORE_RING_VOFFSET)"
+		puts "FP_PDN_CORE_RING_HOFFSET: $::env(FP_PDN_CORE_RING_HOFFSET)"
+	}
+	set ::env(FP_PDN_ENABLE_RAILS) 1
+}
+
+
+proc run_floorplan {args} {
+		puts_info "Running Floorplanning..."
+		# |----------------------------------------------------|
+		# |----------------   2. FLOORPLAN   ------------------|
+		# |----------------------------------------------------|
+		#
+		# intial fp
+		init_floorplan
+
+
+		# place io
+		if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+				place_io_ol
+		} else {
+			if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+				place_io
+				global_placement_or
+				place_contextualized_io \
+					-lef $::env(FP_CONTEXT_LEF) \
+					-def $::env(FP_CONTEXT_DEF)
+			} else {
+				place_io
+			}
+		}
+
+		apply_def_template
+
+		if { [info exist ::env(EXTRA_LEFS)] } {
+			if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+				file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(TMP_DIR)/macro_placement.cfg
+				manual_macro_placement f
+			} else {
+				global_placement_or
+				basic_macro_placement
+			}
+		}
+
+		# tapcell
+		tap_decap_or
+		scrot_klayout -layout $::env(CURRENT_DEF)
+		# power grid generation
+		run_power_grid_generation
+}
+
+
 proc run_flow {args} {
        set script_dir [file dirname [file normalize [info script]]]
 
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index af6e802..bc47034 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -4,5 +4,5 @@
 u_riscv_top	        400	        800	        N
 u_sram_2kb              1200            200             N
 u_pinmux                2200            1600            N
-u_intercon              300             2325            N
+u_intercon              300             2350            N
 u_wb_host               300             300             N
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index b3ed6b0..b987a4d 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h12m1s,-1,51320.0,0.2,25660.0,30.79,658.71,5132,0,0,0,0,0,0,0,1,0,-1,-1,348810,53931,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,244475608.0,3.9,42.91,35.56,9.51,0.43,-1,3179,7916,495,5232,0,0,0,3823,0,0,0,0,0,0,0,4,1147,1169,12,278,2608,0,2886,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h15m41s,-1,51320.0,0.2,25660.0,30.79,695.11,5132,0,0,0,0,0,0,-1,1,0,-1,-1,344100,53314,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,244475608.0,3.9,42.41,35.28,8.88,0.72,-1,3179,7916,495,5232,0,0,0,3823,0,0,0,0,0,0,0,4,1147,1169,12,278,2608,0,2886,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim/final_summary_report.csv b/signoff/qspim/final_summary_report.csv
index 21e8204..e6c0759 100644
--- a/signoff/qspim/final_summary_report.csv
+++ b/signoff/qspim/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h10m47s,-1,54838.46153846153,0.26,27419.230769230766,31.76,699.41,7129,0,0,0,0,0,0,0,1,0,-1,-1,322179,64379,0.0,-2.5,-1,0.0,-1,0.0,-799.65,-1,0.0,-1,221472059.0,7.29,27.23,32.16,0.85,0.44,-1,5836,8788,495,3446,0,0,0,6886,0,0,0,0,0,0,0,4,1766,2187,21,460,3480,0,3940,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h8m55s,-1,64809.09090909091,0.22,32404.545454545456,37.66,681.69,7129,0,0,0,0,0,0,-1,1,0,-1,-1,318392,63729,0.0,-2.67,-1,0.0,-1,0.0,-819.01,-1,0.0,-1,216470544.0,12.44,34.1,35.23,1.44,0.85,-1,5836,8788,495,3446,0,0,0,6886,0,0,0,0,0,0,0,4,1766,2187,21,388,2940,0,3328,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index 4df26b1..5922abf 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,flow_completed,0h29m6s,-1,37152.0,1.125,18576.0,21.23,1211.49,20898,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,1365828,208131,-1.28,-17.65,-1,0.0,-1,-1532.9,-21172.88,-1,0.0,-1,1053833111.0,0.0,33.55,23.18,4.66,0.05,-1,18304,29655,1036,12280,0,0,0,21716,0,0,0,0,0,0,0,4,5144,5849,49,644,15552,0,16196,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,flow_completed,0h35m29s,-1,46440.0,0.9,23220.0,26.62,1189.66,20898,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,1305802,210415,-1.28,-16.34,-1,0.0,-1,-1532.9,-19449.86,-1,0.0,-1,974068194.0,0.4,36.26,30.68,5.68,0.54,-1,18304,29655,1036,12280,0,0,0,21716,0,0,0,0,0,0,0,4,5144,5849,49,644,12312,0,12956,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb_spi/final_summary_report.csv b/signoff/uart_i2cm_usb_spi/final_summary_report.csv
index 2ccd3e0..f174563 100644
--- a/signoff/uart_i2cm_usb_spi/final_summary_report.csv
+++ b/signoff/uart_i2cm_usb_spi/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow_completed,0h18m44s,-1,58368.83116883117,0.385,29184.415584415587,34.12,803.55,11236,0,0,0,0,0,0,0,1,0,-1,-1,464724,99892,-4.36,-4.76,-1,-5.28,-1,-136.52,-146.69,-1,-157.95,-1,264425246.0,0.19,29.86,27.65,1.81,0.63,-1,8583,12990,1537,5887,0,0,0,9761,0,0,0,0,0,0,0,4,2731,2697,24,498,5145,0,5643,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.45,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow_completed,0h18m42s,-1,64205.71428571429,0.35,32102.857142857145,37.64,817.74,11236,0,0,0,0,0,0,-1,1,0,-1,-1,448590,98997,-4.36,-4.77,-1,-4.64,-1,-136.52,-148.03,-1,-140.88,-1,266589420.0,0.0,31.08,30.38,1.28,0.32,-1,8583,12990,1537,5887,0,0,0,9761,0,0,0,0,0,0,0,4,2731,2697,24,498,4643,0,5141,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.45,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 4ad66b7..707b3cf 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h16m49s,-1,1.5566625155666252,10.2784,0.7783312577833126,-1,513.23,8,0,0,0,0,0,0,-1,0,0,-1,-1,1336611,5469,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,1.71,4.92,0.64,0.89,-1,164,1798,164,1798,0,0,0,8,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h16m37s,-1,1.5566625155666252,10.2784,0.7783312577833126,-1,525.17,8,0,0,0,0,0,0,-1,0,0,-1,-1,1352380,5198,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,50744.38,1.67,4.74,0.68,0.97,-1,164,1798,164,1798,0,0,0,8,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,140,140,0.55,0.0,sky130_fd_sc_hd,4,0