diff --git a/checks/full_log.log b/checks/full_log.log
index 26e484c..41c487f 100644
--- a/checks/full_log.log
+++ b/checks/full_log.log
@@ -3,20 +3,16 @@
 Step 0 done without fatal errors.
  Executing Step 1 of 8: Project License Check
 {{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
- No third party libraries found.
-Step 1 done without fatal errors.
-{{SPDX COMPLIANCE WARNING}} Found 527 non-compliant files with the SPDX Standard. Check full log for more information
-SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/dinesha/workarea/opencore/git/yifive_r0/read.me', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/openlane/user_analog_project_wrapper_empty/or_ioplace.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/tbuart.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/spiflash.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/simpleuart.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/picorv32.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/mgmt_soc.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/spimemio.v', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/default.cvcrc', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/config.1.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/config.tcl']
+ SPDX COMPLIANCE Found 2 non-compliant files with the SPDX Standard. Check full log for more information
+SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/dinesha/workarea/opencore/git/yifive_r0/README.md', '/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/README.md']
  Executing Step 2 of 8: YAML File Check
  YAML file valid!
 Step 2 done without fatal errors.
  Detected Project Type is "digital"
  Executing Step 3 of 8: Project Compliance Checks
-b'Going into /home/dinesha/workarea/efabless/caravel'
+b'Going into /home/dinesha/workarea/opencore/git/yifive_r0/caravel'
 b'Removing manifest'
 b'Fetching manifest'
 b'Running sha1sum checks'
- Manifest Checks Failed. Please rebase your Repository to the latest Caravel master.
-verilog/rtl/mgmt_core.v: FAILED
-verilog/rtl/mgmt_soc.v: FAILED
-verilog/rtl/wb_intercon.v: FAILED
+ Manifest Checks Passed. Caravel Version Matches.
+ Makefile Checks Passed.
diff --git a/checks/manifest_check.log b/checks/manifest_check.log
index 94c2d81..13005a7 100644
--- a/checks/manifest_check.log
+++ b/checks/manifest_check.log
@@ -21,10 +21,10 @@
 verilog/rtl/housekeeping_spi.v: OK
 verilog/rtl/la_wb.v: OK
 verilog/rtl/mem_wb.v: OK
-verilog/rtl/mgmt_core.v: FAILED
+verilog/rtl/mgmt_core.v: OK
 verilog/rtl/mgmt_protect.v: OK
 verilog/rtl/mgmt_protect_hv.v: OK
-verilog/rtl/mgmt_soc.v: FAILED
+verilog/rtl/mgmt_soc.v: OK
 verilog/rtl/mprj2_logic_high.v: OK
 verilog/rtl/mprj_ctrl.v: OK
 verilog/rtl/mprj_io.v: OK
@@ -41,7 +41,7 @@
 verilog/rtl/storage.v: OK
 verilog/rtl/storage_bridge_wb.v: OK
 verilog/rtl/sysctrl.v: OK
-verilog/rtl/wb_intercon.v: FAILED
+verilog/rtl/wb_intercon.v: OK
 scripts/set_user_id.py: OK
 scripts/generate_fill.py: OK
 scripts/compositor.py: OK
diff --git a/checks/spdx_compliance_report.log b/checks/spdx_compliance_report.log
index 0f040f1..ac9524b 100644
--- a/checks/spdx_compliance_report.log
+++ b/checks/spdx_compliance_report.log
@@ -1,529 +1,4 @@
 FULL RUN LOG:
 SPDX NON-COMPLIANT FILES
-/home/dinesha/workarea/opencore/git/yifive_r0/read.me
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/openlane/user_analog_project_wrapper_empty/or_ioplace.tcl
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/tbuart.v
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/spiflash.v
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/simpleuart.v
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/picorv32.v
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/mgmt_soc.v
-/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/spimemio.v
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/default.cvcrc
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/config.1.tcl
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/config.tcl
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/config.tcl
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic_spice.tcl
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/opt.lib
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/trimmed.lib
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/tracks_copy.info
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/synthesis/hierarchy.dot
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/synthesis/yosys.sdc
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/20-tritonRoute.param
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/20-tritonRoute.guide
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/17-fastroute.guide
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__conb_1.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__nor2_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__and2_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__a21oi_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__fill_2.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__a32o_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__or2_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__clkbuf_16.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__decap_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__diode_2.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__buf_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__buf_8.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__nand2_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__a211o_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__a21o_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__a21boi_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__buf_2.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__or3_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__decap_12.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/scr1_top_wb.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__a2bb2o_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__and4_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__decap_3.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__o21ai_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__a22oi_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__dfrtp_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__dfxtp_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__tapvpwrvgnd_1.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__a2111o_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__fill_1.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__clkbuf_1.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__o32a_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__decap_6.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__or4_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__a21bo_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__decap_8.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__inv_2.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__o21a_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__o22a_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__and3_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__dfstp_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/lvs/setup_file.lef.lvs
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/runtime_summary_report.rpt.parsable
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/runtime_summary_report.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/manufacturability_report.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/1-yosys_4.chk.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/2-opensta.min_max.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/1-yosys_pre.stat
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/2-opensta_tns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/11-opensta_post_openphysyn.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/11-opensta_post_openphysyn_tns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/1-yosys_dff.stat
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/23-opensta_spef_tns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/23-opensta_spef.min_max.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/11-opensta_post_openphysyn.min_max.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/11-opensta_post_openphysyn.timing.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/23-opensta_spef.timing.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/2-opensta_wns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/2-opensta.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/23-opensta_spef_wns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/2-opensta.timing.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/23-opensta_spef.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/11-opensta_post_openphysyn_wns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/1-yosys_4.stat.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/routing/41-antenna.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/routing/20-tritonRoute.klayout.xml
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/magic/38-magic.drc.klayout.xml
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/floorplan/3-verilog2def.die_area.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/floorplan/3-verilog2def.core_area.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/klayout/35-klayout.xor.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/klayout/33-klayout.xor.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/placement/9-openphysyn_allchecks.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/placement/9-openphysyn_tns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/placement/9-openphysyn_wns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/results/synthesis/scr1_top_wb.synthesis_preroute.v
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/results/synthesis/scr1_top_wb.synthesis.v
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/results/synthesis/scr1_top_wb.synthesis_cts.v
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/results/synthesis/scr1_top_wb.synthesis_optimized.v
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-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__a21boi_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__buf_2.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__or3_4.ext
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-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__a2bb2o_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__and4_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__decap_3.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__o21ai_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__a22oi_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__dfrtp_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__dfxtp_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__tapvpwrvgnd_1.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__fill_1.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__clkbuf_1.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__o32a_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__decap_6.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__or4_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__a21bo_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sdrc_top.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__decap_8.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__inv_2.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__o21a_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__o22a_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__and3_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/magic/sky130_fd_sc_hd__dfstp_4.ext
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/tmp/lvs/setup_file.lef.lvs
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/runtime_summary_report.rpt.parsable
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/runtime_summary_report.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/manufacturability_report.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/1-yosys_4.chk.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/2-opensta.min_max.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/1-yosys_pre.stat
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/2-opensta_tns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/11-opensta_post_openphysyn.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/11-opensta_post_openphysyn_tns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/1-yosys_dff.stat
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/23-opensta_spef_tns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/23-opensta_spef.min_max.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/11-opensta_post_openphysyn.min_max.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/11-opensta_post_openphysyn.timing.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/23-opensta_spef.timing.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/2-opensta_wns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/2-opensta.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/23-opensta_spef_wns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/2-opensta.timing.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/23-opensta_spef.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/11-opensta_post_openphysyn_wns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/synthesis/1-yosys_4.stat.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/routing/41-antenna.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/routing/20-tritonRoute.klayout.xml
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/magic/38-magic.drc.klayout.xml
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/floorplan/3-verilog2def.die_area.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/floorplan/3-verilog2def.core_area.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/klayout/35-klayout.xor.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/klayout/33-klayout.xor.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/placement/9-openphysyn_allchecks.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/placement/9-openphysyn_tns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/placement/9-openphysyn_wns.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/reports/placement/9-openphysyn_violators.rpt
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/synthesis/sdrc_top.synthesis_optimized.v
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/synthesis/sdrc_top.synthesis_cts.v
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/synthesis/sdrc_top.synthesis.v
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/synthesis/sdrc_top.synthesis_preroute.v
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/cvc/sdrc_top.power
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/cvc/cvc_sdrc_top.debug
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/cvc/cvc_sdrc_top.error
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/cvc/sdrc_top.cdl
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/routing/sdrc_top.spef
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/routing/sdrc_top.def.ref
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/magic/.magicrc
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/lvs/sdrc_top.lvs.powered.v
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/lvs/sdrc_top.lvs.lef.json
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/klayout/sdrc_top.xor.xml
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/results/klayout/sdrc_top.lyp
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/logs/synthesis/23-opensta_spef
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/logs/synthesis/2-opensta
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/sdram/runs/sdram/logs/synthesis/11-opensta_post_openphysyn
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/risc_boot/risc_boot_tb.v
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/risc_boot/run_iverilog
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/user_risc_boot/user_risc_boot.dump
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/user_risc_boot/user_risc_boot.c
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/user_risc_boot/user_risc_boot_tb.v
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/user_risc_boot/run_iverilog
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/Makefile
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/src/core.files
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/src/ahb_top.files
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/src/run_modemsim
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/src/axi_top.files
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/src/wb_top.files
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/synth/Makefile
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/synth/run_synth
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/synth/synth.tcl
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/sim/tests/common/reloc.h
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_macros.h
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_csr_encoding.h
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/sim/tests/common/scr1_specific.h
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/lib/wb_interface.v
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/lib/clk_ctl.v
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/lib/wb_crossbar.v
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/lib/async_fifo.sv
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/lib/registers.v
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/lib/sync_fifo.sv
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/sdram_ctrl/src/run_modelsim
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/sdram_ctrl/src/filelist_rtl.f
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/wb_interconnect/src/wb_arb.sv
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/spi_master/src/spim_fifo.sv
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/spi_master/src/filelist.f
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/spi_master/src/spim_top.sv
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/spi_master/src/spim_ctrl.sv
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/spi_master/src/spim_clkgen.sv
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/spi_master/src/spim_regs.sv
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/spi_master/src/spim_tx.sv
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/spi_master/src/spim_rx.sv
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/spi_master/synth/Makefile
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/spi_master/synth/synth.tcl
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/digital_core/run_modelsim
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/digital_core/filelist_rtl.f
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/digital_core/src/glbl_cfg.sv
-/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/digital_core/src/digital_core.sv
+/home/dinesha/workarea/opencore/git/yifive_r0/README.md
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/README.md
diff --git a/openlane/glbl_cfg/base.sdc b/openlane/glbl_cfg/base.sdc
index d57972b..0941e88 100644
--- a/openlane/glbl_cfg/base.sdc
+++ b/openlane/glbl_cfg/base.sdc
@@ -1,3 +1,20 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
 set_units -time ns
 set ::env(WB_CLOCK_PERIOD) "10"
 set ::env(WB_CLOCK_PORT) "mclk"
diff --git a/openlane/glbl_cfg/config.tcl b/openlane/glbl_cfg/config.tcl
index bbdfe91..4848c00 100755
--- a/openlane/glbl_cfg/config.tcl
+++ b/openlane/glbl_cfg/config.tcl
@@ -1,3 +1,19 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
 # Global
 # ------
 
diff --git a/openlane/sdram/base.sdc b/openlane/sdram/base.sdc
index 117c0f4..aa200dd 100644
--- a/openlane/sdram/base.sdc
+++ b/openlane/sdram/base.sdc
@@ -1,3 +1,20 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
 set_units -time ns
 set ::env(WB_CLOCK_PERIOD) "10"
 set ::env(WB_CLOCK_PORT)   "wb_clk_i"
diff --git a/openlane/sdram/config.tcl b/openlane/sdram/config.tcl
index bea0aba..b35501d 100755
--- a/openlane/sdram/config.tcl
+++ b/openlane/sdram/config.tcl
@@ -1,3 +1,19 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
 # Global
 # ------
 
diff --git a/openlane/spi_master/base.sdc b/openlane/spi_master/base.sdc
index af8edee..fa507c1 100644
--- a/openlane/spi_master/base.sdc
+++ b/openlane/spi_master/base.sdc
@@ -1,3 +1,20 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
 set_units -time ns
 set ::env(WB_CLOCK_PERIOD) "10"
 set ::env(WB_CLOCK_PORT) "mclk"
diff --git a/openlane/spi_master/config.tcl b/openlane/spi_master/config.tcl
index 6e48edb..45d0586 100755
--- a/openlane/spi_master/config.tcl
+++ b/openlane/spi_master/config.tcl
@@ -1,3 +1,19 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
 # Global
 # ------
 
diff --git a/openlane/syntacore/base.sdc b/openlane/syntacore/base.sdc
index 5271f33..ec80763 100644
--- a/openlane/syntacore/base.sdc
+++ b/openlane/syntacore/base.sdc
@@ -1,3 +1,20 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
 set_units -time ns
 #Wishbone Clock
 set ::env(WB_CLOCK_PERIOD)    "10"
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index 7daaadb..c23dcc5 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl
@@ -1,3 +1,19 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
 # Global
 # ------
 
diff --git a/openlane/uart/base.sdc b/openlane/uart/base.sdc
index 1eab2c3..c93fb52 100644
--- a/openlane/uart/base.sdc
+++ b/openlane/uart/base.sdc
@@ -1,3 +1,20 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
 set_units -time ns
 set ::env(CORE_CLOCK_PERIOD) "10"
 set ::env(CORE_CLOCK_PORT)   "app_clk"
diff --git a/openlane/uart/config.tcl b/openlane/uart/config.tcl
index e48f62c..51088e3 100644
--- a/openlane/uart/config.tcl
+++ b/openlane/uart/config.tcl
@@ -1,3 +1,19 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
 # Global
 # ------
 
diff --git a/openlane/user_project_wrapper/base.sdc b/openlane/user_project_wrapper/base.sdc
index 97e8ab3..ea5f7ca 100644
--- a/openlane/user_project_wrapper/base.sdc
+++ b/openlane/user_project_wrapper/base.sdc
@@ -1,3 +1,20 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
 set_units -time ns
 set ::env(WB_CLOCK_PERIOD) "10"
 set ::env(WB_CLOCK_PORT)   "wb_clk_i"
diff --git a/openlane/user_project_wrapper/macro/bb/sdram.v b/openlane/user_project_wrapper/macro/bb/sdram.v
deleted file mode 100644
index 2beba06..0000000
--- a/openlane/user_project_wrapper/macro/bb/sdram.v
+++ /dev/null
@@ -1,84 +0,0 @@
-module sdrc_top (cfg_sdr_en,
-    sdr_cas_n,
-    sdr_cke,
-    sdr_cs_n,
-    sdr_den_n,
-    sdr_dqm,
-    sdr_init_done,
-    sdr_ras_n,
-    sdr_we_n,
-    sdram_clk,
-    sdram_pad_clk,
-    sdram_resetn,
-    wb_ack_o,
-    wb_clk_i,
-    wb_cyc_i,
-    wb_rst_i,
-    wb_stb_i,
-    wb_we_i,
-    VPWR,
-    VGND,
-    cfg_colbits,
-    cfg_req_depth,
-    cfg_sdr_cas,
-    cfg_sdr_mode_reg,
-    cfg_sdr_rfmax,
-    cfg_sdr_rfsh,
-    cfg_sdr_tras_d,
-    cfg_sdr_trcar_d,
-    cfg_sdr_trcd_d,
-    cfg_sdr_trp_d,
-    cfg_sdr_twr_d,
-    cfg_sdr_width,
-    pad_sdr_din,
-    sdr_addr,
-    sdr_ba,
-    sdr_dout,
-    wb_addr_i,
-    wb_cti_i,
-    wb_dat_i,
-    wb_dat_o,
-    wb_sel_i);
- input cfg_sdr_en;
- output sdr_cas_n;
- output sdr_cke;
- output sdr_cs_n;
- output sdr_den_n;
- output sdr_dqm;
- output sdr_init_done;
- output sdr_ras_n;
- output sdr_we_n;
- input sdram_clk;
- input sdram_pad_clk;
- input sdram_resetn;
- output wb_ack_o;
- input wb_clk_i;
- input wb_cyc_i;
- input wb_rst_i;
- input wb_stb_i;
- input wb_we_i;
- input VPWR;
- input VGND;
- input [1:0] cfg_colbits;
- input [1:0] cfg_req_depth;
- input [2:0] cfg_sdr_cas;
- input [12:0] cfg_sdr_mode_reg;
- input [2:0] cfg_sdr_rfmax;
- input [11:0] cfg_sdr_rfsh;
- input [3:0] cfg_sdr_tras_d;
- input [3:0] cfg_sdr_trcar_d;
- input [3:0] cfg_sdr_trcd_d;
- input [3:0] cfg_sdr_trp_d;
- input [3:0] cfg_sdr_twr_d;
- input [1:0] cfg_sdr_width;
- input [7:0] pad_sdr_din;
- output [12:0] sdr_addr;
- output [1:0] sdr_ba;
- output [7:0] sdr_dout;
- input [31:0] wb_addr_i;
- input [2:0] wb_cti_i;
- input [31:0] wb_dat_i;
- output [31:0] wb_dat_o;
- input [3:0] wb_sel_i;
-
-endmodule
diff --git a/openlane/user_project_wrapper/macro/bb/syntacore.v b/openlane/user_project_wrapper/macro/bb/syntacore.v
deleted file mode 100644
index 4e1c7db..0000000
--- a/openlane/user_project_wrapper/macro/bb/syntacore.v
+++ /dev/null
@@ -1,62 +0,0 @@
-module scr1_top_wb (core_clk,
-    cpu_rst_n,
-    pwrup_rst_n,
-    rst_n,
-    rtc_clk,
-    soft_irq,
-    test_mode,
-    test_rst_n,
-    wb_clk,
-    wb_rst_n,
-    wbd_dmem_ack_i,
-    wbd_dmem_err_i,
-    wbd_dmem_stb_o,
-    wbd_dmem_we_o,
-    wbd_imem_ack_i,
-    wbd_imem_err_i,
-    wbd_imem_stb_o,
-    wbd_imem_we_o,
-    VPWR,
-    VGND,
-    fuse_mhartid,
-    irq_lines,
-    wbd_dmem_adr_o,
-    wbd_dmem_dat_i,
-    wbd_dmem_dat_o,
-    wbd_dmem_sel_o,
-    wbd_imem_adr_o,
-    wbd_imem_dat_i,
-    wbd_imem_dat_o,
-    wbd_imem_sel_o);
- input core_clk;
- input cpu_rst_n;
- input pwrup_rst_n;
- input rst_n;
- input rtc_clk;
- input soft_irq;
- input test_mode;
- input test_rst_n;
- input wb_clk;
- input wb_rst_n;
- input wbd_dmem_ack_i;
- input wbd_dmem_err_i;
- output wbd_dmem_stb_o;
- output wbd_dmem_we_o;
- input wbd_imem_ack_i;
- input wbd_imem_err_i;
- output wbd_imem_stb_o;
- output wbd_imem_we_o;
- input VPWR;
- input VGND;
- input [31:0] fuse_mhartid;
- input [15:0] irq_lines;
- output [31:0] wbd_dmem_adr_o;
- input [31:0] wbd_dmem_dat_i;
- output [31:0] wbd_dmem_dat_o;
- output [3:0] wbd_dmem_sel_o;
- output [31:0] wbd_imem_adr_o;
- input [31:0] wbd_imem_dat_i;
- output [31:0] wbd_imem_dat_o;
- output [3:0] wbd_imem_sel_o;
-
-endmodule
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index d7c4471..56efc5b 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -1,3 +1,19 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
 # Global
 # ------
 
diff --git a/openlane/wb_interconnect/base.sdc b/openlane/wb_interconnect/base.sdc
index 1ef8a54..6cadf2f 100644
--- a/openlane/wb_interconnect/base.sdc
+++ b/openlane/wb_interconnect/base.sdc
@@ -1,3 +1,21 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+
 set_units -time ns
 set ::env(CLOCK_PERIOD) "10"
 set ::env(CLOCK_PORT) "clk_i"
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 9fcb282..6d95cff 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -1,3 +1,19 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
 # Global
 # ------
 
diff --git a/openlane/yifive/config.tcl b/openlane/yifive/config.tcl
index 2dee262..1787f12 100644
--- a/openlane/yifive/config.tcl
+++ b/openlane/yifive/config.tcl
@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -12,6 +12,8 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 # SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
 
 set script_dir [file dirname [file normalize [info script]]]
 
diff --git a/openlane/yifive/macro/bb/sdram.v b/openlane/yifive/macro/bb/sdram.v
deleted file mode 100644
index 2beba06..0000000
--- a/openlane/yifive/macro/bb/sdram.v
+++ /dev/null
@@ -1,84 +0,0 @@
-module sdrc_top (cfg_sdr_en,
-    sdr_cas_n,
-    sdr_cke,
-    sdr_cs_n,
-    sdr_den_n,
-    sdr_dqm,
-    sdr_init_done,
-    sdr_ras_n,
-    sdr_we_n,
-    sdram_clk,
-    sdram_pad_clk,
-    sdram_resetn,
-    wb_ack_o,
-    wb_clk_i,
-    wb_cyc_i,
-    wb_rst_i,
-    wb_stb_i,
-    wb_we_i,
-    VPWR,
-    VGND,
-    cfg_colbits,
-    cfg_req_depth,
-    cfg_sdr_cas,
-    cfg_sdr_mode_reg,
-    cfg_sdr_rfmax,
-    cfg_sdr_rfsh,
-    cfg_sdr_tras_d,
-    cfg_sdr_trcar_d,
-    cfg_sdr_trcd_d,
-    cfg_sdr_trp_d,
-    cfg_sdr_twr_d,
-    cfg_sdr_width,
-    pad_sdr_din,
-    sdr_addr,
-    sdr_ba,
-    sdr_dout,
-    wb_addr_i,
-    wb_cti_i,
-    wb_dat_i,
-    wb_dat_o,
-    wb_sel_i);
- input cfg_sdr_en;
- output sdr_cas_n;
- output sdr_cke;
- output sdr_cs_n;
- output sdr_den_n;
- output sdr_dqm;
- output sdr_init_done;
- output sdr_ras_n;
- output sdr_we_n;
- input sdram_clk;
- input sdram_pad_clk;
- input sdram_resetn;
- output wb_ack_o;
- input wb_clk_i;
- input wb_cyc_i;
- input wb_rst_i;
- input wb_stb_i;
- input wb_we_i;
- input VPWR;
- input VGND;
- input [1:0] cfg_colbits;
- input [1:0] cfg_req_depth;
- input [2:0] cfg_sdr_cas;
- input [12:0] cfg_sdr_mode_reg;
- input [2:0] cfg_sdr_rfmax;
- input [11:0] cfg_sdr_rfsh;
- input [3:0] cfg_sdr_tras_d;
- input [3:0] cfg_sdr_trcar_d;
- input [3:0] cfg_sdr_trcd_d;
- input [3:0] cfg_sdr_trp_d;
- input [3:0] cfg_sdr_twr_d;
- input [1:0] cfg_sdr_width;
- input [7:0] pad_sdr_din;
- output [12:0] sdr_addr;
- output [1:0] sdr_ba;
- output [7:0] sdr_dout;
- input [31:0] wb_addr_i;
- input [2:0] wb_cti_i;
- input [31:0] wb_dat_i;
- output [31:0] wb_dat_o;
- input [3:0] wb_sel_i;
-
-endmodule
diff --git a/openlane/yifive/macro/bb/syntacore.v b/openlane/yifive/macro/bb/syntacore.v
deleted file mode 100644
index 1eb131f..0000000
--- a/openlane/yifive/macro/bb/syntacore.v
+++ /dev/null
@@ -1,58 +0,0 @@
-module scr1_top_wb (clk,
-    cpu_rst_n,
-    pwrup_rst_n,
-    rst_n,
-    rtc_clk,
-    soft_irq,
-    test_mode,
-    test_rst_n,
-    wbd_dmem_ack_i,
-    wbd_dmem_err_i,
-    wbd_dmem_stb_o,
-    wbd_dmem_we_o,
-    wbd_imem_ack_i,
-    wbd_imem_err_i,
-    wbd_imem_stb_o,
-    wbd_imem_we_o,
-    VPWR,
-    VGND,
-    fuse_mhartid,
-    irq_lines,
-    wbd_dmem_adr_o,
-    wbd_dmem_dat_i,
-    wbd_dmem_dat_o,
-    wbd_dmem_sel_o,
-    wbd_imem_adr_o,
-    wbd_imem_dat_i,
-    wbd_imem_dat_o,
-    wbd_imem_sel_o);
- input clk;
- input cpu_rst_n;
- input pwrup_rst_n;
- input rst_n;
- input rtc_clk;
- input soft_irq;
- input test_mode;
- input test_rst_n;
- input wbd_dmem_ack_i;
- input wbd_dmem_err_i;
- output wbd_dmem_stb_o;
- output wbd_dmem_we_o;
- input wbd_imem_ack_i;
- input wbd_imem_err_i;
- output wbd_imem_stb_o;
- output wbd_imem_we_o;
- input VPWR;
- input VGND;
- input [31:0] fuse_mhartid;
- input [15:0] irq_lines;
- output [31:0] wbd_dmem_adr_o;
- input [31:0] wbd_dmem_dat_i;
- output [31:0] wbd_dmem_dat_o;
- output [3:0] wbd_dmem_sel_o;
- output [31:0] wbd_imem_adr_o;
- input [31:0] wbd_imem_dat_i;
- output [31:0] wbd_imem_dat_o;
- output [3:0] wbd_imem_sel_o;
-
-endmodule
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index b4b1f0b..7cae2d2 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h38m39s,0h5m4s,1.362079701120797,10.2784,0.6810398505603985,0,575.3,7,0,0,0,0,0,0,0,0,0,-1,-1,1229122,6052,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,2.38,3.7,0.68,1.42,0.27,842,1460,842,1460,0,0,0,7,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h39m29s,0h5m43s,1.362079701120797,10.2784,0.6810398505603985,0,578.61,7,0,0,0,0,0,0,0,0,0,-1,-1,1229122,6052,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,2.38,3.7,0.68,1.42,0.27,842,1460,842,1460,0,0,0,7,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/verilog/dv/agents/uart_agent.v b/verilog/dv/agents/uart_agent.v
index 4c9d05d..f3e05ef 100644
--- a/verilog/dv/agents/uart_agent.v
+++ b/verilog/dv/agents/uart_agent.v
@@ -1,4 +1,19 @@
-
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
 module uart_agent (
 	mclk,
 	txd,
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 2777eaf..a90c7b1 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -1,8 +1,25 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 ////  User Risc Core Boot Validation                              ////
 ////                                                              ////
 ////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/yifive_r0.git              ////
 ////  http://www.opencores.org/cores/yifive/                      ////
 ////                                                              ////
 ////  Description                                                 ////
diff --git a/verilog/dv/risc_boot/run_iverilog b/verilog/dv/risc_boot/run_iverilog
index a75e2ff..30d8ffd 100755
--- a/verilog/dv/risc_boot/run_iverilog
+++ b/verilog/dv/risc_boot/run_iverilog
@@ -1,4 +1,20 @@
-
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# // 
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# //      http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
 #add -DWFDUMP to enable waveform dump
 iverilog -DWFDUMP -g2005-sv -DFUNCTIONAL -DSIM -I $PDK_PATH \
 -I $CARAVEL_ROOT/verilog/dv/caravel -I $CARAVEL_ROOT/verilog/rtl \
diff --git a/verilog/dv/risc_boot/user_uart.c b/verilog/dv/risc_boot/user_uart.c
index cb8c107..b60311c 100644
--- a/verilog/dv/risc_boot/user_uart.c
+++ b/verilog/dv/risc_boot/user_uart.c
@@ -1,4 +1,20 @@
-
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
 #define SC_SIM_OUTPORT (0xf0000000)
 #define uint32_t  long
 
diff --git a/verilog/dv/user_risc_boot/run_iverilog b/verilog/dv/user_risc_boot/run_iverilog
index d2520fa..63083a1 100755
--- a/verilog/dv/user_risc_boot/run_iverilog
+++ b/verilog/dv/user_risc_boot/run_iverilog
@@ -1,3 +1,21 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# // 
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# //      http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+
 riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common  user_risc_boot.c -o user_risc_boot.o
 
 riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/  ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
diff --git a/verilog/dv/user_risc_boot/user_risc_boot.c b/verilog/dv/user_risc_boot/user_risc_boot.c
index 3e9abeb..af9339d 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot.c
+++ b/verilog/dv/user_risc_boot/user_risc_boot.c
@@ -1,4 +1,20 @@
-
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
 #define SC_SIM_OUTPORT (0xf0000000)
 #define uint32_t  long
 
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index fa08ddc..87bf24c 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -1,20 +1,37 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 ////  Standalone User validation Test bench                       ////
 ////                                                              ////
 ////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/yifive_r0.git              ////
 ////  http://www.opencores.org/cores/yifive/                      ////
 ////                                                              ////
 ////  Description                                                 ////
-//     This is a standalone test bench to validate the            ////
-//     Digital core.                                              ////
-//     1. User Risc core is booted using  compiled code of        ////
-//        user_risc_boot.c                                        ////
-//     2. User Risc core uses Serial Flash and SDRAM to boot      ////
-//     3. After successful boot, Risc core will  write signature  ////
-//        in to  user register from 0x3000_0018 to 0x3000_002C    ////
-//     4. Through the External Wishbone Interface we read back    ////
-//         and validate the user register to declared pass fail   ////
+////   This is a standalone test bench to validate the            ////
+////   Digital core.                                              ////
+////   1. User Risc core is booted using  compiled code of        ////
+////      user_risc_boot.c                                        ////
+////   2. User Risc core uses Serial Flash and SDRAM to boot      ////
+////   3. After successful boot, Risc core will  write signature  ////
+////      in to  user register from 0x3000_0018 to 0x3000_002C    ////
+////   4. Through the External Wishbone Interface we read back    ////
+////       and validate the user register to declared pass fail   ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
diff --git a/verilog/dv/user_risc_boot/user_uart.c b/verilog/dv/user_risc_boot/user_uart.c
index cb8c107..04512bc 100644
--- a/verilog/dv/user_risc_boot/user_uart.c
+++ b/verilog/dv/user_risc_boot/user_uart.c
@@ -1,3 +1,20 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
 
 #define SC_SIM_OUTPORT (0xf0000000)
 #define uint32_t  long
diff --git a/verilog/dv/user_uart/run_iverilog b/verilog/dv/user_uart/run_iverilog
index 1badece..00d1d51 100755
--- a/verilog/dv/user_uart/run_iverilog
+++ b/verilog/dv/user_uart/run_iverilog
@@ -1,3 +1,20 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# // 
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# //      http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
 riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common  user_uart.c -o user_uart.o
 
 riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/  ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
diff --git a/verilog/dv/user_uart/user_uart.c b/verilog/dv/user_uart/user_uart.c
index cb8c107..b60311c 100644
--- a/verilog/dv/user_uart/user_uart.c
+++ b/verilog/dv/user_uart/user_uart.c
@@ -1,4 +1,20 @@
-
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
 #define SC_SIM_OUTPORT (0xf0000000)
 #define uint32_t  long
 
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index b1faa2f..3dcc653 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -1,8 +1,25 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 ////  Standalone User validation Test bench                       ////
 ////                                                              ////
 ////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/yifive_r0.git              ////
 ////  http://www.opencores.org/cores/yifive/                      ////
 ////                                                              ////
 ////  Description                                                 ////
diff --git a/verilog/rtl/digital_core/filelist_rtl.f b/verilog/rtl/digital_core/filelist_rtl.f
index d22f12e..3bb3d95 100755
--- a/verilog/rtl/digital_core/filelist_rtl.f
+++ b/verilog/rtl/digital_core/filelist_rtl.f
@@ -1,4 +1,20 @@
-
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
 +incdir+../sdram_ctrl/src/defs 
 +incdir+../syntacore/scr1/src/includes
 
diff --git a/verilog/rtl/digital_core/run_modelsim b/verilog/rtl/digital_core/run_modelsim
index 68309a1..2b56b12 100755
--- a/verilog/rtl/digital_core/run_modelsim
+++ b/verilog/rtl/digital_core/run_modelsim
@@ -1,3 +1,21 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# // 
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# //      http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+
 vlib work
 vlog -f filelist_rtl.f
 vsim -c digital_core -suppress vsim-3999 -do "exit"
diff --git a/verilog/rtl/lib/async_wb.sv b/verilog/rtl/lib/async_wb.sv
index 6174875..9908e54 100644
--- a/verilog/rtl/lib/async_wb.sv
+++ b/verilog/rtl/lib/async_wb.sv
@@ -1,3 +1,21 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+/*********************************************************************
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 ////  Async Wishbone Interface                                    ////
diff --git a/verilog/rtl/lib/registers.v b/verilog/rtl/lib/registers.v
index 665ef0a..44b2b1d 100755
--- a/verilog/rtl/lib/registers.v
+++ b/verilog/rtl/lib/registers.v
@@ -1,3 +1,20 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 ////  Tubo 8051 cores common library Module                       ////
diff --git a/verilog/rtl/sdram_ctrl/src/filelist_rtl.f b/verilog/rtl/sdram_ctrl/src/filelist_rtl.f
index 645eb9b..9e0b35c 100755
--- a/verilog/rtl/sdram_ctrl/src/filelist_rtl.f
+++ b/verilog/rtl/sdram_ctrl/src/filelist_rtl.f
@@ -1,3 +1,20 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
 ./top/sdrc_top.v 
 ./wb2sdrc/wb2sdrc.v 
 ../../lib/async_fifo.sv  
diff --git a/verilog/rtl/sdram_ctrl/src/run_modelsim b/verilog/rtl/sdram_ctrl/src/run_modelsim
index 353a20b..3a05c98 100755
--- a/verilog/rtl/sdram_ctrl/src/run_modelsim
+++ b/verilog/rtl/sdram_ctrl/src/run_modelsim
@@ -1,2 +1,20 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# // 
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# //      http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+
 vlib work
 vlog -f filelist_rtl.f +incdir+./defs
diff --git a/verilog/rtl/spi_master/src/filelist.f b/verilog/rtl/spi_master/src/filelist.f
index 6b47b62..ff10568 100644
--- a/verilog/rtl/spi_master/src/filelist.f
+++ b/verilog/rtl/spi_master/src/filelist.f
@@ -1,3 +1,21 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
+
 spim_top.sv
 spim_regs.sv
 spim_clkgen.sv
diff --git a/verilog/rtl/spi_master/synth/Makefile b/verilog/rtl/spi_master/synth/Makefile
index 1c814b2..f6ae1df 100644
--- a/verilog/rtl/spi_master/synth/Makefile
+++ b/verilog/rtl/spi_master/synth/Makefile
@@ -1,3 +1,20 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# // 
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# //      http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
 #------------------------------------------------------------------------------
 # Makefile for Synthesis
 #------------------------------------------------------------------------------
diff --git a/verilog/rtl/spi_master/synth/synth.tcl b/verilog/rtl/spi_master/synth/synth.tcl
index 1c327cf..aa97d89 100755
--- a/verilog/rtl/spi_master/synth/synth.tcl
+++ b/verilog/rtl/spi_master/synth/synth.tcl
@@ -1,17 +1,20 @@
-# Copyright 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# // 
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# //      http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
 # inputs expected as env vars
 #set opt $::env(SYNTH_OPT)
 ########### config.tcl ##################
diff --git a/verilog/rtl/syntacore/scr1/Makefile b/verilog/rtl/syntacore/scr1/Makefile
index adb33c5..a2142c4 100644
--- a/verilog/rtl/syntacore/scr1/Makefile
+++ b/verilog/rtl/syntacore/scr1/Makefile
@@ -1,3 +1,20 @@
+#//////////////////////////////////////////////////////////////////////////////
+#// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
+#// 
+#// Licensed under the Apache License, Version 2.0 (the "License");
+#// you may not use this file except in compliance with the License.
+#// You may obtain a copy of the License at
+#//
+#//      http://www.apache.org/licenses/LICENSE-2.0
+#//
+#// Unless required by applicable law or agreed to in writing, software
+#// distributed under the License is distributed on an "AS IS" BASIS,
+#// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#// See the License for the specific language governing permissions and
+#// limitations under the License.
+#// SPDX-License-Identifier: Apache-2.0
+#// SPDX-FileContributor: Syntacore LLC
+#// //////////////////////////////////////////////////////////////////////////
 #------------------------------------------------------------------------------
 # Makefile for SCR1
 #------------------------------------------------------------------------------
@@ -290,4 +307,4 @@
 	$(MAKE) -C $(tst_dir)/riscv_isa clean
 	$(MAKE) -C $(tst_dir)/riscv_compliance clean
 	$(RM) -R $(root_dir)/build/*
-	$(RM) $(test_info)
\ No newline at end of file
+	$(RM) $(test_info)
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk b/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk
index 9f78692..b9c0e03 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk
@@ -1,3 +1,21 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# // 
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# //      http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+
 ADD_ASM_MACRO ?= -D__ASSEMBLY__=1
 
 FLAGS = -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las $(ADD_FLAGS)
@@ -41,4 +59,4 @@
 	$(RISCV_OBJCOPY) $^ $@
 
 $(bld_dir)/%.dump: $(bld_dir)/%.elf
-	$(RISCV_OBJDUMP) $^ > $@
\ No newline at end of file
+	$(RISCV_OBJDUMP) $^ > $@
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/crt.S b/verilog/rtl/syntacore/scr1/sim/tests/common/crt.S
index 7887a29..6b18c76 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/crt.S
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/crt.S
@@ -1,4 +1,20 @@
-/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Syntacore LLC
+// //////////////////////////////////////////////////////////////////////////
 /// @file       <crt.S>
 ///
 
@@ -143,4 +159,4 @@
 handle_trap:
     j SIM_EXIT
 
-// end of crt.S
\ No newline at end of file
+// end of crt.S
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/crt_tcm.S b/verilog/rtl/syntacore/scr1/sim/tests/common/crt_tcm.S
index 5083438..5f2eba4 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/crt_tcm.S
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/crt_tcm.S
@@ -1,4 +1,20 @@
-/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Syntacore LLC
+// //////////////////////////////////////////////////////////////////////////
 /// @file       <crt_tcm.S>
 ///
 
@@ -154,4 +170,4 @@
 handle_trap:
     j SIM_EXIT
 
-// end of crt.S
\ No newline at end of file
+// end of crt.S
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/csr.h b/verilog/rtl/syntacore/scr1/sim/tests/common/csr.h
index 72c60fc..669dac5 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/csr.h
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/csr.h
@@ -1,4 +1,20 @@
-/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Syntacore LLC
+// //////////////////////////////////////////////////////////////////////////
 /// @file       <csr.h>
 /// Architecture specific CSR's defs and inlines
 
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld b/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld
index 050c58d..790e858 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld
@@ -1,5 +1,21 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Syntacore LLC
+// //////////////////////////////////////////////////////////////////////////
 /*
-* Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
 * @file       <link.ld>
 * @brief      bare metal tests' linker script
 */
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
index 0612031..d2bccd2 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
@@ -1,5 +1,21 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Syntacore LLC
+// //////////////////////////////////////////////////////////////////////////
 /*
-* Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
 * @file       <link.ld>
 * @brief      bare metal tests' linker script
 */
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/reloc.h b/verilog/rtl/syntacore/scr1/sim/tests/common/reloc.h
index 275d7a8..67dba7a 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/reloc.h
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/reloc.h
@@ -1,3 +1,22 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Syntacore LLC
+// //////////////////////////////////////////////////////////////////////////
+
+
 #ifndef RELOC_H
 #define RELOC_H
 
@@ -34,4 +53,4 @@
 
 #endif  // #else #if TCM
 
-#endif  // 
\ No newline at end of file
+#endif  // 
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_csr_encoding.h b/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_csr_encoding.h
index a1c9f64..19d3805 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_csr_encoding.h
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_csr_encoding.h
@@ -1,3 +1,20 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Syntacore LLC
+// //////////////////////////////////////////////////////////////////////////
 // See LICENSE for license details.
 
 #ifndef RISCV_CSR_ENCODING_H
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_macros.h b/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_macros.h
index 9390a8c..7f5ae94 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_macros.h
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_macros.h
@@ -1,3 +1,20 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Syntacore LLC
+// //////////////////////////////////////////////////////////////////////////
 // See LICENSE for license details.
 
 #ifndef __RISCV_MACROS_H
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.c b/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.c
index 3af9d23..5131e3b 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.c
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.c
@@ -1,4 +1,20 @@
-/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Syntacore LLC
+// //////////////////////////////////////////////////////////////////////////
 /// @file       <sc_print.c>
 ///
 
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.h b/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.h
index f175417..cc204cd 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.h
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.h
@@ -1,4 +1,20 @@
-/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Syntacore LLC
+// //////////////////////////////////////////////////////////////////////////
 /// @file       <sc_print.h>
 ///
 
@@ -7,4 +23,4 @@
 
 extern int sc_printf(const char* fmt, ...);
 
-#endif // SC_PRINT_H
\ No newline at end of file
+#endif // SC_PRINT_H
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/sc_test.h b/verilog/rtl/syntacore/scr1/sim/tests/common/sc_test.h
index 84827aa..032de7c 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/sc_test.h
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/sc_test.h
@@ -1,4 +1,20 @@
-/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Syntacore LLC
+// //////////////////////////////////////////////////////////////////////////
 /// @file       <sc_test.h>
 ///
 
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/scr1_specific.h b/verilog/rtl/syntacore/scr1/sim/tests/common/scr1_specific.h
index f965880..e9fe5ae 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/scr1_specific.h
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/scr1_specific.h
@@ -1,3 +1,20 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Syntacore LLC
+// //////////////////////////////////////////////////////////////////////////
 #ifndef __SCR1__SPECIFIC
 #define __SCR1__SPECIFIC
 
diff --git a/verilog/rtl/syntacore/scr1/synth/synth.tcl b/verilog/rtl/syntacore/scr1/synth/synth.tcl
index ca8fde9..1499a8c 100755
--- a/verilog/rtl/syntacore/scr1/synth/synth.tcl
+++ b/verilog/rtl/syntacore/scr1/synth/synth.tcl
@@ -1,19 +1,20 @@
-# Copyright 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# ////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+# //
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# //      http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
 
-# inputs expected as env vars
-#set opt $::env(SYNTH_OPT)
 ########### config.tcl ##################
 # User config