diff --git a/openlane/clk_buf/config.tcl b/openlane/clk_buf/config.tcl
new file mode 100644
index 0000000..a4e28ab
--- /dev/null
+++ b/openlane/clk_buf/config.tcl
@@ -0,0 +1,68 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) clk_buf
+set verilog_root $script_dir/../../verilog/
+set lef_root $script_dir/../../lef/
+set gds_root $script_dir/../../gds/
+#section end
+
+# User Configurations
+#
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) "0"
+
+
+## Source Verilog Files
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/lib/clk_buf.v"
+
+## Clock configurations
+#set ::env(CLOCK_PORT) "clk_in"
+
+#set ::env(CLOCK_PERIOD) "10"
+
+## Internal Macros
+### Macro Placement
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 30 30"
+
+
+
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+# Fill this
+set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(CELL_PAD) 4
+
+set ::env(FP_CORE_UTIL) 60
+#set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+
+set ::env(BOTTOM_MARGIN_MULT) 2
+set ::env(TOP_MARGIN_MULT) 2
+set ::env(GLB_RT_MAXLAYER) 4
diff --git a/openlane/clk_buf/pin_order.cfg b/openlane/clk_buf/pin_order.cfg
new file mode 100644
index 0000000..1b25a6f
--- /dev/null
+++ b/openlane/clk_buf/pin_order.cfg
@@ -0,0 +1,9 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#N
+clk_o              0000 0
+
+#S
+clk_i              0000 0
diff --git a/openlane/glbl_cfg/base.sdc b/openlane/glbl_cfg/base.sdc
index 0941e88..92c03ea 100644
--- a/openlane/glbl_cfg/base.sdc
+++ b/openlane/glbl_cfg/base.sdc
@@ -28,6 +28,8 @@
 puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
 puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
 
+set_clock_uncertainty -from $::env(WB_CLOCK_PORT) -to $::env(WB_CLOCK_PORT)  -setup 0.400
+set_clock_uncertainty -from $::env(WB_CLOCK_PORT) -to $::env(WB_CLOCK_PORT)  -hold  0.050
 
 set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {reset_n}
 
@@ -38,7 +40,6 @@
 set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_be*]
 set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port sdr_init_done*]
 
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port device_idcode*]
 set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_rdata*]
 set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_ack*]
 set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port fuse_mhartid*]
@@ -69,11 +70,3 @@
 puts "\[INFO\]: Setting load to: $cap_load"
 set_load  $cap_load [all_outputs]
 
-## These are generated clock, only max delay added
-set_false_path -to [get_port sdram_clk] 
-set_false_path -to [get_port cpu_clk] 
-set_false_path -to [get_port rtc_clk] 
-
-#set_max_delay 2.0 [get_port sdram_clk]
-#set_max_delay 2.0 [get_port cpu_clk]
-#set_max_delay 2.0 [get_port rtc_clk]
diff --git a/openlane/glbl_cfg/pin_order.cfg b/openlane/glbl_cfg/pin_order.cfg
index 770b1f7..f111f5a 100644
--- a/openlane/glbl_cfg/pin_order.cfg
+++ b/openlane/glbl_cfg/pin_order.cfg
@@ -3,8 +3,7 @@
 #MANUAL_PLACE
 
 #N
-mclk                   0000 0
-reset_n                
+reset_n               0000 0        
 user_irq\[2\]          
 user_irq\[1\]          
 user_irq\[0\]          
@@ -69,7 +68,7 @@
 cfg_sdr_rfmax\[2\]   
 cfg_sdr_rfmax\[1\]   
 cfg_sdr_rfmax\[0\]   
-
+mclk                   0150 0
 
 #S
 reg_cs               0000 0
diff --git a/openlane/sdram/base.sdc b/openlane/sdram/base.sdc
index 2bdd058..a64cf51 100644
--- a/openlane/sdram/base.sdc
+++ b/openlane/sdram/base.sdc
@@ -18,59 +18,63 @@
 set_units -time ns
 set ::env(WB_CLOCK_PERIOD) "10"
 set ::env(WB_CLOCK_PORT)   "wb_clk_i"
+set ::env(WB_CLOCK_NAME)   "wb_clk"
 
 set ::env(SDRAM_CLOCK_PERIOD) "20"
 set ::env(SDRAM_CLOCK_PORT)   "sdram_clk"
+set ::env(SDRAM_CLOCK_NAME)   "sdram_clk"
 
 set ::env(PAD_SDRAM_CLOCK_PERIOD) "20"
 set ::env(PAD_SDRAM_CLOCK_PORT)   "io_in\[29\]"
+set ::env(PAD_SDRAM_CLOCK_NAME)   "pad_sdram_clk"
 ######################################
 # WB Clock domain input output
 ######################################
-create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_PORT)  -period $::env(WB_CLOCK_PERIOD)
+create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_NAME)  -period $::env(WB_CLOCK_PERIOD)
 set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
 set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
 puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
 puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
 
 
-set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {wb_rst_n}
-set_input_delay 2.0 -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] {sdram_resetn}
+set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_NAME)] {wb_rst_n}
 
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_stb_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_addr_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_we_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_dat_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_sel_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_cyc_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_stb_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_addr_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_we_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_dat_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_sel_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_cyc_i*]
 
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_tras_d*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trp_d*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcd_d*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_en*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_req_depth*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_mode_reg*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_cas*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcar_d*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_twr_d*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfsh*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfmax*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_colbits*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_width*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_tras_d*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_trp_d*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_trcd_d*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_en*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_req_depth*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_mode_reg*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_cas*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_trcar_d*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_twr_d*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_rfsh*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_rfmax*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_colbits*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port cfg_sdr_width*]
 
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_dat_o*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_ack_o*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port sdr_init_done*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_dat_o*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port wb_ack_o*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_NAME)] [get_port sdr_init_done*]
 
 ######################################
 # SDRAM Clock domain input output
 ######################################
-create_clock [get_ports $::env(SDRAM_CLOCK_PORT)]  -name $::env(SDRAM_CLOCK_PORT)  -period $::env(SDRAM_CLOCK_PERIOD)
+create_clock [get_ports $::env(SDRAM_CLOCK_PORT)]  -name $::env(SDRAM_CLOCK_NAME)  -period $::env(SDRAM_CLOCK_PERIOD)
 set sdram_input_delay_value [expr $::env(SDRAM_CLOCK_PERIOD) * 0.6]
 set sdram_output_delay_value [expr $::env(SDRAM_CLOCK_PERIOD) * 0.6]
 puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
 puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
 
+set_input_delay 2.0 -clock [get_clocks $::env(SDRAM_CLOCK_NAME)] {sdram_resetn}
+
 set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[0]]
 set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[1]]
 set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[2]]
@@ -132,7 +136,7 @@
 set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[26]]
 set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[27]]
 set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[28]]
-#set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[29]] Masked SDRAM clock
+#set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_outp 29]] Masked SDRAM clock
 set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_oeb*]
 
 ################################################
@@ -141,13 +145,22 @@
 #       it's a feedback clock through pads
 ################################################
 
-create_clock [get_ports $::env(PAD_SDRAM_CLOCK_PORT)]  -name $::env(PAD_SDRAM_CLOCK_PORT)  -period $::env(SDRAM_CLOCK_PERIOD)
-set_input_delay  $sdram_input_delay_value -max  -clock [get_clocks $::env(PAD_SDRAM_CLOCK_PORT)] [get_port io_in*]
-set_input_delay  1                        -min -clock [get_clocks $::env(PAD_SDRAM_CLOCK_PORT)] [get_port io_in*]
+create_clock [get_ports $::env(PAD_SDRAM_CLOCK_PORT)]  -name $::env(PAD_SDRAM_CLOCK_NAME)  -period $::env(SDRAM_CLOCK_PERIOD)
+set_input_delay  $sdram_input_delay_value -max  -clock [get_clocks $::env(PAD_SDRAM_CLOCK_NAME)] [get_port io_in*]
+set_input_delay  1                        -min -clock [get_clocks $::env(PAD_SDRAM_CLOCK_NAME)] [get_port io_in*]
 
 
-set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_PORT)] -group [get_clocks $::env(SDRAM_CLOCK_PORT)]
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_NAME)] -group [get_clocks $::env(SDRAM_CLOCK_NAME)]
 
+## Add clock uncertainty
+#Note: We have PAD_SDRAM_CLOCK_NAME => SDRAM_CLOCK_NAME path only
+set_clock_uncertainty -from $::env(WB_CLOCK_NAME)        -to $::env(WB_CLOCK_NAME)    -setup 0.400
+set_clock_uncertainty -from $::env(SDRAM_CLOCK_NAME)     -to $::env(SDRAM_CLOCK_NAME) -setup 0.400
+set_clock_uncertainty -from $::env(PAD_SDRAM_CLOCK_NAME) -to $::env(SDRAM_CLOCK_NAME) -setup 0.400
+
+set_clock_uncertainty -from $::env(WB_CLOCK_NAME)        -to $::env(WB_CLOCK_NAME)    -hold 0.050
+set_clock_uncertainty -from $::env(SDRAM_CLOCK_NAME)     -to $::env(SDRAM_CLOCK_NAME) -hold 0.050
+set_clock_uncertainty -from $::env(PAD_SDRAM_CLOCK_NAME) -to $::env(SDRAM_CLOCK_NAME) -hold 0.050 
 
 # TODO set this as parameter
 set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
diff --git a/openlane/spi_master/base.sdc b/openlane/spi_master/base.sdc
index aab27ac..129b737 100644
--- a/openlane/spi_master/base.sdc
+++ b/openlane/spi_master/base.sdc
@@ -92,6 +92,11 @@
 set_output_delay 0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[2]]
 set_output_delay 0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[1]]
 
+set_clock_uncertainty -from $::env(SPI_CLOCK_PORT)   -to $::env(SPI_CLOCK_PORT)   -setup 0.400
+set_clock_uncertainty -from $::env(WB_CLOCK_PERIOD)  -to $::env(WB_CLOCK_PERIOD)  -setup 0.400
+set_clock_uncertainty -from $::env(SPI_CLOCK_PORT)   -to $::env(SPI_CLOCK_PORT)   -hold 0.050
+set_clock_uncertainty -from $::env(WB_CLOCK_PERIOD)  -to $::env(WB_CLOCK_PERIOD)  -hold 0.050
+
 # TODO set this as parameter
 set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
 set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
diff --git a/openlane/syntacore/base.sdc b/openlane/syntacore/base.sdc
index ec80763..508d423 100644
--- a/openlane/syntacore/base.sdc
+++ b/openlane/syntacore/base.sdc
@@ -19,47 +19,65 @@
 #Wishbone Clock
 set ::env(WB_CLOCK_PERIOD)    "10"
 set ::env(WB_CLOCK_PORT)      "wb_clk"
+set ::env(WB_CLOCK_NAME)      "wb_clk"
 
 #Risc Core Clock
-set ::env(CORE_CLOCK_PERIOD) "50"
+set ::env(CORE_CLOCK_PERIOD) "40"
 set ::env(CORE_CLOCK_PORT)   "core_clk"
+set ::env(CORE_CLOCK_NAME)   "core_clk"
+
+#RTC Core Clock
+set ::env(RTC_CLOCK_PERIOD) "40"
+set ::env(RTC_CLOCK_PORT)   "rtc_clk"
+set ::env(RTC_CLOCK_NAME)   "rtc_clk"
 
 ######################################
 # CORE Clock domain input output
 ######################################
-create_clock [get_ports $::env(CORE_CLOCK_PORT)]  -name $::env(CORE_CLOCK_PORT)  -period $::env(CORE_CLOCK_PERIOD)
+create_clock [get_ports $::env(CORE_CLOCK_PORT)]  -name $::env(CORE_CLOCK_NAME)  -period $::env(CORE_CLOCK_PERIOD)
 set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
 set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
 puts "\[INFO\]: Setting core output delay to: $core_output_delay_value"
 puts "\[INFO\]: Setting core input delay to: $core_input_delay_value"
-set core_clk_indx [lsearch [all_inputs] [get_port $::env(CORE_CLOCK_PORT)]]
+set core_clk_indx [lsearch [all_inputs] [get_port $::env(CORE_CLOCK_NAME)]]
 set core_rst_indx [lsearch [all_inputs] [get_port cpu_rst_n]]
 set all_inputs_wo_core_clk_rst [lreplace [all_inputs] $core_clk_indx $core_rst_indx]
 set all_outputs_core [all_outputs] 
 
-set_input_delay $core_input_delay_value  -clock [get_clocks $::env(CORE_CLOCK_PORT)] $all_inputs_wo_core_clk_rst
-set_input_delay 5.0 -clock [get_clocks $::env(CORE_CLOCK_PORT)] {cpu_rst_n}
-set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_PORT)] $all_outputs_core
+set_input_delay $core_input_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] $all_inputs_wo_core_clk_rst
+set_input_delay 5.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {cpu_rst_n}
+set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] $all_outputs_core
+
+create_clock [get_ports $::env(RTC_CLOCK_PORT)]  -name $::env(RTC_CLOCK_NAME)  -period $::env(RTC_CLOCK_PERIOD)
 
 ######################################
 # WB Clock domain input output
 ######################################
-create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_PORT)  -period $::env(WB_CLOCK_PERIOD)
+create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_NAME)  -period $::env(WB_CLOCK_PERIOD)
 set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
 set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
 puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
 puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
-set wb_clk_indx [lsearch [all_inputs] [get_port $::env(WB_CLOCK_PORT)]]
+set wb_clk_indx [lsearch [all_inputs] [get_port $::env(WB_CLOCK_NAME)]]
 set wb_rst_indx [lsearch [all_inputs] [get_port wb_rst_n]]
 set all_inputs_wo_wb_clk_rst [lreplace [all_inputs] $wb_clk_indx $wb_rst_indx]
 set all_outputs_wb [all_outputs]
 
-set_input_delay $wb_input_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] $all_inputs_wo_wb_clk_rst
-set_input_delay 5.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {wb_rst_n}
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] $all_outputs_wb
+set_input_delay $wb_input_delay_value  -clock [get_clocks $::env(WB_CLOCK_NAME)] $all_inputs_wo_wb_clk_rst
+set_input_delay 5.0 -clock [get_clocks $::env(WB_CLOCK_NAME)] {wb_rst_n}
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_NAME)] $all_outputs_wb
 
 #### Clock Async Defination
-set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_PORT)] -group [get_clocks $::env(CORE_CLOCK_PORT)]
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_NAME)] -group [get_clocks $::env(CORE_CLOCK_NAME)] -group [get_clocks $::env(RTC_CLOCK_NAME)]
+
+set_clock_uncertainty -from $::env(WB_CLOCK_NAME)    -to $::env(WB_CLOCK_NAME)    -setup 0.400
+set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)  -to $::env(CORE_CLOCK_NAME)   -setup 0.400
+set_clock_uncertainty -from $::env(RTC_CLOCK_NAME)   -to $::env(RTC_CLOCK_NAME)   -setup 0.400
+
+set_clock_uncertainty -from $::env(WB_CLOCK_NAME)    -to $::env(WB_CLOCK_NAME)    -hold 0.050
+set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)  -to $::env(CORE_CLOCK_NAME)   -hold 0.050
+set_clock_uncertainty -from $::env(RTC_CLOCK_NAME)   -to $::env(RTC_CLOCK_NAME)   -hold 0.050
+
 
 # TODO set this as parameter
 set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
diff --git a/openlane/uart/base.sdc b/openlane/uart/base.sdc
index 01e5123..b64ad61 100644
--- a/openlane/uart/base.sdc
+++ b/openlane/uart/base.sdc
@@ -18,18 +18,17 @@
 set_units -time ns
 set ::env(CORE_CLOCK_PERIOD) "10"
 set ::env(CORE_CLOCK_PORT)   "app_clk"
+set ::env(CORE_CLOCK_NAME)   "app_clk"
 
 set ::env(LINE_CLOCK_PERIOD) "100"
-set ::env(LINE_CLOCK_PORT)   "line_clk"
+set ::env(LINE_CLOCK_PORT)   "u_lineclk_buf/X"
+set ::env(LINE_CLOCK_NAME)   "line_clk"
 
 ######################################
 # WB Clock domain input output
 ######################################
-create_clock [get_ports $::env(CORE_CLOCK_PORT)]  -name $::env(CORE_CLOCK_PORT)  -period $::env(CORE_CLOCK_PERIOD)
-create_clock [get_pins  u_lineclk_buf/X ]  -name $::env(LINE_CLOCK_PORT)  -period $::env(LINE_CLOCK_PERIOD)
-
-
-set_clock_groups -name sys_clk -asynchronous -group $::env(CORE_CLOCK_PORT) -group $::env(LINE_CLOCK_PORT)
+create_clock [get_ports $::env(CORE_CLOCK_PORT)]  -name $::env(CORE_CLOCK_NAME)  -period $::env(CORE_CLOCK_PERIOD)
+create_clock [get_pins  $::env(LINE_CLOCK_PORT)]  -name $::env(LINE_CLOCK_NAME)  -period $::env(LINE_CLOCK_PERIOD)
 
 set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
 set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
@@ -40,23 +39,31 @@
 puts "\[INFO\]: Setting wb input delay to: $core_input_delay_value"
 
 
-set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_PORT)] {arst_n}
+set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {arst_n}
 
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_PORT)] [get_port reg_cs*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_PORT)] [get_port reg_addr*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_PORT)] [get_port reg_wr*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_PORT)] [get_port reg_be*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_PORT)] [get_port reg_wdata*]
+set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_cs*]
+set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_addr*]
+set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wr*]
+set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_be*]
+set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wdata*]
 
 
-set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_PORT)] [get_port reg_rdata*]
-set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_PORT)] [get_port reg_ack*]
+set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_rdata*]
+set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_ack*]
 
-set_input_delay  $line_input_delay_value   -clock [get_clocks $::env(LINE_CLOCK_PORT)] [get_port io_in*]
-set_output_delay $line_input_delay_value   -clock [get_clocks $::env(LINE_CLOCK_PORT)] [get_port io_oeb*]
-set_output_delay $line_output_delay_value  -clock [get_clocks $::env(LINE_CLOCK_PORT)] [get_port io_out*]
+set_input_delay  $line_input_delay_value   -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_in*]
+set_output_delay $line_input_delay_value   -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_oeb*]
+set_output_delay $line_output_delay_value  -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_out*]
 
 
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(CORE_CLOCK_NAME)] -group [get_clocks $::env(LINE_CLOCK_NAME)] 
+
+set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)   -to $::env(CORE_CLOCK_NAME)  -setup 0.400
+set_clock_uncertainty -from $::env(LINE_CLOCK_NAME)   -to $::env(LINE_CLOCK_NAME) -setup 0.400
+
+set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)   -to $::env(CORE_CLOCK_NAME)  -hold 0.050
+set_clock_uncertainty -from $::env(LINE_CLOCK_NAME)   -to $::env(LINE_CLOCK_NAME) -hold 0.050
+
 # TODO set this as parameter
 set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
 set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
diff --git a/openlane/user_project_wrapper/base.sdc b/openlane/user_project_wrapper/base.sdc
index 6aabd5a..509c8cb 100644
--- a/openlane/user_project_wrapper/base.sdc
+++ b/openlane/user_project_wrapper/base.sdc
@@ -21,25 +21,29 @@
 set ::env(WBM_CLOCK_NAME)   "wbm_clk_i"
 
 set ::env(WBS_CLOCK_PERIOD) "10"
-set ::env(WBS_CLOCK_PORT)   "u_wb_host*wbs_clk_i"
+set ::env(WBS_CLOCK_PORT)   "u_wb_host*wbs_clk_out"
 set ::env(WBS_CLOCK_NAME)   "wbs_clk_i"
 
 set ::env(SDRAM_CLOCK_PERIOD) "20"
-set ::env(SDRAM_CLOCK_PORT)   "u_glbl_cfg*sdram_clk"
+set ::env(SDRAM_CLOCK_PORT)   "u_wb_host*sdram_clk"
 set ::env(SDRAM_CLOCK_NAME)   "sdram_clk"
 
 set ::env(PAD_SDRAM_CLOCK_PERIOD) "20"
-set ::env(PAD_SDRAM_CLOCK_PORT)   "u_skew_sd_ci*sclk_out"
+set ::env(PAD_SDRAM_CLOCK_PORT)   "u_skew_sd_ci*clk_in"
 set ::env(PAD_SDRAM_CLOCK_NAME)   "sdram_pad_clk"
 
 set ::env(CPU_CLOCK_PERIOD) "50"
-set ::env(CPU_CLOCK_PORT)   "u_glbl_cfg*cpu_clk"
+set ::env(CPU_CLOCK_PORT)   "u_wb_host*cpu_clk"
 set ::env(CPU_CLOCK_NAME)   "cpu_clk"
 
 set ::env(RTC_CLOCK_PERIOD) "50"
-set ::env(RTC_CLOCK_PORT)   "u_glbl_cfg*rtc_clk"
+set ::env(RTC_CLOCK_PORT)   "u_wb_host*rtc_clk"
 set ::env(RTC_CLOCK_NAME)   "rtc_clk"
 
+set ::env(UART_CLOCK_PERIOD) "100"
+set ::env(UART_CLOCK_PORT)   "u_uart_core*u_lineclk_buf/X"
+set ::env(UART_CLOCK_NAME)   "line_clk"
+
 #Setting clock delay to center of the tap
 set_case_analysis 1 [get_pins -hierarchical u_skew_wi*sel[3]]
 set_case_analysis 0 [get_pins -hierarchical u_skew_wi*sel[2]] 
@@ -61,10 +65,10 @@
 set_case_analysis 0 [get_pins -hierarchical u_skew_spi*sel[1]]
 set_case_analysis 0 [get_pins -hierarchical u_skew_spi*sel[0]]
 
-set_case_analysis 1 [get_pins -hierarchical u_skew_glbl*sel[3]]
-set_case_analysis 0 [get_pins -hierarchical u_skew_glbl*sel[2]]
-set_case_analysis 0 [get_pins -hierarchical u_skew_glbl*sel[1]]
-set_case_analysis 0 [get_pins -hierarchical u_skew_glbl*sel[0]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_glbl*sel[3]]
+set_case_analysis 1 [get_pins -hierarchical u_skew_glbl*sel[2]]
+set_case_analysis 1 [get_pins -hierarchical u_skew_glbl*sel[1]]
+set_case_analysis 1 [get_pins -hierarchical u_skew_glbl*sel[0]]
 
 set_case_analysis 1 [get_pins -hierarchical u_skew_wh*sel[3]]
 set_case_analysis 0 [get_pins -hierarchical u_skew_wh*sel[2]]
@@ -80,7 +84,7 @@
 set_case_analysis 0 [get_pins -hierarchical u_skew_sd_ci*sel[3]]
 set_case_analysis 0 [get_pins -hierarchical u_skew_sd_ci*sel[2]]
 set_case_analysis 0 [get_pins -hierarchical u_skew_sd_ci*sel[1]]
-set_case_analysis 0 [get_pins -hierarchical u_skew_sd_ci*sel[0]]
+set_case_analysis 1 [get_pins -hierarchical u_skew_sd_ci*sel[0]]
 
 set_case_analysis 0 [get_pins -hierarchical u_skew_sp_co*sel[3]]
 set_case_analysis 0 [get_pins -hierarchical u_skew_sp_co*sel[2]]
@@ -91,8 +95,8 @@
 # WB MASTER Clock domain input output
 ######################################
 create_clock [get_ports $::env(WBM_CLOCK_PORT)]  -name $::env(WBM_CLOCK_NAME)  -period $::env(WBM_CLOCK_PERIOD)
-set wb_input_delay_value [expr $::env(WBM_CLOCK_PERIOD) * 0.6]
-set wb_output_delay_value [expr $::env(WBM_CLOCK_PERIOD) * 0.6]
+set wb_input_delay_value [expr $::env(WBM_CLOCK_PERIOD) * 0.54]
+set wb_output_delay_value [expr $::env(WBM_CLOCK_PERIOD) * 0.54]
 puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
 puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
 
@@ -108,7 +112,7 @@
 set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wb_cti_i*]
 
 set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_dat_o*]
-set_output_delay 3.0                     -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_ack_o*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_ack_o*]
 
 ######################################
 # WishBone Slave Port
@@ -121,10 +125,29 @@
 create_clock [get_pins -hierarchical $::env(PAD_SDRAM_CLOCK_PORT)]  -name $::env(PAD_SDRAM_CLOCK_NAME)  -period $::env(PAD_SDRAM_CLOCK_PERIOD)
 create_clock [get_pins -hierarchical $::env(CPU_CLOCK_PORT)] -name $::env(CPU_CLOCK_NAME)  -period $::env(CPU_CLOCK_PERIOD)
 create_clock [get_pins -hierarchical $::env(RTC_CLOCK_PORT)] -name $::env(RTC_CLOCK_NAME)  -period $::env(RTC_CLOCK_PERIOD)
+create_clock [get_pins -hierarchical $::env(UART_CLOCK_PORT)]  -name $::env(UART_CLOCK_NAME)  -period $::env(UART_CLOCK_PERIOD)
 
-set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WBM_CLOCK_NAME)] -group [get_clocks $::env(WBS_CLOCK_NAME)] -group [get_clocks $::env(SDRAM_CLOCK_NAME)] -group [get_clocks $::env(CPU_CLOCK_NAME)] -group [get_clocks $::env(RTC_CLOCK_NAME)] 
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WBM_CLOCK_NAME)] -group [get_clocks $::env(WBS_CLOCK_NAME)] -group [get_clocks $::env(SDRAM_CLOCK_NAME)] -group [get_clocks $::env(CPU_CLOCK_NAME)] -group [get_clocks $::env(RTC_CLOCK_NAME)] -group [get_clocks $::env(UART_CLOCK_NAME)] 
 
 
+## Add clock uncertainty
+#Note: We have PAD_SDRAM_CLOCK_NAME => SDRAM_CLOCK_NAME path only
+
+set_clock_uncertainty -from $::env(WBM_CLOCK_NAME)          -to $::env(WBM_CLOCK_NAME)    -setup 0.200
+set_clock_uncertainty -from $::env(WBS_CLOCK_NAME)          -to $::env(WBS_CLOCK_NAME)    -setup 0.200
+set_clock_uncertainty -from $::env(SDRAM_CLOCK_NAME)        -to $::env(SDRAM_CLOCK_NAME)  -setup 0.200
+set_clock_uncertainty -from $::env(PAD_SDRAM_CLOCK_NAME)    -to $::env(SDRAM_CLOCK_NAME)  -setup 0.200
+set_clock_uncertainty -from $::env(CPU_CLOCK_NAME)          -to $::env(CPU_CLOCK_NAME)    -setup 0.200
+set_clock_uncertainty -from $::env(RTC_CLOCK_NAME)          -to $::env(RTC_CLOCK_NAME)    -setup 0.200
+set_clock_uncertainty -from $::env(UART_CLOCK_NAME)         -to $::env(UART_CLOCK_NAME)   -setup 0.200
+
+set_clock_uncertainty -from $::env(WBM_CLOCK_NAME)          -to $::env(WBM_CLOCK_NAME)    -hold 0.050
+set_clock_uncertainty -from $::env(WBS_CLOCK_NAME)          -to $::env(WBS_CLOCK_NAME)    -hold 0.050
+set_clock_uncertainty -from $::env(SDRAM_CLOCK_NAME)        -to $::env(SDRAM_CLOCK_NAME)  -hold 0.050
+set_clock_uncertainty -from $::env(PAD_SDRAM_CLOCK_NAME)    -to $::env(SDRAM_CLOCK_NAME)  -hold 0.050
+set_clock_uncertainty -from $::env(CPU_CLOCK_NAME)          -to $::env(CPU_CLOCK_NAME)    -hold 0.050
+set_clock_uncertainty -from $::env(RTC_CLOCK_NAME)          -to $::env(RTC_CLOCK_NAME)    -hold 0.050
+set_clock_uncertainty -from $::env(UART_CLOCK_NAME)         -to $::env(UART_CLOCK_NAME)   -hold 0.050
 
 # TODO set this as parameter
 set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
@@ -132,3 +155,9 @@
 puts "\[INFO\]: Setting load to: $cap_load"
 set_load  $cap_load [all_outputs]
 
+## 2 Multi-cycle setup and 0 hold
+set_multicycle_path -setup -from wbs_adr_i* 2
+set_multicycle_path -hold -from wbs_adr_i* 2
+
+set_multicycle_path -setup -from wbs_we_i* 2
+set_multicycle_path -hold -from wbs_we_i* 2
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index f51d3d1..66a7991 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -50,6 +50,7 @@
 set ::env(SDC_FILE) "$script_dir/base.sdc"
 set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
 
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
@@ -59,6 +60,7 @@
         $script_dir/../../verilog/gl/uart.v     \
 	$script_dir/../../verilog/gl/sdram.v \
 	$script_dir/../../verilog/gl/wb_host.v \
+	$script_dir/../../verilog/gl/clk_buf.v \
 	$script_dir/../../verilog/gl/clk_skew_adjust.v \
 	$script_dir/../../verilog/gl/syntacore.v \
 	"
@@ -70,6 +72,7 @@
 	$lef_root/sdram.lef \
 	$lef_root/uart.lef \
 	$lef_root/wb_host.lef \
+	$lef_root/clk_buf.lef \
 	$lef_root/clk_skew_adjust.lef \
 	$lef_root/syntacore.lef \
 	"
@@ -81,6 +84,7 @@
 	$gds_root/uart.gds \
 	$gds_root/sdram.gds \
 	$gds_root/wb_host.gds \
+	$gds_root/clk_buf.gds \
 	$gds_root/clk_skew_adjust.gds \
 	$gds_root/syntacore.gds \
 	"
@@ -101,16 +105,16 @@
 
 # The following is because there are no std cells in the example wrapper project.
 #set ::env(SYNTH_TOP_LEVEL) 1
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+#set ::env(PL_RANDOM_GLB_PLACEMENT) 1
 
 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
 set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
 set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
 
+set ::env(TAP_DECAP_INSERTION) "0"
 set ::env(DIODE_INSERTION_STRATEGY) 0
 set ::env(FILL_INSERTION) 0
-set ::env(TAP_DECAP_INSERTION) 0
 set ::env(CLOCK_TREE_SYNTH) 0
 
 #set ::env(MAGIC_EXT_USE_GDS) "1"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index c5044dc..ca7a467 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,17 +1,21 @@
 u_spi_master            300             2700            N
 u_sdram_ctrl            1000            2700            N
 u_glbl_cfg              2000            2700            N
-u_riscv_top	       500	       800	       N
+u_riscv_top	        500	        800	        N
 u_uart_core             2200            1600            N
 u_intercon              300             2300            N
 u_wb_host               300             300             N
 u_skew_wi               2600            2300            N
-u_skew_riscv            400             800             N
+u_skew_riscv            500             700             N
 u_skew_uart             2200            1500            N
 u_skew_spi              200             2700            E
 u_skew_sdram            900             2700            E
-u_skew_glbl             2000            3200            N
-u_skew_wh               1400            300             N
+u_skew_glbl             1900            2850            N
+u_skew_wh               800             600             N
 u_skew_sd_co            950             3300            N
 u_skew_sd_ci            1100            3300            N
-u_skew_sp_co            300             3400            N
+u_skew_sp_co            100             1800            N
+u_buf1_wb_rstn          2000            500             N
+u_buf2_wb_rstn          2600            1700            N
+u_buf1_wbclk            2100            700             N
+u_buf2_wbclk            1500            2100            N
diff --git a/openlane/user_project_wrapper/sta.tcl b/openlane/user_project_wrapper/sta.tcl
index 72967bd..ac444aa 100644
--- a/openlane/user_project_wrapper/sta.tcl
+++ b/openlane/user_project_wrapper/sta.tcl
@@ -15,55 +15,59 @@
 # SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
 
 
-set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
-set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
 set ::env(DESIGN_NAME) "user_project_wrapper"
-set ::env(BASE_SDC_FILE) "/project/openlane/user_project_wrapper/base.sdc"
+set ::env(BASE_SDC_FILE) "base.sdc"
 set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
 set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
 set ::env(SYNTH_CAP_LOAD) "17.65"
 set ::env(WIRE_RC_LAYER) "met1"
 
+#To disable empty filler cell black box get created
+#set link_make_black_boxes 0
+
 
 set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
 define_corners wc bc
 read_liberty -corner bc $::env(LIB_FASTEST)
 read_liberty -corner wc $::env(LIB_SLOWEST)
-read_verilog /project/verilog/gl/clk_skew_adjust.v  
-read_verilog /project/verilog/gl/glbl_cfg.v  
-#read_verilog /project/verilog/gl/sdram.v  
-read_verilog /project/verilog/gl/spi_master.v  
-#read_verilog /project/verilog/gl/syntacore.v  
-read_verilog /project/verilog/gl/uart.v  
-read_verilog /project/verilog/gl/wb_host.v  
-read_verilog /project/verilog/gl/wb_interconnect.v
-read_verilog /project/verilog/gl/user_project_wrapper.v  
+read_verilog netlist/clk_skew_adjust.v  
+read_verilog netlist/glbl_cfg.v  
+read_verilog netlist/sdram.v  
+read_verilog netlist/spi_master.v 
+read_verilog netlist/syntacore.v  
+read_verilog netlist/uart.v  
+read_verilog netlist/wb_host.v  
+read_verilog netlist/wb_interconnect.v
+read_verilog netlist/user_project_wrapper.v  
 link_design  $::env(DESIGN_NAME)
 
-read_spef -path u_skew_wi    /project/spef/clk_skew_adjust.spef  
-read_spef -path u_skew_riscv /project/spef/clk_skew_adjust.spef  
-read_spef -path u_skew_uart  /project/spef/clk_skew_adjust.spef  
-read_spef -path u_skew_spi   /project/spef/clk_skew_adjust.spef  
-read_spef -path u_skew_sdram /project/spef/clk_skew_adjust.spef  
-read_spef -path u_skew_glbl  /project/spef/clk_skew_adjust.spef  
-read_spef -path u_skew_wh    /project/spef/clk_skew_adjust.spef  
-read_spef -path u_skew_sd_co /project/spef/clk_skew_adjust.spef  
-read_spef -path u_skew_sd_ci /project/spef/clk_skew_adjust.spef  
-read_spef -path u_skew_sp_co /project/spef/clk_skew_adjust.spef  
-read_spef -path u_glbl_cfg   /project/spef/glbl_cfg.spef  
-#read_spef -path u_riscv_top  /project/spef/scr1_top_wb.spef  
-#read_spef -path u_sdram_ctrl /project/spef/sdrc_top.spef  
-read_spef -path u_spi_master /project/spef/spim_top.spef  
-read_spef -path u_uart_core  /project/spef/uart_core.spef  
-read_spef -path u_wb_host    /project/spef/wb_host.spef  
-read_spef -path u_intercon   /project/spef/wb_interconnect.spef
-read_spef /project/spef/user_project_wrapper.spef  
+
+read_spef -path u_skew_wi    ../../spef/clk_skew_adjust.spef  
+read_spef -path u_skew_riscv ../../spef/clk_skew_adjust.spef  
+read_spef -path u_skew_uart  ../../spef/clk_skew_adjust.spef  
+read_spef -path u_skew_spi   ../../spef/clk_skew_adjust.spef  
+read_spef -path u_skew_sdram ../../spef/clk_skew_adjust.spef  
+read_spef -path u_skew_glbl  ../../spef/clk_skew_adjust.spef  
+read_spef -path u_skew_wh    ../../spef/clk_skew_adjust.spef  
+read_spef -path u_skew_sd_co ../../spef/clk_skew_adjust.spef  
+read_spef -path u_skew_sd_ci ../../spef/clk_skew_adjust.spef  
+read_spef -path u_skew_sp_co ../../spef/clk_skew_adjust.spef  
+read_spef -path u_glbl_cfg   ../../spef/glbl_cfg.spef  
+read_spef -path u_riscv_top  ../../spef/scr1_top_wb.spef  
+read_spef -path u_sdram_ctrl ../../spef/sdrc_top.spef  
+read_spef -path u_spi_master ../../spef/spim_top.spef  
+read_spef -path u_uart_core  ../../spef/uart_core.spef  
+read_spef -path u_wb_host    ../../spef/wb_host.spef  
+read_spef -path u_intercon   ../../spef/wb_interconnect.spef
+read_spef ../..//spef/user_project_wrapper.spef  
 
 
 read_sdc -echo $::env(BASE_SDC_FILE)
 
 # check for missing constraints
-check_setup  -verbose > unconstraints.rpt
+#check_setup  -verbose > unconstraints.rpt
 
 set_operating_conditions -analysis_type single
 # Propgate the clock
@@ -71,11 +75,25 @@
 
 report_tns
 report_wns
-report_power 
-report_checks -unique -slack_max -0.0 -group_count 100 
-report_checks -unique -slack_min -0.0 -group_count 100 
+#report_power 
+echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_max.rpt
+report_checks -unique -path_delay max -slack_max -0.0 -group_count 100 -corner wc >> timing_max.rpt
+report_checks -group_count 100 -path_delay max  -slack_max -0.01 -path_group $::env(WBM_CLOCK_NAME)       -corner wc  > timing_max.rpt
+report_checks -group_count 100 -path_delay max  -slack_max -0.01 -path_group $::env(WBS_CLOCK_NAME)       -corner wc  > timing_max.rpt
+report_checks -group_count 100 -path_delay max  -slack_max -0.01 -path_group $::env(SDRAM_CLOCK_NAME)     -corner wc  > timing_max.rpt
+report_checks -group_count 100 -path_delay max  -slack_max -0.01 -path_group $::env(PAD_SDRAM_CLOCK_NAME) -corner wc  > timing_max.rpt
+report_checks -group_count 100 -path_delay max  -slack_max -0.01 -path_group $::env(CPU_CLOCK_NAME)       -corner wc  > timing_max.rpt
+report_checks -group_count 100 -path_delay max  -slack_max -0.01 -path_group $::env(RTC_CLOCK_NAME)       -corner wc  > timing_max.rpt
+
+echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_min.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner bc >> timing_min.rpt
+report_checks -group_count 100  -path_delay min -slack_min -0.01 -path_group $::env(WBM_CLOCK_NAME)        -corner bc  > timing_min.rpt
+report_checks -group_count 100  -path_delay min -slack_min -0.01 -path_group $::env(WBS_CLOCK_NAME)        -corner bc  > timing_min.rpt
+report_checks -group_count 100  -path_delay min -slack_min -0.01 -path_group $::env(SDRAM_CLOCK_NAME)      -corner bc  > timing_min.rpt
+report_checks -group_count 100  -path_delay min -slack_min -0.01 -path_group $::env(PAD_SDRAM_CLOCK_NAME)  -corner bc  > timing_min.rpt
+report_checks -group_count 100  -path_delay min -slack_min -0.01 -path_group $::env(CPU_CLOCK_NAME)        -corner bc  > timing_min.rpt
+report_checks -group_count 100  -path_delay min -slack_min -0.01 -path_group $::env(RTC_CLOCK_NAME)        -corner bc  > timing_min.rpt
+
 report_checks -path_delay min_max 
-report_checks -group_count 100  -slack_max -0.01  > timing.rpt
 
-report_checks -group_count 100  -slack_min -0.01 >> timing.rpt
-
+exit
diff --git a/openlane/wb_host/base.sdc b/openlane/wb_host/base.sdc
index 0b5df4d..cd46516 100644
--- a/openlane/wb_host/base.sdc
+++ b/openlane/wb_host/base.sdc
@@ -18,9 +18,11 @@
 set_units -time ns
 set ::env(WBM_CLOCK_PERIOD) "10"
 set ::env(WBM_CLOCK_PORT)   "wbm_clk_i"
+set ::env(WBM_CLOCK_NAME)   "wbm_clk_i"
 
 set ::env(WBS_CLOCK_PERIOD) "10"
 set ::env(WBS_CLOCK_PORT)   "wbs_clk_i"
+set ::env(WBS_CLOCK_NAME)   "wbs_clk_i"
 
 ######################################
 # WB Clock domain input output
@@ -48,20 +50,35 @@
 set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port wbm_ack_o*]
 set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port wbm_err_o*]
 
-set_output_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_cyc_o*]
-set_output_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_stb_o*]
-set_output_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_adr_o*]
-set_output_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_we_o*]
-set_output_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_dat_o*]
-set_output_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_sel_o*]
+set_output_delay 4.5   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_cyc_o*]
+set_output_delay 4.5   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_stb_o*]
+set_output_delay 4.5   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_adr_o*]
+set_output_delay 4.5   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_we_o*]
+set_output_delay 4.5   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_dat_o*]
+set_output_delay 4.5   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_sel_o*]
 
 set_input_delay $wb_output_delay_value  -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_dat_i*]
 set_input_delay $wb_output_delay_value  -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_ack_i*]
 
 
+# WBM and WBS are async to each other
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WBM_CLOCK_PORT)] -group [get_clocks $::env(WBS_CLOCK_NAME)]
+
+set_clock_uncertainty -from $::env(WBM_CLOCK_NAME)          -to $::env(WBM_CLOCK_NAME)    -setup 0.400
+set_clock_uncertainty -from $::env(WBS_CLOCK_NAME)          -to $::env(WBS_CLOCK_NAME)    -setup 0.400
+
+set_clock_uncertainty -from $::env(WBM_CLOCK_NAME)          -to $::env(WBM_CLOCK_NAME)    -hold 0.050
+set_clock_uncertainty -from $::env(WBS_CLOCK_NAME)          -to $::env(WBS_CLOCK_NAME)    -hold 0.050
+
 # TODO set this as parameter
 set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
 set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
 puts "\[INFO\]: Setting load to: $cap_load"
 set_load  $cap_load [all_outputs]
 
+## 2 Multi-cycle setup and 0 hold
+set_multicycle_path -setup -from wbm_adr_i* 2
+set_multicycle_path -hold -from wbm_adr_i* 2
+
+set_multicycle_path -setup -from wbm_we_i* 2
+set_multicycle_path -hold -from wbm_we_i* 2
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index d0b09f1..6b90110 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -2,44 +2,29 @@
 
 #MANUAL_PLACE
 
-#E
-wbs_clk_i     0000 0 2   
-wbs_clk_out   
-cpu_clk
-rtc_clk
-wbd_int_rst_n
-cpu_rst_n
-spi_rst_n
-sdram_rst_n
-cfg_clk_ctrl1\[27\]
-cfg_clk_ctrl1\[26\]
-cfg_clk_ctrl1\[25\]
-cfg_clk_ctrl1\[24\]
-cfg_clk_ctrl1\[11\]
-cfg_clk_ctrl1\[10\]
-cfg_clk_ctrl1\[9\]
-cfg_clk_ctrl1\[8\]
-
 
 #W
+sdram_clk           0000 0 4
+sdram_rst_n
+cpu_rst_n
+spi_rst_n
 cfg_clk_ctrl1\[15\]
 cfg_clk_ctrl1\[14\]
 cfg_clk_ctrl1\[13\]
 cfg_clk_ctrl1\[12\]
-sdram_clk
 
 
 
 
 #S
-user_clock2     0000 0  2
-user_clock1  
+user_clock2     
+user_clock1     
 wbm_clk_i       
-wbm_rst_i        
+wbm_rst_i       
 wbm_ack_o       
-wbm_cyc_i        
-wbm_stb_i        
-wbm_we_i         
+wbm_cyc_i       
+wbm_stb_i       
+wbm_we_i        
 wbm_adr_i\[0\]  
 wbm_dat_i\[0\]  
 wbm_dat_o\[0\]  
@@ -74,41 +59,42 @@
 wbm_adr_i\[9\]  
 wbm_dat_i\[9\]  
 wbm_dat_o\[9\]  
-wbm_adr_i\[10\]  
-wbm_dat_i\[10\]  
-wbm_dat_o\[10\]  
-wbm_adr_i\[11\]  
-wbm_dat_i\[11\]  
-wbm_dat_o\[11\]  
-wbm_adr_i\[12\]  
-wbm_dat_i\[12\]  
-wbm_dat_o\[12\]  
-wbm_adr_i\[13\]  
-wbm_dat_i\[13\]  
-wbm_dat_o\[13\]  
-wbm_adr_i\[14\]  
-wbm_dat_i\[14\]  
-wbm_dat_o\[14\]  
-wbm_adr_i\[15\]  
-wbm_dat_i\[15\]  
-wbm_dat_o\[15\]  
-wbm_adr_i\[16\]  
-wbm_dat_i\[16\]  
-wbm_dat_o\[16\]  
-wbm_adr_i\[17\]  
-wbm_dat_i\[17\]  
-wbm_dat_o\[17\]  
-wbm_adr_i\[18\]  
-wbm_dat_i\[18\]  
-wbm_dat_o\[18\]  
-wbm_adr_i\[19\]  
-wbm_dat_i\[19\]  
-wbm_dat_o\[19\]  
-wbm_adr_i\[20\]  
-wbm_dat_i\[20\]  
-wbm_dat_o\[20\]  
-wbm_adr_i\[21\]  
-wbm_dat_i\[21\]  
+wbm_adr_i\[10\] 
+wbm_dat_i\[10\] 
+wbm_dat_o\[10\] 
+wbm_adr_i\[11\] 
+wbm_dat_i\[11\] 
+wbm_dat_o\[11\] 
+wbm_adr_i\[12\] 
+wbm_dat_i\[12\] 
+wbm_dat_o\[12\] 
+wbm_adr_i\[13\] 
+wbm_dat_i\[13\] 
+wbm_dat_o\[13\] 
+wbm_adr_i\[14\] 
+wbm_dat_i\[14\] 
+wbm_dat_o\[14\] 
+wbm_adr_i\[15\] 
+wbm_dat_i\[15\] 
+wbm_dat_o\[15\] 
+wbm_adr_i\[16\] 
+wbm_dat_i\[16\] 
+wbm_dat_o\[16\] 
+wbm_adr_i\[17\] 
+
+wbm_dat_i\[17\] 
+wbm_dat_o\[17\] 
+wbm_adr_i\[18\] 
+wbm_dat_i\[18\] 
+wbm_dat_o\[18\] 
+wbm_adr_i\[19\] 
+wbm_dat_i\[19\] 
+wbm_dat_o\[19\] 
+wbm_adr_i\[20\] 
+wbm_dat_i\[20\] 
+wbm_dat_o\[20\] 
+wbm_adr_i\[21\] 
+wbm_dat_i\[21\] 
 wbm_dat_o\[21\]  
 wbm_adr_i\[22\]  
 wbm_dat_i\[22\]  
@@ -142,6 +128,19 @@
 wbm_dat_o\[31\]  
 wbm_err_o        
 
+cfg_clk_ctrl1\[11\] 200 0 4
+cfg_clk_ctrl1\[10\]
+cfg_clk_ctrl1\[9\]
+cfg_clk_ctrl1\[8\]
+cfg_clk_ctrl1\[27\]
+cfg_clk_ctrl1\[26\]
+cfg_clk_ctrl1\[25\]
+cfg_clk_ctrl1\[24\]
+wbs_clk_i            400 0 4
+wbs_clk_out   
+cpu_clk
+rtc_clk
+wbd_int_rst_n
 
 #N
 wbs_stb_o        0000 0 2
diff --git a/openlane/wb_interconnect/base.sdc b/openlane/wb_interconnect/base.sdc
index 6cadf2f..9be4a55 100644
--- a/openlane/wb_interconnect/base.sdc
+++ b/openlane/wb_interconnect/base.sdc
@@ -32,6 +32,8 @@
 set rst_indx [lsearch [all_inputs] [get_port rst_n]]
 set all_inputs_wo_clk_rst [lreplace [all_inputs] $clk_indx $rst_indx]
 
+set_clock_uncertainty -from $::env(CLOCK_PORT) -to $::env(CLOCK_PORT)  -setup 0.400
+set_clock_uncertainty -from $::env(CLOCK_PORT) -to $::env(CLOCK_PORT)  -hold  0.050
 
 # correct resetn
 set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
diff --git a/signoff/clk_buf/OPENLANE_VERSION b/signoff/clk_buf/OPENLANE_VERSION
new file mode 100644
index 0000000..a2633b1
--- /dev/null
+++ b/signoff/clk_buf/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane rc7
diff --git a/signoff/clk_buf/PDK_SOURCES b/signoff/clk_buf/PDK_SOURCES
new file mode 100644
index 0000000..8b58bd5
--- /dev/null
+++ b/signoff/clk_buf/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane 
+a68c95289612a361870acedb7f6478fcfae32e49
+-ne skywater-pdk 
+f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+-ne open_pdks 
+522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/clk_buf/final_summary_report.csv b/signoff/clk_buf/final_summary_report.csv
new file mode 100644
index 0000000..c4c7b1f
--- /dev/null
+++ b/signoff/clk_buf/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/clk_buf,clk_buf,clk_buf,Flow_completed,0h1m1s,0h0m25s,1851.851851851852,0.0009,1111.111111111111,8,379.25,1,0,0,0,0,0,0,0,0,0,0,0,41,4,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,45365,0.0,0.93,0.53,0.0,-1,-1,2,2,2,2,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,14,4,0,18,90.9090909090909,11,10,AREA 0,5,60,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
index 359db11..1ec2d16 100644
--- a/signoff/glbl_cfg/final_summary_report.csv
+++ b/signoff/glbl_cfg/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h5m23s,0h3m25s,45883.33333333334,0.12,22941.66666666667,40,553.93,2753,0,0,0,0,0,0,0,4,0,-1,0,141562,23694,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,98863982,0.0,29.06,28.48,0.34,-1,-1,2637,2802,459,624,0,0,0,2753,1,0,3,0,471,0,0,562,577,533,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h5m16s,0h3m23s,45883.33333333334,0.12,22941.66666666667,40,559.94,2753,0,0,0,0,0,0,0,1,0,-1,0,141067,23714,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,98939272,0.0,28.84,28.31,0.23,-1,-1,2637,2802,459,624,0,0,0,2753,1,0,3,0,471,0,0,562,577,533,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
index 7d8ac3a..9f8bba1 100644
--- a/signoff/sdram/final_summary_report.csv
+++ b/signoff/sdram/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h9m25s,0h5m13s,41131.42857142857,0.35,20565.714285714286,27,654.48,7198,0,0,0,0,0,0,0,14,0,-1,0,307108,51429,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,245789185,0.0,20.86,16.44,1.36,-1,-1,7102,7361,1246,1505,0,0,0,7198,197,107,83,94,354,211,32,2289,1267,1186,27,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h8m49s,0h4m33s,41131.42857142857,0.35,20565.714285714286,27,656.29,7198,0,0,0,0,0,0,0,14,0,-1,0,307108,51429,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,245789185,0.0,20.86,16.44,1.36,-1,-1,7102,7361,1246,1505,0,0,0,7198,197,107,83,94,354,211,32,2289,1267,1186,27,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
index dae8ae2..9d40c99 100644
--- a/signoff/spi_master/final_summary_report.csv
+++ b/signoff/spi_master/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h6m47s,0h3m51s,45758.33333333334,0.24,22879.16666666667,33,615.0,5491,0,0,0,0,0,0,0,4,4,-1,0,244856,41928,-0.01,-0.01,0.0,0.0,0.0,-0.01,-0.01,0.0,0.0,0.0,192084576,0.0,17.57,28.06,0.0,-1,-1,5427,5567,901,1041,0,0,0,5491,223,0,184,93,748,126,37,1613,982,921,24,424,2889,0,3313,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h7m22s,0h4m17s,45758.33333333334,0.24,22879.16666666667,33,609.27,5491,0,0,0,0,0,0,0,4,4,-1,0,244856,41928,-0.01,-0.01,0.0,0.0,0.0,-0.01,-0.01,0.0,0.0,0.0,192084576,0.0,17.57,28.06,0.0,-1,-1,5427,5567,901,1041,0,0,0,5491,223,0,184,93,748,126,37,1613,982,921,24,424,2889,0,3313,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index a01c86f..0fd7224 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h51m11s,0h28m28s,34498.88888888888,1.8,17249.44444444444,23,1210.03,31049,0,0,0,0,0,0,0,76,9,-1,0,1617218,250691,-4.42,-4.42,-4.38,-4.38,-4.45,-34.56,-34.56,-34.86,-34.86,-35.41,1349556396,0.0,18.48,16.7,4.85,0.56,-1,30872,31173,2777,3078,0,0,0,31049,637,0,695,2031,3988,2108,1314,7432,2838,2808,95,866,22836,0,23702,69.20415224913495,14.45,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h53m13s,0h28m58s,34498.88888888888,1.8,17249.44444444444,23,1213.48,31049,0,0,0,0,0,0,0,57,10,-1,0,1624212,251814,-4.82,-4.82,-4.79,-4.79,-4.92,-38.56,-38.56,-38.91,-38.91,-39.55,1349556396,0.0,18.58,16.71,4.86,0.69,-1,30872,31173,2777,3078,0,0,0,31049,637,0,695,2031,3988,2108,1314,7432,2838,2808,95,866,22836,5,23707,67.02412868632707,14.92,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/uart/final_summary_report.csv b/signoff/uart/final_summary_report.csv
index 63ea5b4..ee96d6e 100644
--- a/signoff/uart/final_summary_report.csv
+++ b/signoff/uart/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart,uart_core,uart,Flow_completed,0h4m21s,0h2m40s,46166.66666666667,0.12,23083.333333333336,35,540.52,2770,0,0,0,0,0,0,0,0,0,-1,0,91807,20722,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,62462955,0.0,19.42,18.96,0.0,-1,-1,2769,2789,456,476,0,0,0,2770,56,0,29,41,182,125,26,685,435,396,18,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/uart,uart_core,uart,Flow_completed,0h4m44s,0h2m53s,46166.66666666667,0.12,23083.333333333336,35,547.19,2770,0,0,0,0,0,0,0,0,0,-1,0,93003,20847,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,62462955,0.0,19.71,19.11,0.0,-1,-1,2769,2789,456,476,0,0,0,2770,56,0,29,41,182,125,26,685,435,396,18,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index cd729d9..9d16e43 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h40m38s,0h4m51s,3.3079078455790785,10.2784,1.6539539227895392,0,568.44,17,0,0,0,0,0,0,0,0,24,-1,-1,1182176,4163,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.24,4.03,1.04,2.32,-1,848,1466,848,1466,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h41m55s,0h4m57s,4.086239103362392,10.2784,2.043119551681196,0,570.2,21,0,0,0,0,0,0,0,0,38,-1,-1,1176072,4123,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.35,4.28,0.87,1.77,-1,852,1470,852,1470,0,0,0,21,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 2cc30c1..7d06a32 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h5m36s,0h3m45s,61400.0,0.1,30700.0,49,587.03,3070,0,0,0,0,0,0,0,1,0,-1,0,173130,26433,-2.81,-2.81,-2.74,-2.74,-2.73,-85.26,-85.26,-84.77,-84.77,-85.68,139031696,0.0,48.06,23.93,17.81,-1,-1,2926,3180,551,805,0,0,0,3070,78,0,3,11,50,27,10,799,605,775,14,130,1139,0,1269,78.55459544383346,12.73,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h5m14s,0h3m25s,61400.0,0.1,30700.0,49,582.5,3070,0,0,0,0,0,0,0,0,0,-1,0,172500,26194,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,140873672,0.0,49.1,23.43,16.91,-1,-1,2926,3180,551,805,0,0,0,3070,78,0,3,11,50,27,10,799,605,775,14,130,1139,0,1269,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index 61ca705..afa6597 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h8m41s,0h4m48s,5868.181818181818,0.44,2934.090909090909,5,582.16,1291,0,0,0,0,0,0,0,1,0,-1,0,483038,20167,0.0,0.0,0.0,0.0,-1.08,0.0,0.0,0.0,0.0,-86.31,415470896,0.0,32.3,8.43,19.36,-1,-1,1041,1614,204,777,0,0,0,1291,244,0,75,15,111,0,0,180,431,414,11,130,5189,0,5319,90.25270758122744,11.08,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h10m20s,0h6m12s,5868.181818181818,0.44,2934.090909090909,5,576.81,1291,0,0,0,0,0,0,0,2,0,-1,0,483765,20458,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,415470896,0.0,32.05,8.47,19.72,-1,-1,1041,1614,204,777,0,0,0,1291,244,0,75,15,111,0,0,180,431,414,11,130,5189,0,5319,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 2cb80c3..666880f 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -476,6 +476,25 @@
 	force uut.mprj.u_wb_host.u_clkbuf_rtc.VGND =VSS;
 	force uut.mprj.u_wb_host.u_clkbuf_rtc.VNB = VSS;
 
+	force uut.mprj.u_buf1_wb_rstn.u_buf.VPWR =USER_VDD1V8;
+	force uut.mprj.u_buf1_wb_rstn.u_buf.VPB  =USER_VDD1V8;
+	force uut.mprj.u_buf1_wb_rstn.u_buf.VGND =VSS;
+	force uut.mprj.u_buf1_wb_rstn.u_buf.VNB = VSS;
+
+	force uut.mprj.u_buf2_wb_rstn.u_buf.VPWR =USER_VDD1V8;
+	force uut.mprj.u_buf2_wb_rstn.u_buf.VPB  =USER_VDD1V8;
+	force uut.mprj.u_buf2_wb_rstn.u_buf.VGND =VSS;
+	force uut.mprj.u_buf2_wb_rstn.u_buf.VNB = VSS;
+
+	force uut.mprj.u_buf1_wbclk.u_buf.VPWR =USER_VDD1V8;
+	force uut.mprj.u_buf1_wbclk.u_buf.VPB  =USER_VDD1V8;
+	force uut.mprj.u_buf1_wbclk.u_buf.VGND =VSS;
+	force uut.mprj.u_buf1_wbclk.u_buf.VNB = VSS;
+
+	force uut.mprj.u_buf2_wbclk.u_buf.VPWR =USER_VDD1V8;
+	force uut.mprj.u_buf2_wbclk.u_buf.VPB  =USER_VDD1V8;
+	force uut.mprj.u_buf2_wbclk.u_buf.VGND =VSS;
+	force uut.mprj.u_buf2_wbclk.u_buf.VNB = VSS;
     end
 `endif    
 
diff --git a/verilog/dv/user_risc_boot/uprj_netlists.v b/verilog/dv/user_risc_boot/uprj_netlists.v
index ae6502e..29925ab 100644
--- a/verilog/dv/user_risc_boot/uprj_netlists.v
+++ b/verilog/dv/user_risc_boot/uprj_netlists.v
@@ -35,6 +35,7 @@
         `include "syntacore.v"
         `include "wb_host.v"
 	`include "clk_skew_adjust.v"
+	`include "clk_buf.v"
 
 `else
 
@@ -60,6 +61,7 @@
      `include "lib/async_fifo_th.sv"  
      `include "lib/reset_sync.sv"  
      `include "lib/double_sync_low.v"  
+     `include "lib/clk_buf.v"  
 
      `include "sdram_ctrl/src/top/sdrc_top.v" 
      `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v" 
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index aa4c71a..8da63e3 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -346,6 +346,25 @@
 	force u_top.u_wb_host.u_clkbuf_rtc.VPB  =USER_VDD1V8;
 	force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
 	force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
+	force u_top.u_buf1_wb_rstn.u_buf.VPWR =USER_VDD1V8;
+	force u_top.u_buf1_wb_rstn.u_buf.VPB  =USER_VDD1V8;
+	force u_top.u_buf1_wb_rstn.u_buf.VGND =VSS;
+	force u_top.u_buf1_wb_rstn.u_buf.VNB = VSS;
+
+	force u_top.u_buf2_wb_rstn.u_buf.VPWR =USER_VDD1V8;
+	force u_top.u_buf2_wb_rstn.u_buf.VPB  =USER_VDD1V8;
+	force u_top.u_buf2_wb_rstn.u_buf.VGND =VSS;
+	force u_top.u_buf2_wb_rstn.u_buf.VNB = VSS;
+
+	force u_top.u_buf1_wbclk.u_buf.VPWR =USER_VDD1V8;
+	force u_top.u_buf1_wbclk.u_buf.VPB  =USER_VDD1V8;
+	force u_top.u_buf1_wbclk.u_buf.VGND =VSS;
+	force u_top.u_buf1_wbclk.u_buf.VNB = VSS;
+
+	force u_top.u_buf2_wbclk.u_buf.VPWR =USER_VDD1V8;
+	force u_top.u_buf2_wbclk.u_buf.VPB  =USER_VDD1V8;
+	force u_top.u_buf2_wbclk.u_buf.VGND =VSS;
+	force u_top.u_buf2_wbclk.u_buf.VNB = VSS;
     end
 `endif    
 
diff --git a/verilog/dv/user_spi/uprj_netlists.v b/verilog/dv/user_spi/uprj_netlists.v
index ae6502e..29925ab 100644
--- a/verilog/dv/user_spi/uprj_netlists.v
+++ b/verilog/dv/user_spi/uprj_netlists.v
@@ -35,6 +35,7 @@
         `include "syntacore.v"
         `include "wb_host.v"
 	`include "clk_skew_adjust.v"
+	`include "clk_buf.v"
 
 `else
 
@@ -60,6 +61,7 @@
      `include "lib/async_fifo_th.sv"  
      `include "lib/reset_sync.sv"  
      `include "lib/double_sync_low.v"  
+     `include "lib/clk_buf.v"  
 
      `include "sdram_ctrl/src/top/sdrc_top.v" 
      `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v" 
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index 60ad1f9..9b1e753 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -480,6 +480,25 @@
 	force u_top.u_wb_host.u_clkbuf_rtc.VPB  =USER_VDD1V8;
 	force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
 	force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
+	force u_top.u_buf1_wb_rstn.u_buf.VPWR =USER_VDD1V8;
+	force u_top.u_buf1_wb_rstn.u_buf.VPB  =USER_VDD1V8;
+	force u_top.u_buf1_wb_rstn.u_buf.VGND =VSS;
+	force u_top.u_buf1_wb_rstn.u_buf.VNB = VSS;
+
+	force u_top.u_buf2_wb_rstn.u_buf.VPWR =USER_VDD1V8;
+	force u_top.u_buf2_wb_rstn.u_buf.VPB  =USER_VDD1V8;
+	force u_top.u_buf2_wb_rstn.u_buf.VGND =VSS;
+	force u_top.u_buf2_wb_rstn.u_buf.VNB = VSS;
+
+	force u_top.u_buf1_wbclk.u_buf.VPWR =USER_VDD1V8;
+	force u_top.u_buf1_wbclk.u_buf.VPB  =USER_VDD1V8;
+	force u_top.u_buf1_wbclk.u_buf.VGND =VSS;
+	force u_top.u_buf1_wbclk.u_buf.VNB = VSS;
+
+	force u_top.u_buf2_wbclk.u_buf.VPWR =USER_VDD1V8;
+	force u_top.u_buf2_wbclk.u_buf.VPB  =USER_VDD1V8;
+	force u_top.u_buf2_wbclk.u_buf.VGND =VSS;
+	force u_top.u_buf2_wbclk.u_buf.VNB = VSS;
     end
 `endif    
 
diff --git a/verilog/dv/user_uart/uprj_netlists.v b/verilog/dv/user_uart/uprj_netlists.v
index e8f024b..89364ec 100644
--- a/verilog/dv/user_uart/uprj_netlists.v
+++ b/verilog/dv/user_uart/uprj_netlists.v
@@ -34,6 +34,7 @@
         `include "syntacore.v"
         `include "wb_host.v"
 	`include "clk_skew_adjust.v"
+	`include "clk_buf.v"
 
 `else
      `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
@@ -58,6 +59,7 @@
      `include "lib/async_fifo_th.sv"  
      `include "lib/reset_sync.sv"  
      `include "lib/double_sync_low.v"  
+     `include "lib/clk_buf.v"  
 
      `include "sdram_ctrl/src/top/sdrc_top.v" 
      `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v" 
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index d6fb8a0..986be10 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -385,6 +385,26 @@
 	force u_top.u_wb_host.u_clkbuf_rtc.VPB  =USER_VDD1V8;
 	force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
 	force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
+
+	force u_top.u_buf1_wb_rstn.u_buf.VPWR =USER_VDD1V8;
+	force u_top.u_buf1_wb_rstn.u_buf.VPB  =USER_VDD1V8;
+	force u_top.u_buf1_wb_rstn.u_buf.VGND =VSS;
+	force u_top.u_buf1_wb_rstn.u_buf.VNB = VSS;
+
+	force u_top.u_buf2_wb_rstn.u_buf.VPWR =USER_VDD1V8;
+	force u_top.u_buf2_wb_rstn.u_buf.VPB  =USER_VDD1V8;
+	force u_top.u_buf2_wb_rstn.u_buf.VGND =VSS;
+	force u_top.u_buf2_wb_rstn.u_buf.VNB = VSS;
+
+	force u_top.u_buf1_wbclk.u_buf.VPWR =USER_VDD1V8;
+	force u_top.u_buf1_wbclk.u_buf.VPB  =USER_VDD1V8;
+	force u_top.u_buf1_wbclk.u_buf.VGND =VSS;
+	force u_top.u_buf1_wbclk.u_buf.VNB = VSS;
+
+	force u_top.u_buf2_wbclk.u_buf.VPWR =USER_VDD1V8;
+	force u_top.u_buf2_wbclk.u_buf.VPB  =USER_VDD1V8;
+	force u_top.u_buf2_wbclk.u_buf.VGND =VSS;
+	force u_top.u_buf2_wbclk.u_buf.VNB = VSS;
     end
 `endif    
 //------------------------------------------------------
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index 7b12e0e..b045e13 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -261,6 +261,25 @@
 	force uut.mprj.u_wb_host.u_clkbuf_rtc.VGND =VSS;
 	force uut.mprj.u_wb_host.u_clkbuf_rtc.VNB = VSS;
 
+	force uut.mprj.u_buf1_wb_rstn.u_buf.VPWR =USER_VDD1V8;
+	force uut.mprj.u_buf1_wb_rstn.u_buf.VPB  =USER_VDD1V8;
+	force uut.mprj.u_buf1_wb_rstn.u_buf.VGND =VSS;
+	force uut.mprj.u_buf1_wb_rstn.u_buf.VNB = VSS;
+
+	force uut.mprj.u_buf2_wb_rstn.u_buf.VPWR =USER_VDD1V8;
+	force uut.mprj.u_buf2_wb_rstn.u_buf.VPB  =USER_VDD1V8;
+	force uut.mprj.u_buf2_wb_rstn.u_buf.VGND =VSS;
+	force uut.mprj.u_buf2_wb_rstn.u_buf.VNB = VSS;
+
+	force uut.mprj.u_buf1_wbclk.u_buf.VPWR =USER_VDD1V8;
+	force uut.mprj.u_buf1_wbclk.u_buf.VPB  =USER_VDD1V8;
+	force uut.mprj.u_buf1_wbclk.u_buf.VGND =VSS;
+	force uut.mprj.u_buf1_wbclk.u_buf.VNB = VSS;
+
+	force uut.mprj.u_buf2_wbclk.u_buf.VPWR =USER_VDD1V8;
+	force uut.mprj.u_buf2_wbclk.u_buf.VPB  =USER_VDD1V8;
+	force uut.mprj.u_buf2_wbclk.u_buf.VGND =VSS;
+	force uut.mprj.u_buf2_wbclk.u_buf.VNB = VSS;
     end
 `endif    
 endmodule
diff --git a/verilog/rtl/lib/clk_buf.v b/verilog/rtl/lib/clk_buf.v
new file mode 100644
index 0000000..dad8fc6
--- /dev/null
+++ b/verilog/rtl/lib/clk_buf.v
@@ -0,0 +1,85 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Clk Buf                                                     ////
+////                                                              ////
+////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/yifive_r0.git              ////
+////  http://www.opencores.org/cores/yifive/                      ////
+////                                                              ////
+////  Description                                                 ////
+////     Adding clock buf for manual clock tree at SOC level      ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+
+module clk_buf (
+   // Outputs
+       clk_o,
+   // Inputs
+       clk_i
+   );
+
+//---------------------------------------------
+// All the input to this block are declared here
+// --------------------------------------------
+   input        clk_i          ;// 
+   
+//---------------------------------------------
+// All the output to this block are declared here
+// --------------------------------------------
+   output       clk_o             ; // clock out
+
+               
+
+sky130_fd_sc_hd__clkbuf_16 u_buf  (.A(clk_i),.X(clk_o));
+
+endmodule 
+
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index ae6502e..29925ab 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -35,6 +35,7 @@
         `include "syntacore.v"
         `include "wb_host.v"
 	`include "clk_skew_adjust.v"
+	`include "clk_buf.v"
 
 `else
 
@@ -60,6 +61,7 @@
      `include "lib/async_fifo_th.sv"  
      `include "lib/reset_sync.sv"  
      `include "lib/double_sync_low.v"  
+     `include "lib/clk_buf.v"  
 
      `include "sdram_ctrl/src/top/sdrc_top.v" 
      `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v" 
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index bb9c9b2..35e10c8 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -271,7 +271,11 @@
 wire                              cpu_clk       ;
 wire                              rtc_clk       ;
 wire                              wbd_clk_int   ;
+wire                              wbd_clk_int1  ;
+wire                              wbd_clk_int2  ;
 wire                              wbd_int_rst_n ;
+wire                              wbd_int1_rst_n ;
+wire                              wbd_int2_rst_n ;
 
 wire [31:0]                       fuse_mhartid  ;
 wire [15:0]                       irq_lines     ;
@@ -348,6 +352,11 @@
 //assign la_data_out    = {riscv_debug,spi_debug,sdram_debug};
 assign la_data_out[127:0]    = {sdram_debug,spi_debug,riscv_debug};
 
+clk_buf u_buf1_wb_rstn  (.clk_i(wbd_int_rst_n),.clk_o(wbd_int1_rst_n));
+clk_buf u_buf2_wb_rstn  (.clk_i(wbd_int1_rst_n),.clk_o(wbd_int2_rst_n));
+
+clk_buf u_buf1_wbclk    (.clk_i(wbd_clk_int),.clk_o(wbd_clk_int1));
+clk_buf u_buf2_wbclk    (.clk_i(wbd_clk_int1),.clk_o(wbd_clk_int2));
 
 wb_host u_wb_host(
        .user_clock1      (wb_clk_i             ),
@@ -495,7 +504,7 @@
     .sdram_debug            (sdram_debug                ),
                     
     // WB bus
-    .wb_rst_n               (wbd_int_rst_n              ),
+    .wb_rst_n               (wbd_int2_rst_n             ),
     .wb_clk_i               (wbd_clk_sdram              ),
     
     .wb_stb_i               (wbd_sdram_stb_o            ),
@@ -535,7 +544,7 @@
 
 wb_interconnect  u_intercon (
          .clk_i         (wbd_clk_wi            ), 
-         .rst_n         (wbd_int_rst_n         ),
+         .rst_n         (wbd_int2_rst_n        ),
 
          // Master 0 Interface
          .m0_wbd_dat_i  (wbd_int_dat_i         ),
@@ -619,7 +628,7 @@
 glbl_cfg   u_glbl_cfg (
 
        .mclk                   (wbd_clk_glbl              ),
-       .reset_n                (wbd_int_rst_n             ),
+       .reset_n                (wbd_int2_rst_n            ),
 
         // Reg Bus Interface Signal
        .reg_cs                 (wbd_glbl_stb_o            ),
@@ -660,7 +669,7 @@
         );
 
 uart_core   u_uart_core (
-        .arst_n                 (wbd_int_rst_n            ), // async reset
+        .arst_n                 (wbd_int1_rst_n           ), // async reset
         .app_clk                (wbd_clk_uart             ),
 
         // Reg Bus Interface Signal
@@ -692,7 +701,7 @@
                .vccd1      (vccd1                      ),// User area 1 1.8V supply
                .vssd1      (vssd1                      ),// User area 1 digital ground
 `endif
-	       .clk_in     (wbd_clk_int                 ), 
+	       .clk_in     (wbd_clk_int1                ), 
 	       .sel        (cfg_cska_wi                 ), 
 	       .clk_out    (wbd_clk_wi                  ) 
        );
@@ -716,7 +725,7 @@
                .vccd1      (vccd1                      ),// User area 1 1.8V supply
                .vssd1      (vssd1                      ),// User area 1 digital ground
 `endif
-	       .clk_in     (wbd_clk_int                 ), 
+	       .clk_in     (wbd_clk_int1                ), 
 	       .sel        (cfg_cska_uart               ), 
 	       .clk_out    (wbd_clk_uart                ) 
        );
@@ -728,7 +737,7 @@
                .vccd1      (vccd1                      ),// User area 1 1.8V supply
                .vssd1      (vssd1                      ),// User area 1 digital ground
 `endif
-	       .clk_in     (wbd_clk_int                ), 
+	       .clk_in     (wbd_clk_int2               ), 
 	       .sel        (cfg_cska_spi               ), 
 	       .clk_out    (wbd_clk_spi                ) 
        );
@@ -740,7 +749,7 @@
                .vccd1      (vccd1                      ),// User area 1 1.8V supply
                .vssd1      (vssd1                      ),// User area 1 digital ground
 `endif
-	       .clk_in     (wbd_clk_int                ), 
+	       .clk_in     (wbd_clk_int2               ), 
 	       .sel        (cfg_cska_sdram             ), 
 	       .clk_out    (wbd_clk_sdram              ) 
        );
@@ -752,7 +761,7 @@
                .vccd1      (vccd1                      ),// User area 1 1.8V supply
                .vssd1      (vssd1                      ),// User area 1 digital ground
 `endif
-	       .clk_in     (wbd_clk_int               ), 
+	       .clk_in     (wbd_clk_int2              ), 
 	       .sel        (cfg_cska_glbl             ), 
 	       .clk_out    (wbd_clk_glbl              ) 
        );