diff --git a/openlane/clk_skew_adjust/config.tcl b/openlane/clk_skew_adjust/config.tcl
new file mode 100644
index 0000000..0c507cc
--- /dev/null
+++ b/openlane/clk_skew_adjust/config.tcl
@@ -0,0 +1,89 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Base Configurations. Don't Touch
+# section begin
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) clk_skew_adjust
+set verilog_root $script_dir/../../verilog/
+set lef_root $script_dir/../../lef/
+set gds_root $script_dir/../../gds/
+#section end
+
+# User Configurations
+#
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) "0"
+set ::env(SYNTH_READ_BLACKBOX_LIB) "1"
+
+
+## Source Verilog Files
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv"
+
+## Clock configurations
+set ::env(CLOCK_PORT) "clk_in"
+
+set ::env(CLOCK_PERIOD) "10"
+
+## Internal Macros
+### Macro Placement
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 50 50"
+set ::env(PL_TARGET_DENSITY) 0.85
+set ::env(FP_CORE_UTIL) "60"
+
+
+
+set ::env(FP_PDN_CHECK_NODES) 0
+
+set ::env(RUN_KLAYOUT_DRC) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+# The following is because there are no std cells in the example wrapper project.
+set ::env(SYNTH_TOP_LEVEL) 1
+
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+
+# No Synthesis and CTS
+set ::env(RUN_SIMPLE_CTS) 0
+set ::env(SYNTH_BUFFERING) 0
+set ::env(SYNTH_SIZING) 0
+set ::env(CLOCK_TREE_SYNTH) 0
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
+set ::env(FILL_INSERTION) 1
+set ::env(RUN_SIMPLE_CTS) 0
+set ::env(LVS_CONNECT_BY_LABEL) 1
+set ::env(CELL_PAD) 0
+
+
+
+
+set ::env(PL_ROUTABILITY_DRIVEN) 1
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+set ::env(GLB_RT_MAXLAYER) 4
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/clk_skew_adjust/pin_order.cfg b/openlane/clk_skew_adjust/pin_order.cfg
new file mode 100644
index 0000000..73fa0a0
--- /dev/null
+++ b/openlane/clk_skew_adjust/pin_order.cfg
@@ -0,0 +1,13 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#W
+clk_out              0000 0
+
+#E
+clk_in              0000 0
+sel\[3\]            0000 10
+sel\[2\]            0000 11
+sel\[1\]            0000 12
+sel\[0\]            0000 13
diff --git a/openlane/glbl_cfg/pin_order.cfg b/openlane/glbl_cfg/pin_order.cfg
index 5867718..022eda4 100644
--- a/openlane/glbl_cfg/pin_order.cfg
+++ b/openlane/glbl_cfg/pin_order.cfg
@@ -4,59 +4,11 @@
 #E
 cpu_clk                0000 0
 rtc_clk                
-irq_lines\[15\]        
-irq_lines\[14\]        
-irq_lines\[13\]        
-irq_lines\[12\]        
-irq_lines\[11\]        
-irq_lines\[10\]        
-irq_lines\[9\]         
-irq_lines\[8\]         
-irq_lines\[7\]         
-irq_lines\[6\]         
-irq_lines\[5\]         
-irq_lines\[4\]         
-irq_lines\[3\]         
-irq_lines\[2\]         
-irq_lines\[1\]         
-irq_lines\[0\]         
-soft_irq               
-fuse_mhartid\[31\]     
-fuse_mhartid\[30\]     
-fuse_mhartid\[29\]     
-fuse_mhartid\[28\]     
-fuse_mhartid\[27\]     
-fuse_mhartid\[26\]     
-fuse_mhartid\[25\]     
-fuse_mhartid\[24\]     
-fuse_mhartid\[23\]     
-fuse_mhartid\[22\]     
-fuse_mhartid\[21\]     
-fuse_mhartid\[20\]     
-fuse_mhartid\[19\]     
-fuse_mhartid\[18\]     
-fuse_mhartid\[17\]     
-fuse_mhartid\[16\]     
-fuse_mhartid\[15\]     
-fuse_mhartid\[14\]     
-fuse_mhartid\[13\]     
-fuse_mhartid\[12\]     
-fuse_mhartid\[11\]     
-fuse_mhartid\[10\]     
-fuse_mhartid\[9\]      
-fuse_mhartid\[8\]      
-fuse_mhartid\[7\]      
-fuse_mhartid\[6\]      
-fuse_mhartid\[5\]      
-fuse_mhartid\[4\]      
-fuse_mhartid\[3\]      
-fuse_mhartid\[2\]      
-fuse_mhartid\[1\]      
-fuse_mhartid\[0\]      
 
 #N
 mclk                   0000 0
 reset_n                
+user_clock1            
 user_clock2            
 user_irq\[2\]          
 user_irq\[1\]          
@@ -237,3 +189,55 @@
 reg_rdata\[1\]      
 reg_rdata\[0\]      
 reg_ack             
+
+
+irq_lines\[15\]    200 0 2    
+irq_lines\[14\]        
+irq_lines\[13\]        
+irq_lines\[12\]        
+irq_lines\[11\]        
+irq_lines\[10\]        
+irq_lines\[9\]         
+irq_lines\[8\]         
+irq_lines\[7\]         
+irq_lines\[6\]         
+irq_lines\[5\]         
+irq_lines\[4\]         
+irq_lines\[3\]         
+irq_lines\[2\]         
+irq_lines\[1\]         
+irq_lines\[0\]         
+soft_irq               
+fuse_mhartid\[31\]     
+fuse_mhartid\[30\]     
+fuse_mhartid\[29\]     
+fuse_mhartid\[28\]     
+fuse_mhartid\[27\]     
+fuse_mhartid\[26\]     
+fuse_mhartid\[25\]     
+fuse_mhartid\[24\]     
+fuse_mhartid\[23\]     
+fuse_mhartid\[22\]     
+fuse_mhartid\[21\]     
+fuse_mhartid\[20\]     
+fuse_mhartid\[19\]     
+fuse_mhartid\[18\]     
+fuse_mhartid\[17\]     
+fuse_mhartid\[16\]     
+fuse_mhartid\[15\]     
+fuse_mhartid\[14\]     
+fuse_mhartid\[13\]     
+fuse_mhartid\[12\]     
+fuse_mhartid\[11\]     
+fuse_mhartid\[10\]     
+fuse_mhartid\[9\]      
+fuse_mhartid\[8\]      
+fuse_mhartid\[7\]      
+fuse_mhartid\[6\]      
+fuse_mhartid\[5\]      
+fuse_mhartid\[4\]      
+fuse_mhartid\[3\]      
+fuse_mhartid\[2\]      
+fuse_mhartid\[1\]      
+fuse_mhartid\[0\]      
+
diff --git a/openlane/sdram/config.tcl b/openlane/sdram/config.tcl
index b35501d..230d1e6 100755
--- a/openlane/sdram/config.tcl
+++ b/openlane/sdram/config.tcl
@@ -39,6 +39,7 @@
          $script_dir/../../verilog/rtl/sdram_ctrl/src/top/sdrc_top.v \
          $script_dir/../../verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v \
          $script_dir/../../verilog/rtl/lib/async_fifo.sv  \
+         $script_dir/../../verilog/rtl/lib/wb_stagging.sv \
          $script_dir/../../verilog/rtl/sdram_ctrl/src/core/sdrc_core.v \
          $script_dir/../../verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v \
          $script_dir/../../verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v \
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index c23dcc5..ad5d9bb 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl
@@ -101,3 +101,5 @@
 set ::env(GLB_RT_MAXLAYER) 5
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 
+#set ::env(LVS_CONNECT_BY_LABEL) 1
+
diff --git a/openlane/syntacore/pin_order.cfg b/openlane/syntacore/pin_order.cfg
index 5f52899..fb94b98 100644
--- a/openlane/syntacore/pin_order.cfg
+++ b/openlane/syntacore/pin_order.cfg
@@ -3,272 +3,272 @@
 #MANUAL_PLACE
 #E
 core_clk            0000 0
-rtc_clk             0000 1
-cpu_rst_n           0000 2
-irq_lines\[15\]     0000 3
-irq_lines\[14\]     0000 4
-irq_lines\[13\]     0000 5
-irq_lines\[12\]     0000 6
-irq_lines\[11\]     0000 7
-irq_lines\[10\]     0000 8
-irq_lines\[9\]     0000 9
-irq_lines\[8\]     0000 10
-irq_lines\[7\]     0000 11
-irq_lines\[6\]     0000 12
-irq_lines\[5\]     0000 13
-irq_lines\[4\]     0000 14
-irq_lines\[3\]     0000 15
-irq_lines\[2\]     0000 16
-irq_lines\[1\]     0000 17
-irq_lines\[0\]     0000 18
-soft_irq           0000 19
-fuse_mhartid\[31\] 0000 20
-fuse_mhartid\[30\] 0000 21
-fuse_mhartid\[29\] 0000 22
-fuse_mhartid\[28\] 0000 23
-fuse_mhartid\[27\] 0000 24
-fuse_mhartid\[26\] 0000 25
-fuse_mhartid\[25\] 0000 26
-fuse_mhartid\[24\] 0000 27
-fuse_mhartid\[23\] 0000 28
-fuse_mhartid\[22\] 0000 29
-fuse_mhartid\[21\] 0000 30
-fuse_mhartid\[20\] 0000 31
-fuse_mhartid\[19\] 0000 32
-fuse_mhartid\[18\] 0000 33
-fuse_mhartid\[17\] 0000 34
-fuse_mhartid\[16\] 0000 35
-fuse_mhartid\[15\] 0000 36
-fuse_mhartid\[14\] 0000 37
-fuse_mhartid\[13\] 0000 38
-fuse_mhartid\[12\] 0000 39
-fuse_mhartid\[11\] 0000 40
-fuse_mhartid\[10\] 0000 41
-fuse_mhartid\[9\] 0000 42
-fuse_mhartid\[8\] 0000 43
-fuse_mhartid\[7\] 0000 44
-fuse_mhartid\[6\] 0000 45
-fuse_mhartid\[5\] 0000 46
-fuse_mhartid\[4\] 0000 47
-fuse_mhartid\[3\] 0000 48
-fuse_mhartid\[2\] 0000 49
-fuse_mhartid\[1\] 0000 50
-fuse_mhartid\[0\] 0000 51
+rtc_clk             
+cpu_rst_n           
 
 #W
 wb_clk            0000 0
-wb_rst_n          0000 1
-pwrup_rst_n       0000 2
-rst_n             0000 3
+wb_rst_n          
+pwrup_rst_n       
+rst_n             
 
 #N
-wbd_imem_stb_o    0000 0
-wbd_imem_we_o     0000 1
-wbd_imem_adr_o\[31\]    0000 2
-wbd_imem_adr_o\[30\]    0000 3
-wbd_imem_adr_o\[29\]    0000 4
-wbd_imem_adr_o\[28\]    0000 5
-wbd_imem_adr_o\[27\]    0000 6
-wbd_imem_adr_o\[26\]    0000 7
-wbd_imem_adr_o\[25\]    0000 8
-wbd_imem_adr_o\[24\]    0000 9
-wbd_imem_adr_o\[23\]    0000 10
-wbd_imem_adr_o\[22\]    0000 11
-wbd_imem_adr_o\[21\]    0000 12
-wbd_imem_adr_o\[20\]    0000 13
-wbd_imem_adr_o\[19\]    0000 14
-wbd_imem_adr_o\[18\]    0000 15
-wbd_imem_adr_o\[17\]    0000 16
-wbd_imem_adr_o\[16\]    0000 17
-wbd_imem_adr_o\[15\]    0000 18
-wbd_imem_adr_o\[14\]    0000 19
-wbd_imem_adr_o\[13\]    0000 20
-wbd_imem_adr_o\[12\]    0000 21
-wbd_imem_adr_o\[11\]    0000 22
-wbd_imem_adr_o\[10\]    0000 23
-wbd_imem_adr_o\[9\]    0000 24
-wbd_imem_adr_o\[8\]    0000 25
-wbd_imem_adr_o\[7\]    0000 26
-wbd_imem_adr_o\[6\]    0000 27
-wbd_imem_adr_o\[5\]    0000 28
-wbd_imem_adr_o\[4\]    0000 29
-wbd_imem_adr_o\[3\]    0000 30
-wbd_imem_adr_o\[2\]    0000 31
-wbd_imem_adr_o\[1\]    0000 32
-wbd_imem_adr_o\[0\]    0000 33
-wbd_imem_sel_o\[3\]    0000 34
-wbd_imem_sel_o\[2\]    0000 35
-wbd_imem_sel_o\[1\]    0000 36
-wbd_imem_sel_o\[0\]    0000 37
-wbd_imem_dat_o\[31\]   0000 38
-wbd_imem_dat_o\[30\]   0000 39
-wbd_imem_dat_o\[29\]   0000 40
-wbd_imem_dat_o\[28\]   0000 41
-wbd_imem_dat_o\[27\]   0000 42
-wbd_imem_dat_o\[26\]   0000 43
-wbd_imem_dat_o\[25\]   0000 44
-wbd_imem_dat_o\[24\]   0000 45
-wbd_imem_dat_o\[23\]   0000 46
-wbd_imem_dat_o\[22\]   0000 47
-wbd_imem_dat_o\[21\]   0000 48
-wbd_imem_dat_o\[20\]   0000 49
-wbd_imem_dat_o\[19\]   0000 50
-wbd_imem_dat_o\[18\]   0000 51
-wbd_imem_dat_o\[17\]   0000 52
-wbd_imem_dat_o\[16\]   0000 53
-wbd_imem_dat_o\[15\]   0000 54
-wbd_imem_dat_o\[14\]   0000 55
-wbd_imem_dat_o\[13\]   0000 56
-wbd_imem_dat_o\[12\]   0000 57
-wbd_imem_dat_o\[11\]   0000 58
-wbd_imem_dat_o\[10\]   0000 59
-wbd_imem_dat_o\[9\]   0000 60
-wbd_imem_dat_o\[8\]   0000 61
-wbd_imem_dat_o\[7\]   0000 62
-wbd_imem_dat_o\[6\]   0000 63
-wbd_imem_dat_o\[5\]   0000 64
-wbd_imem_dat_o\[4\]   0000 65
-wbd_imem_dat_o\[3\]   0000 66
-wbd_imem_dat_o\[2\]   0000 67
-wbd_imem_dat_o\[1\]   0000 68
-wbd_imem_dat_o\[0\]   0000 69
-wbd_imem_dat_i\[31\]  0000 70
-wbd_imem_dat_i\[30\]  0000 71
-wbd_imem_dat_i\[29\]  0000 72
-wbd_imem_dat_i\[28\]  0000 73
-wbd_imem_dat_i\[27\]  0000 74
-wbd_imem_dat_i\[26\]  0000 75
-wbd_imem_dat_i\[25\]  0000 76
-wbd_imem_dat_i\[24\]  0000 77
-wbd_imem_dat_i\[23\]  0000 78
-wbd_imem_dat_i\[22\]  0000 79
-wbd_imem_dat_i\[21\]  0000 80
-wbd_imem_dat_i\[20\]  0000 81
-wbd_imem_dat_i\[19\]  0000 82
-wbd_imem_dat_i\[18\]  0000 83
-wbd_imem_dat_i\[17\]  0000 84
-wbd_imem_dat_i\[16\]  0000 85
-wbd_imem_dat_i\[15\]  0000 86
-wbd_imem_dat_i\[14\]  0000 87
-wbd_imem_dat_i\[13\]  0000 88
-wbd_imem_dat_i\[12\]  0000 89
-wbd_imem_dat_i\[11\]  0000 90
-wbd_imem_dat_i\[10\]  0000 91
-wbd_imem_dat_i\[9\]  0000 92
-wbd_imem_dat_i\[8\]  0000 93
-wbd_imem_dat_i\[7\]  0000 94
-wbd_imem_dat_i\[6\]  0000 95
-wbd_imem_dat_i\[5\]  0000 96
-wbd_imem_dat_i\[4\]  0000 97
-wbd_imem_dat_i\[3\]  0000 98
-wbd_imem_dat_i\[2\]  0000 99
-wbd_imem_dat_i\[1\]  0000 100
-wbd_imem_dat_i\[0\]  0000 101
-wbd_imem_ack_i       0000 102
-wbd_imem_err_i       0000 103
+wbd_imem_stb_o          0000 0
+wbd_imem_we_o           
+wbd_imem_adr_o\[31\]    
+wbd_imem_adr_o\[30\]    
+wbd_imem_adr_o\[29\]    
+wbd_imem_adr_o\[28\]    
+wbd_imem_adr_o\[27\]    
+wbd_imem_adr_o\[26\]    
+wbd_imem_adr_o\[25\]    
+wbd_imem_adr_o\[24\]    
+wbd_imem_adr_o\[23\]    
+wbd_imem_adr_o\[22\]    
+wbd_imem_adr_o\[21\]    
+wbd_imem_adr_o\[20\]    
+wbd_imem_adr_o\[19\]    
+wbd_imem_adr_o\[18\]    
+wbd_imem_adr_o\[17\]    
+wbd_imem_adr_o\[16\]    
+wbd_imem_adr_o\[15\]    
+wbd_imem_adr_o\[14\]    
+wbd_imem_adr_o\[13\]    
+wbd_imem_adr_o\[12\]    
+wbd_imem_adr_o\[11\]    
+wbd_imem_adr_o\[10\]   
+wbd_imem_adr_o\[9\]    
+wbd_imem_adr_o\[8\]    
+wbd_imem_adr_o\[7\]    
+wbd_imem_adr_o\[6\]    
+wbd_imem_adr_o\[5\]    
+wbd_imem_adr_o\[4\]    
+wbd_imem_adr_o\[3\]    
+wbd_imem_adr_o\[2\]    
+wbd_imem_adr_o\[1\]    
+wbd_imem_adr_o\[0\]    
+wbd_imem_sel_o\[3\]    
+wbd_imem_sel_o\[2\]    
+wbd_imem_sel_o\[1\]    
+wbd_imem_sel_o\[0\]    
+wbd_imem_dat_o\[31\]   
+wbd_imem_dat_o\[30\]   
+wbd_imem_dat_o\[29\]   
+wbd_imem_dat_o\[28\]   
+wbd_imem_dat_o\[27\]   
+wbd_imem_dat_o\[26\]   
+wbd_imem_dat_o\[25\]   
+wbd_imem_dat_o\[24\]   
+wbd_imem_dat_o\[23\]   
+wbd_imem_dat_o\[22\]   
+wbd_imem_dat_o\[21\]   
+wbd_imem_dat_o\[20\]   
+wbd_imem_dat_o\[19\]   
+wbd_imem_dat_o\[18\]   
+wbd_imem_dat_o\[17\]   
+wbd_imem_dat_o\[16\]   
+wbd_imem_dat_o\[15\]   
+wbd_imem_dat_o\[14\]   
+wbd_imem_dat_o\[13\]   
+wbd_imem_dat_o\[12\]  
+wbd_imem_dat_o\[11\]  
+wbd_imem_dat_o\[10\]  
+wbd_imem_dat_o\[9\]   
+wbd_imem_dat_o\[8\]   
+wbd_imem_dat_o\[7\]   
+wbd_imem_dat_o\[6\]   
+wbd_imem_dat_o\[5\]   
+wbd_imem_dat_o\[4\]   
+wbd_imem_dat_o\[3\]   
+wbd_imem_dat_o\[2\]   
+wbd_imem_dat_o\[1\]   
+wbd_imem_dat_o\[0\]   
+wbd_imem_dat_i\[31\]  
+wbd_imem_dat_i\[30\]  
+wbd_imem_dat_i\[29\]  
+wbd_imem_dat_i\[28\]  
+wbd_imem_dat_i\[27\]  
+wbd_imem_dat_i\[26\]  
+wbd_imem_dat_i\[25\]  
+wbd_imem_dat_i\[24\]  
+wbd_imem_dat_i\[23\]  
+wbd_imem_dat_i\[22\]  
+wbd_imem_dat_i\[21\]  
+wbd_imem_dat_i\[20\]  
+wbd_imem_dat_i\[19\]  
+wbd_imem_dat_i\[18\]  
+wbd_imem_dat_i\[17\]  
+wbd_imem_dat_i\[16\]  
+wbd_imem_dat_i\[15\]  
+wbd_imem_dat_i\[14\]  
+wbd_imem_dat_i\[13\]  
+wbd_imem_dat_i\[12\]  
+wbd_imem_dat_i\[11\]  
+wbd_imem_dat_i\[10\]  
+wbd_imem_dat_i\[9\]  
+wbd_imem_dat_i\[8\]  
+wbd_imem_dat_i\[7\]  
+wbd_imem_dat_i\[6\]  
+wbd_imem_dat_i\[5\]  
+wbd_imem_dat_i\[4\]  
+wbd_imem_dat_i\[3\]  
+wbd_imem_dat_i\[2\]  
+wbd_imem_dat_i\[1\]  
+wbd_imem_dat_i\[0\]  
+wbd_imem_ack_i       
+wbd_imem_err_i       
 
-wbd_dmem_stb_o       0500 0
-wbd_dmem_we_o        0500 1
-wbd_dmem_adr_o\[31\] 0500 2
-wbd_dmem_adr_o\[30\] 0500 3
-wbd_dmem_adr_o\[29\] 0500 4
-wbd_dmem_adr_o\[28\] 0500 5
-wbd_dmem_adr_o\[27\] 0500 6
-wbd_dmem_adr_o\[26\] 0500 7
-wbd_dmem_adr_o\[25\] 0500 8
-wbd_dmem_adr_o\[24\] 0500 9
-wbd_dmem_adr_o\[23\] 0500 10
-wbd_dmem_adr_o\[22\] 0500 11
-wbd_dmem_adr_o\[21\] 0500 12
-wbd_dmem_adr_o\[20\] 0500 13
-wbd_dmem_adr_o\[19\] 0500 14
-wbd_dmem_adr_o\[18\] 0500 15
-wbd_dmem_adr_o\[17\] 0500 16
-wbd_dmem_adr_o\[16\] 0500 17
-wbd_dmem_adr_o\[15\] 0500 18
-wbd_dmem_adr_o\[14\] 0500 19
-wbd_dmem_adr_o\[13\] 0500 20
-wbd_dmem_adr_o\[12\] 0500 21
-wbd_dmem_adr_o\[11\] 0500 22
-wbd_dmem_adr_o\[10\] 0500 23
-wbd_dmem_adr_o\[9\] 0500 24
-wbd_dmem_adr_o\[8\] 0500 25
-wbd_dmem_adr_o\[7\] 0500 26
-wbd_dmem_adr_o\[6\] 0500 27
-wbd_dmem_adr_o\[5\] 0500 28
-wbd_dmem_adr_o\[4\] 0500 29
-wbd_dmem_adr_o\[3\] 0500 30
-wbd_dmem_adr_o\[2\] 0500 31
-wbd_dmem_adr_o\[1\] 0500 32
-wbd_dmem_adr_o\[0\] 0500 33
-wbd_dmem_sel_o\[3\]  0500 34
-wbd_dmem_sel_o\[2\]  0500 35
-wbd_dmem_sel_o\[1\]  0500 36
-wbd_dmem_sel_o\[0\]  0500 37
-wbd_dmem_dat_o\[31\] 0500 38
-wbd_dmem_dat_o\[30\] 0500 39
-wbd_dmem_dat_o\[29\] 0500 40
-wbd_dmem_dat_o\[28\] 0500 41
-wbd_dmem_dat_o\[27\] 0500 42
-wbd_dmem_dat_o\[26\] 0500 43
-wbd_dmem_dat_o\[25\] 0500 44
-wbd_dmem_dat_o\[24\] 0500 45
-wbd_dmem_dat_o\[23\] 0500 46
-wbd_dmem_dat_o\[22\] 0500 47
-wbd_dmem_dat_o\[21\] 0500 48
-wbd_dmem_dat_o\[20\] 0500 49
-wbd_dmem_dat_o\[19\] 0500 50
-wbd_dmem_dat_o\[18\] 0500 51
-wbd_dmem_dat_o\[17\] 0500 52
-wbd_dmem_dat_o\[16\] 0500 53
-wbd_dmem_dat_o\[15\] 0500 54
-wbd_dmem_dat_o\[14\] 0500 55
-wbd_dmem_dat_o\[13\] 0500 56
-wbd_dmem_dat_o\[12\] 0500 57
-wbd_dmem_dat_o\[11\] 0500 58
-wbd_dmem_dat_o\[10\] 0500 59
-wbd_dmem_dat_o\[9\] 0500 60
-wbd_dmem_dat_o\[8\] 0500 61
-wbd_dmem_dat_o\[7\] 0500 62
-wbd_dmem_dat_o\[6\] 0500 63
-wbd_dmem_dat_o\[5\] 0500 64
-wbd_dmem_dat_o\[4\] 0500 65
-wbd_dmem_dat_o\[3\] 0500 66
-wbd_dmem_dat_o\[2\] 0500 67
-wbd_dmem_dat_o\[1\] 0500 68
-wbd_dmem_dat_o\[0\] 0500 69
-wbd_dmem_dat_i\[31\] 0500 70
-wbd_dmem_dat_i\[30\] 0500 71
-wbd_dmem_dat_i\[29\] 0500 72
-wbd_dmem_dat_i\[28\] 0500 73
-wbd_dmem_dat_i\[27\] 0500 74
-wbd_dmem_dat_i\[26\] 0500 75
-wbd_dmem_dat_i\[25\] 0500 76
-wbd_dmem_dat_i\[24\] 0500 77
-wbd_dmem_dat_i\[23\] 0500 78
-wbd_dmem_dat_i\[22\] 0500 79
-wbd_dmem_dat_i\[21\] 0500 80
-wbd_dmem_dat_i\[20\] 0500 81
-wbd_dmem_dat_i\[19\] 0500 82
-wbd_dmem_dat_i\[18\] 0500 83
-wbd_dmem_dat_i\[17\] 0500 84
-wbd_dmem_dat_i\[16\] 0500 85
-wbd_dmem_dat_i\[15\] 0500 86
-wbd_dmem_dat_i\[14\] 0500 87
-wbd_dmem_dat_i\[13\] 0500 88
-wbd_dmem_dat_i\[12\] 0500 89
-wbd_dmem_dat_i\[11\] 0500 90
-wbd_dmem_dat_i\[10\] 0500 91
-wbd_dmem_dat_i\[9\] 0500 92
-wbd_dmem_dat_i\[8\] 0500 93
-wbd_dmem_dat_i\[7\] 0500 94
-wbd_dmem_dat_i\[6\] 0500 95
-wbd_dmem_dat_i\[5\] 0500 96
-wbd_dmem_dat_i\[4\] 0500 97
-wbd_dmem_dat_i\[3\] 0500 98
-wbd_dmem_dat_i\[2\] 0500 99
-wbd_dmem_dat_i\[1\] 0500 100
-wbd_dmem_dat_i\[0\] 0500 101
-wbd_dmem_ack_i      0500 102
-wbd_dmem_err_i      0500 103
+wbd_dmem_stb_o       0500 0  2
+wbd_dmem_we_o        
+wbd_dmem_adr_o\[31\] 
+wbd_dmem_adr_o\[30\] 
+wbd_dmem_adr_o\[29\] 
+wbd_dmem_adr_o\[28\] 
+wbd_dmem_adr_o\[27\] 
+wbd_dmem_adr_o\[26\] 
+wbd_dmem_adr_o\[25\] 
+wbd_dmem_adr_o\[24\] 
+wbd_dmem_adr_o\[23\] 
+wbd_dmem_adr_o\[22\] 
+wbd_dmem_adr_o\[21\] 
+wbd_dmem_adr_o\[20\] 
+wbd_dmem_adr_o\[19\] 
+wbd_dmem_adr_o\[18\] 
+wbd_dmem_adr_o\[17\] 
+wbd_dmem_adr_o\[16\] 
+wbd_dmem_adr_o\[15\] 
+wbd_dmem_adr_o\[14\] 
+wbd_dmem_adr_o\[13\] 
+wbd_dmem_adr_o\[12\] 
+wbd_dmem_adr_o\[11\] 
+wbd_dmem_adr_o\[10\] 
+wbd_dmem_adr_o\[9\] 
+wbd_dmem_adr_o\[8\] 
+wbd_dmem_adr_o\[7\] 
+wbd_dmem_adr_o\[6\] 
+wbd_dmem_adr_o\[5\] 
+wbd_dmem_adr_o\[4\] 
+wbd_dmem_adr_o\[3\] 
+wbd_dmem_adr_o\[2\] 
+wbd_dmem_adr_o\[1\] 
+wbd_dmem_adr_o\[0\] 
+wbd_dmem_sel_o\[3\]  
+wbd_dmem_sel_o\[2\]  
+wbd_dmem_sel_o\[1\]  
+wbd_dmem_sel_o\[0\]  
+wbd_dmem_dat_o\[31\] 
+wbd_dmem_dat_o\[30\] 
+wbd_dmem_dat_o\[29\] 
+wbd_dmem_dat_o\[28\] 
+wbd_dmem_dat_o\[27\] 
+wbd_dmem_dat_o\[26\] 
+wbd_dmem_dat_o\[25\] 
+wbd_dmem_dat_o\[24\] 
+wbd_dmem_dat_o\[23\] 
+wbd_dmem_dat_o\[22\] 
+wbd_dmem_dat_o\[21\] 
+wbd_dmem_dat_o\[20\] 
+wbd_dmem_dat_o\[19\] 
+wbd_dmem_dat_o\[18\] 
+wbd_dmem_dat_o\[17\] 
+wbd_dmem_dat_o\[16\] 
+wbd_dmem_dat_o\[15\] 
+wbd_dmem_dat_o\[14\] 
+wbd_dmem_dat_o\[13\] 
+wbd_dmem_dat_o\[12\] 
+wbd_dmem_dat_o\[11\] 
+wbd_dmem_dat_o\[10\] 
+wbd_dmem_dat_o\[9\]  
+wbd_dmem_dat_o\[8\]  
+wbd_dmem_dat_o\[7\]  
+wbd_dmem_dat_o\[6\]  
+wbd_dmem_dat_o\[5\]  
+wbd_dmem_dat_o\[4\]  
+wbd_dmem_dat_o\[3\]  
+wbd_dmem_dat_o\[2\]  
+wbd_dmem_dat_o\[1\]  
+wbd_dmem_dat_o\[0\]  
+wbd_dmem_dat_i\[31\] 
+wbd_dmem_dat_i\[30\] 
+wbd_dmem_dat_i\[29\] 
+wbd_dmem_dat_i\[28\] 
+wbd_dmem_dat_i\[27\] 
+wbd_dmem_dat_i\[26\] 
+wbd_dmem_dat_i\[25\] 
+wbd_dmem_dat_i\[24\] 
+wbd_dmem_dat_i\[23\] 
+wbd_dmem_dat_i\[22\] 
+wbd_dmem_dat_i\[21\] 
+wbd_dmem_dat_i\[20\] 
+wbd_dmem_dat_i\[19\] 
+wbd_dmem_dat_i\[18\] 
+wbd_dmem_dat_i\[17\] 
+wbd_dmem_dat_i\[16\] 
+wbd_dmem_dat_i\[15\] 
+wbd_dmem_dat_i\[14\] 
+wbd_dmem_dat_i\[13\] 
+wbd_dmem_dat_i\[12\] 
+wbd_dmem_dat_i\[11\] 
+wbd_dmem_dat_i\[10\] 
+wbd_dmem_dat_i\[9\] 
+wbd_dmem_dat_i\[8\] 
+wbd_dmem_dat_i\[7\] 
+wbd_dmem_dat_i\[6\] 
+wbd_dmem_dat_i\[5\] 
+wbd_dmem_dat_i\[4\] 
+wbd_dmem_dat_i\[3\] 
+wbd_dmem_dat_i\[2\] 
+wbd_dmem_dat_i\[1\] 
+wbd_dmem_dat_i\[0\] 
+wbd_dmem_ack_i      
+wbd_dmem_err_i      
 
+irq_lines\[15\]     1200 0  2
+irq_lines\[14\]     
+irq_lines\[13\]     
+irq_lines\[12\]     
+irq_lines\[11\]     
+irq_lines\[10\]     
+irq_lines\[9\]     
+irq_lines\[8\]     
+irq_lines\[7\]     
+irq_lines\[6\]     
+irq_lines\[5\]     
+irq_lines\[4\]     
+irq_lines\[3\]     
+irq_lines\[2\]     
+irq_lines\[1\]     
+irq_lines\[0\]     
+soft_irq           
+fuse_mhartid\[31\] 
+fuse_mhartid\[30\] 
+fuse_mhartid\[29\] 
+fuse_mhartid\[28\] 
+fuse_mhartid\[27\] 
+fuse_mhartid\[26\] 
+fuse_mhartid\[25\] 
+fuse_mhartid\[24\] 
+fuse_mhartid\[23\] 
+fuse_mhartid\[22\] 
+fuse_mhartid\[21\] 
+fuse_mhartid\[20\] 
+fuse_mhartid\[19\] 
+fuse_mhartid\[18\] 
+fuse_mhartid\[17\] 
+fuse_mhartid\[16\] 
+fuse_mhartid\[15\] 
+fuse_mhartid\[14\] 
+fuse_mhartid\[13\] 
+fuse_mhartid\[12\] 
+fuse_mhartid\[11\] 
+fuse_mhartid\[10\] 
+fuse_mhartid\[9\] 
+fuse_mhartid\[8\] 
+fuse_mhartid\[7\] 
+fuse_mhartid\[6\] 
+fuse_mhartid\[5\] 
+fuse_mhartid\[4\] 
+fuse_mhartid\[3\] 
+fuse_mhartid\[2\] 
+fuse_mhartid\[1\] 
+fuse_mhartid\[0\] 
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 7661525..51dc0f8 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -60,6 +60,7 @@
         $script_dir/../../verilog/gl/uart.v     \
 	$script_dir/../../verilog/gl/sdram.v \
 	$script_dir/../../verilog/gl/wb_host.v \
+	$script_dir/../../verilog/gl/clk_skew_adjust.v \
 	$script_dir/../../verilog/gl/syntacore.v \
 	"
 
@@ -70,6 +71,7 @@
 	$lef_root/sdram.lef \
 	$lef_root/uart.lef \
 	$lef_root/wb_host.lef \
+	$lef_root/clk_skew_adjust.lef \
 	$lef_root/syntacore.lef \
 	"
 
@@ -80,6 +82,7 @@
 	$gds_root/uart.gds \
 	$gds_root/sdram.gds \
 	$gds_root/wb_host.gds \
+	$gds_root/clk_skew_adjust.gds \
 	$gds_root/syntacore.gds \
 	"
 
@@ -87,7 +90,7 @@
 
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
 
-set ::env(GLB_RT_MAXLAYER) 6
+set ::env(GLB_RT_MAXLAYER) 5
 
 set ::env(FP_PDN_CHECK_NODES) 0
 
@@ -111,6 +114,9 @@
 set ::env(TAP_DECAP_INSERTION) 0
 set ::env(CLOCK_TREE_SYNTH) 0
 
+set ::env(MAGIC_EXT_USE_GDS) "1"
+
+
 set ::env(PL_DIAMOND_SEARCH_HEIGHT) "250"
 
 
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 9ef1988..2843978 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -5,3 +5,13 @@
 u_core.u_uart_core             2200            1600            N
 u_core.u_intercon              300             2300            N
 u_core.u_wb_host               300             300             N
+u_core.u_skew_wi               2600            2300            N
+u_core.u_skew_riscv            400             800             N
+u_core.u_skew_uart             2200            1500            N
+u_core.u_skew_spi              200             2700            E
+u_core.u_skew_sdram            900             2700            E
+u_core.u_skew_glbl             2000            3200            N
+u_core.u_skew_wh               1400            300             N
+u_core.u_skew_sd_co            950             3300            N
+u_core.u_skew_sd_ci            1100            3300            N
+u_core.u_skew_sp_co            300             3400            N
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 56efc5b..1c7005b 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -37,8 +37,9 @@
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
      $script_dir/../../verilog/rtl/wb_host/src/wb_host.sv \
-     $script_dir/../../verilog/rtl/lib/async_fifo.sv \
-     $script_dir/../../verilog/rtl/lib/async_wb.sv \
+     $script_dir/../../verilog/rtl/lib/async_fifo.sv      \
+     $script_dir/../../verilog/rtl/lib/async_wb.sv        \
+     $script_dir/../../verilog/rtl/lib/clk_ctl.v          \
      $script_dir/../../verilog/rtl/lib/registers.v"
 
 #set ::env(SDC_FILE) "$script_dir/base.sdc"
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index ed2fa74..635b188 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -63,7 +63,7 @@
 ifeq ($(SIM),RTL)
 	iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH)  \
 	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
 	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
 	$< -o $@ 
diff --git a/verilog/dv/user_risc_boot/run_iverilog b/verilog/dv/user_risc_boot/run_iverilog
index 63083a1..f083d6d 100755
--- a/verilog/dv/user_risc_boot/run_iverilog
+++ b/verilog/dv/user_risc_boot/run_iverilog
@@ -29,9 +29,13 @@
 rm crt_tcm.o user_risc_boot.o
 
 #iverilog with waveform dump
-#iverilog -g2005-sv -DWFDUMP -I $PDK_PATH -I ../ -I ../../../verilog/rtl -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model user_risc_boot_tb.v -o user_risc_boot_tb.vvp
+iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH -I  ../../../caravel/verilog/rtl  -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_risc_boot_tb.v -o user_risc_boot_tb.vvp
 
-iverilog -g2005-sv -I $PDK_PATH -I ../ -I ../../../verilog/rtl -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model user_risc_boot_tb.v -o user_risc_boot_tb.vvp
+
+#iverilog -g2005-sv -I $PDK_PATH -DFUNCTIONAL -DSIM -I  ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_risc_boot_tb.v -o user_risc_boot_tb.vvp
+
+# GLS
+#iverilog -g2005-sv -DGL -I $PDK_PATH -I  ../../../caravel/verilog/rtl  -I ../ -I ../../../verilog/rtl -I ../../../verilog -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_risc_boot_tb.vvp
 
 vvp user_risc_boot_tb.vvp | tee test.log
 
diff --git a/verilog/dv/user_risc_boot/uprj_netlists.v b/verilog/dv/user_risc_boot/uprj_netlists.v
index 1668caa..24c1d6d 100644
--- a/verilog/dv/user_risc_boot/uprj_netlists.v
+++ b/verilog/dv/user_risc_boot/uprj_netlists.v
@@ -16,14 +16,17 @@
 // Include caravel global defines for the number of the user project IO pads 
 `include "defines.v"
 `define USE_POWER_PINS
+`define UNIT_DELAY #1
 
 `ifdef GL
-      `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
-      `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
-      `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
-      `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
 
-      `include "digital_core/src/digital_core.sv"
+       `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+       `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+       `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+       `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+
+
       `include "glbl_cfg.v"
       `include "sdram.v"
       `include "spi_master.v"
@@ -66,6 +69,11 @@
      `include "lib/sync_fifo.sv"
      `include "lib/async_fifo.sv"  
 `else
+     `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+     `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+     `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+     `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
      `include "spi_master/src/spim_top.sv"
      `include "spi_master/src/spim_regs.sv"
      `include "spi_master/src/spim_clkgen.sv"
@@ -136,4 +144,7 @@
      `include "lib/sync_fifo.sv"
 
      `include "user_project_wrapper.v"
+     // we are using netlist file for clk_skew_adjust as it has 
+     // standard cell + power pin
+     `include "gl/clk_skew_adjust.v"
 `endif
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index 45b15cc..c05ec68 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -63,7 +63,7 @@
 ifeq ($(SIM),RTL)
 	iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
 	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
 	$< -o $@ 
diff --git a/verilog/dv/user_uart/run_iverilog b/verilog/dv/user_uart/run_iverilog
index 00d1d51..6cac66f 100755
--- a/verilog/dv/user_uart/run_iverilog
+++ b/verilog/dv/user_uart/run_iverilog
@@ -28,13 +28,13 @@
 rm crt_tcm.o user_uart.o
 
 #iverilog with waveform dump
-iverilog -g2005-sv -DWFDUMP -I $PDK_PATH -I  ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
+iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH -I  ../../../caravel/verilog/rtl  -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
 
 
-#iverilog -g2005-sv -I $PDK_PATH -I  ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
+#iverilog -g2005-sv -I $PDK_PATH -DFUNCTIONAL -DSIM -I  ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
 
 # GLS
-#iverilog -g2005-sv -DGL -I $PDK_PATH -I  ../../../caravel/verilog/rtl -I ../../gl -I ../ -I ../../../verilog/rtl -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
+#iverilog -g2005-sv -DGL -I $PDK_PATH -I  ../../../caravel/verilog/rtl  -I ../ -I ../../../verilog/rtl -I ../../../verilog -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes   -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp
 
 vvp user_uart_tb.vvp | tee test.log
 
diff --git a/verilog/dv/user_uart/uprj_netlists.v b/verilog/dv/user_uart/uprj_netlists.v
index 5e42730..d140c85 100644
--- a/verilog/dv/user_uart/uprj_netlists.v
+++ b/verilog/dv/user_uart/uprj_netlists.v
@@ -16,12 +16,16 @@
 // Include caravel global defines for the number of the user project IO pads 
 `include "defines.v"
 `define USE_POWER_PINS
+`define UNIT_DELAY #1
 
 `ifdef GL
-      `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
-      `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
-      `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
-      `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+       `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+       `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+       `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+       `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+
 
       `include "glbl_cfg.v"
       `include "sdram.v"
@@ -34,6 +38,13 @@
      `include "wb_host.v"
 
 `else
+
+     `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+     `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+     `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+     `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+
      `include "spi_master/src/spim_top.sv"
      `include "spi_master/src/spim_regs.sv"
      `include "spi_master/src/spim_clkgen.sv"
@@ -104,4 +115,7 @@
      `include "lib/sync_fifo.sv"
 
      `include "user_project_wrapper.v"
+     // we are using netlist file for clk_skew_adjust as it has 
+     // standard cell + power pin
+     `include "gl/clk_skew_adjust.v"
 `endif
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 3dcc653..cfe4819 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -150,9 +150,6 @@
 	   initial begin
 	   	$dumpfile("risc_boot.vcd");
 	   	$dumpvars(4, user_uart_tb);
-
-		#1000;
-		$finish;
 	   end
        `endif
 
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index f1565bb..19c32ee 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -51,7 +51,7 @@
 ifeq ($(SIM),RTL)
 	iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
 	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
 	$< -o $@ 
 else  
diff --git a/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv b/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv
new file mode 100644
index 0000000..038ef52
--- /dev/null
+++ b/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv
@@ -0,0 +1,194 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  clock skew adjust                                          ////
+////                                                              ////
+////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/yifive_r0.git              ////
+////  http://www.opencores.org/cores/yifive/                      ////
+////                                                              ////
+////  Description                                                 ////
+////      This block is useful for global clock skew adjustment   ////
+////      logic implementation:                                   ////
+////        clk_out = (sel=0) ? clk_in :                          ////
+////                  (sel=1) ? clk_d1 :                          ////
+////                  (sel=1) ? clk_d2 :                          ////
+////                  .....                                       ////
+////                  (sel=15)? clk_d15 :clk_in                   ////
+////                                                              ////
+////     Note: each d* indicate clk buf delay                     ////
+////                                                              ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.0 - 29th Feb 2021, Dinesh A                             ////
+////          Initial version                                     ////
+///
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+// Clock-in is east pad direction
+// clock out give in other three direction for better placement
+/////////////////////////////////////////////////////////////////////
+module clk_skew_adjust(clk_in, sel, clk_out);
+  input  clk_in;
+  output clk_out;
+  input [3:0] sel;
+  wire in0;
+  wire in1;
+  wire in2;
+  wire in3;
+  wire in4;
+  wire in5;
+  wire in6;
+  wire in7;
+  wire in8;
+  wire in9;
+  wire in10;
+  wire in11;
+  wire in12;
+  wire in13;
+  wire in14;
+  wire in15;
+
+  wire clk_d1;
+  wire clk_d2;
+  wire clk_d3;
+  wire clk_d4;
+  wire clk_d5;
+  wire clk_d6;
+  wire clk_d7;
+  wire clk_d8;
+  wire clk_d9;
+  wire clk_d10;
+  wire clk_d11;
+  wire clk_d12;
+  wire clk_d13;
+  wire clk_d14;
+  wire clk_d15;
+
+  wire d00;
+  wire d01;
+  wire d02;
+  wire d03;
+  wire d04;
+  wire d05;
+  wire d06;
+  wire d07;
+  wire d10;
+  wire d11;
+  wire d12;
+  wire d13;
+  wire d20;
+  wire d21;
+  wire d30;
+
+
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_1  (.A(clk_in),  .X(clk_d1));
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_2  (.A(clk_d1),    .X(clk_d2));
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_3  (.A(clk_d2),    .X(clk_d3));
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_4  (.A(clk_d3),    .X(clk_d4));
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_5  (.A(clk_d4),    .X(clk_d5));
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_6  (.A(clk_d5),    .X(clk_d6));
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_7  (.A(clk_d6),    .X(clk_d7));
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_8  (.A(clk_d7),    .X(clk_d8));
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_9  (.A(clk_d8),    .X(clk_d9));
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_10 (.A(clk_d9),    .X(clk_d10));
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_11 (.A(clk_d10),   .X(clk_d11));
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_12 (.A(clk_d11),   .X(clk_d12));
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_13 (.A(clk_d12),   .X(clk_d13));
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_14 (.A(clk_d13),   .X(clk_d14));
+  sky130_fd_sc_hd__clkbuf_1 clkbuf_15 (.A(clk_d14),   .X(clk_d15));
+
+
+  // Tap point selection
+  assign in0  = clk_in;
+  assign in1  = clk_d1;
+  assign in2  = clk_d2;
+  assign in3  = clk_d3;
+  assign in4  = clk_d4;
+  assign in5  = clk_d5;
+  assign in6  = clk_d6;
+  assign in7  = clk_d7;
+  assign in8  = clk_d8;
+  assign in9  = clk_d9;
+  assign in10 = clk_d10;
+  assign in11 = clk_d11;
+  assign in12 = clk_d12;
+  assign in13 = clk_d13;
+  assign in14 = clk_d14;
+  assign in15 = clk_d15;
+
+
+  // first level mux - 8
+  sky130_fd_sc_hd__mux2_1 u_mux_level_00 ( .X (d00) , .A0 (in0),  .A1(in1),  .S(sel[0]));
+  sky130_fd_sc_hd__mux2_1 u_mux_level_01 ( .X (d01) , .A0 (in2),  .A1(in3),  .S(sel[0]));
+  sky130_fd_sc_hd__mux2_1 u_mux_level_02 ( .X (d02) , .A0 (in4),  .A1(in5),  .S(sel[0]));
+  sky130_fd_sc_hd__mux2_1 u_mux_level_03 ( .X (d03) , .A0 (in6),  .A1(in7),  .S(sel[0]));
+  sky130_fd_sc_hd__mux2_1 u_mux_level_04 ( .X (d04) , .A0 (in8),  .A1(in9),  .S(sel[0]));
+  sky130_fd_sc_hd__mux2_1 u_mux_level_05 ( .X (d05) , .A0 (in10), .A1(in11), .S(sel[0]));
+  sky130_fd_sc_hd__mux2_1 u_mux_level_06 ( .X (d06) , .A0 (in12), .A1(in13), .S(sel[0]));
+  sky130_fd_sc_hd__mux2_1 u_mux_level_07 ( .X (d07) , .A0 (in14), .A1(in15), .S(sel[0]));
+
+  // second level mux - 4
+  sky130_fd_sc_hd__mux2_1 u_mux_level_10 ( .X (d10) , .A0 (d00), .A1(d01), .S(sel[1]));
+  sky130_fd_sc_hd__mux2_1 u_mux_level_11 ( .X (d11) , .A0 (d02), .A1(d03), .S(sel[1]));
+  sky130_fd_sc_hd__mux2_1 u_mux_level_12 ( .X (d12) , .A0 (d04), .A1(d05), .S(sel[1]));
+  sky130_fd_sc_hd__mux2_1 u_mux_level_13 ( .X (d13) , .A0 (d06), .A1(d07), .S(sel[1]));
+
+  // third level mux - 2
+  sky130_fd_sc_hd__mux2_1 u_mux_level_20 ( .X (d20) , .A0 (d10), .A1(d11), .S(sel[2]));
+  sky130_fd_sc_hd__mux2_1 u_mux_level_21 ( .X (d21) , .A0 (d12), .A1(d13), .S(sel[2]));
+
+  // fourth level mux - 1
+  sky130_fd_sc_hd__mux2_1 u_mux_level_30 ( .X (d30) , .A0 (d20), .A1(d21), .S(sel[3]));
+
+
+  assign clk_out = d30;
+
+endmodule
diff --git a/verilog/rtl/clk_skew_adjust/synth/Makefile b/verilog/rtl/clk_skew_adjust/synth/Makefile
new file mode 100644
index 0000000..f6ae1df
--- /dev/null
+++ b/verilog/rtl/clk_skew_adjust/synth/Makefile
@@ -0,0 +1,49 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# // 
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# //      http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+#------------------------------------------------------------------------------
+# Makefile for Synthesis
+#------------------------------------------------------------------------------
+
+# Paths
+export ROOT_DIR := $(shell pwd)
+export REPORT_DIR  := $(ROOT_DIR)/reports
+export NETLIST_DIR  := $(ROOT_DIR)/netlist
+export TMP_DIR  := $(ROOT_DIR)/tmp
+
+
+# Targets
+.PHONY: clean create synth
+
+default: clean create synth
+
+synth: clean create 
+	yosys -g -c synth.tcl -l synth.log
+
+create:
+	mkdir -p ./tmp/synthesis; 
+	mkdir -p ./reports; 
+	mkdir -p ./netlist;
+	$(OPENLANE_ROOT)/scripts/libtrim.pl $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib $(PDK_ROOT)/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells > ./tmp/trimmed.lib
+
+
+
+clean:
+	$(RM) -R synth.log
+	$(RM) -R $(REPORT_DIR)
+	$(RM) -R $(NETLIST_DIR)
+	$(RM) -R $(TMP_DIR)
diff --git a/verilog/rtl/clk_skew_adjust/synth/synth.tcl b/verilog/rtl/clk_skew_adjust/synth/synth.tcl
new file mode 100755
index 0000000..b7adea6
--- /dev/null
+++ b/verilog/rtl/clk_skew_adjust/synth/synth.tcl
@@ -0,0 +1,385 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# // 
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# //      http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+# inputs expected as env vars
+#set opt $::env(SYNTH_OPT)
+########### config.tcl ##################
+# User config
+
+# User config
+set ::env(DESIGN_DIR) ../
+
+set ::env(PROJ_DIR) ../../../../
+
+# User config
+set ::env(DESIGN_NAME) clk_mux
+
+# Change if needed
+set ::env(VERILOG_FILES) [glob  \
+	../src/clk_mux.v  ]
+
+
+set ::env(SYNTH_DEFINES) [list YOSYS ]
+
+
+set ::env(LIB_SYNTH)  ./tmp/trimmed.lib
+
+
+# Fill this
+set ::env(CLOCK_PERIOD) "10"
+#set ::env(CLOCK_PORT) "mclk"
+set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(RUN_SIMPLE_CTS) 0
+set ::env(SYNTH_BUFFERING) 0
+set ::env(SYNTH_SIZING) 0
+
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(SYNTH_MAX_TRAN) "[expr {0.1*10.0}]"
+
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 50
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CELL_PAD) 4
+
+set ::env(SYNTH_NO_FLAT) "0"
+
+
+set ::env(SYNTH_STRATEGY) "AREA 0"
+set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hd__conb_1 LO"
+set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hd__conb_1 HI"
+set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hd__buf_2 A X"
+
+
+#set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+
+
+set ::env(yosys_tmp_file_tag) "./tmp/"
+set ::env(TMP_DIR) "./tmp/"
+set ::env(yosys_netlist_dir) "./netlist"
+set ::env(yosys_report_file_tag) "./reports/yosys"
+set ::env(yosys_result_file_tag) "./reports/yosys.synthesis"
+
+set ::env(SAVE_NETLIST) $::env(yosys_netlist_dir)/$::env(DESIGN_NAME).gv
+
+
+
+########### End of config.tcl
+set buffering $::env(SYNTH_BUFFERING)
+set sizing $::env(SYNTH_SIZING)
+
+yosys -import
+
+set vtop $::env(DESIGN_NAME)
+#set sdc_file $::env(SDC_FILE)
+set sclib $::env(LIB_SYNTH)
+
+if { [info exists ::env(SYNTH_DEFINES) ] } {
+	foreach define $::env(SYNTH_DEFINES) {
+		log "Defining $define"
+		verilog_defines -D$define
+	}
+}
+
+set vIdirsArgs ""
+if {[info exist ::env(VERILOG_INCLUDE_DIRS)]} {
+	foreach dir $::env(VERILOG_INCLUDE_DIRS) {
+		log "Adding include file -I$dir "
+		lappend vIdirsArgs "-I$dir"
+	}
+	set vIdirsArgs [join $vIdirsArgs]
+}
+
+
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+	foreach lib $::env(EXTRA_LIBS) {
+		read_liberty {*}$vIdirsArgs -lib -ignore_miss_dir -setattr blackbox $lib
+	}
+}
+
+
+
+# ns expected (in sdc as well)
+set clock_period [expr {$::env(CLOCK_PERIOD)*1000}]
+
+set driver  $::env(SYNTH_DRIVING_CELL)
+set cload   $::env(SYNTH_CAP_LOAD)
+# input pin cap of IN_3VX8
+set max_FO $::env(SYNTH_MAX_FANOUT)
+if {![info exist ::env(SYNTH_MAX_TRAN)]} {
+	set ::env(SYNTH_MAX_TRAN) [expr {0.1*$clock_period}]
+} else {
+	set ::env(SYNTH_MAX_TRAN) [expr {$::env(SYNTH_MAX_TRAN) * 1000}]
+}
+set max_Tran $::env(SYNTH_MAX_TRAN)
+
+
+# Mapping parameters
+set A_factor  0.00
+set B_factor  0.88
+set F_factor  0.00
+
+# Don't change these unless you know what you are doing
+set stat_ext    ".stat.rpt"
+set chk_ext    ".chk.rpt"
+set gl_ext      ".gl.v"
+set constr_ext  ".$clock_period.constr"
+set timing_ext  ".timing.txt"
+set abc_ext     ".abc"
+
+
+# get old sdc, add library specific stuff for abc scripts
+set sdc_file $::env(yosys_tmp_file_tag).sdc
+set outfile [open ${sdc_file} w]
+#puts $outfile $sdc_data
+puts $outfile "set_driving_cell ${driver}"
+puts $outfile "set_load ${cload}"
+close $outfile
+
+
+# ABC Scrips
+set abc_rs_K    "resub,-K,"
+set abc_rs      "resub"
+set abc_rsz     "resub,-z"
+set abc_rw_K    "rewrite,-K,"
+set abc_rw      "rewrite"
+set abc_rwz     "rewrite,-z"
+set abc_rf      "refactor"
+set abc_rfz     "refactor,-z"
+set abc_b       "balance"
+
+set abc_resyn2        "${abc_b}; ${abc_rw}; ${abc_rf}; ${abc_b}; ${abc_rw}; ${abc_rwz}; ${abc_b}; ${abc_rfz}; ${abc_rwz}; ${abc_b}"
+set abc_share         "strash; multi,-m; ${abc_resyn2}"
+set abc_resyn2a       "${abc_b};${abc_rw};${abc_b};${abc_rw};${abc_rwz};${abc_b};${abc_rwz};${abc_b}"
+set abc_resyn3        "balance;resub;resub,-K,6;balance;resub,-z;resub,-z,-K,6;balance;resub,-z,-K,5;balance"
+set abc_resyn2rs      "${abc_b};${abc_rs_K},6;${abc_rw};${abc_rs_K},6,-N,2;${abc_rf};${abc_rs_K},8;${abc_rw};${abc_rs_K},10;${abc_rwz};${abc_rs_K},10,-N,2;${abc_b},${abc_rs_K},12;${abc_rfz};${abc_rs_K},12,-N,2;${abc_rwz};${abc_b}"
+
+set abc_choice        "fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
+set abc_choice2      "fraig_store; balance; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
+
+set abc_map_old_cnt			"map,-p,-a,-B,0.2,-A,0.9,-M,0"
+set abc_map_old_dly         "map,-p,-B,0.2,-A,0.9,-M,0"
+set abc_retime_area         "retime,-D,{D},-M,5"
+set abc_retime_dly          "retime,-D,{D},-M,6"
+set abc_map_new_area        "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
+
+set abc_area_recovery_1       "${abc_choice}; map;"
+set abc_area_recovery_2       "${abc_choice2}; map;"
+
+set map_old_cnt			    "map,-p,-a,-B,0.2,-A,0.9,-M,0"
+set map_old_dly			    "map,-p,-B,0.2,-A,0.9,-M,0"
+set abc_retime_area   	"retime,-D,{D},-M,5"
+set abc_retime_dly    	"retime,-D,{D},-M,6"
+set abc_map_new_area  	"amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
+
+if {$buffering==1} {
+	set abc_fine_tune		"buffer,-N,${max_FO},-S,${max_Tran};upsize,{D};dnsize,{D}"
+} elseif {$sizing} {
+	set abc_fine_tune       "upsize,{D};dnsize,{D}"
+} else {
+	set abc_fine_tune       ""
+}
+
+
+set delay_scripts [list \
+	"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_map_old_dly};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+	\
+	"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice2};${abc_map_old_dly};${abc_area_recovery_2}; retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+	\
+	"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice};${abc_map_old_dly};${abc_area_recovery_1}; retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+	\
+	"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_old_dly};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+	]
+
+set area_scripts [list \
+	"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+	\
+	"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+	\
+	"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_choice2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+	]
+
+set all_scripts [list {*}$delay_scripts {*}$area_scripts]
+
+set strategy_parts [split $::env(SYNTH_STRATEGY)]
+
+proc synth_strategy_format_err { } {
+	upvar area_scripts area_scripts
+	upvar delay_scripts delay_scripts
+	log -stderr "\[ERROR] Misformatted SYNTH_STRATEGY (\"$::env(SYNTH_STRATEGY)\")."
+	log -stderr "\[ERROR] Correct format is \"DELAY|AREA 0-[expr [llength $delay_scripts]-1]|0-[expr [llength $area_scripts]-1]\"."
+	exit 1
+}
+
+if { [llength $strategy_parts] != 2 } {
+	synth_strategy_format_err
+}
+
+set strategy_type [lindex $strategy_parts 0]
+set strategy_type_idx [lindex $strategy_parts 1]
+
+if { $strategy_type != "AREA" && $strategy_type != "DELAY" } {
+	log -stderr "\[ERROR] AREA|DELAY tokens not found. ($strategy_type)"
+	synth_strategy_format_err
+}
+
+if { $strategy_type == "DELAY" && $strategy_type_idx >= [llength $delay_scripts] } {
+	log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high."
+	synth_strategy_format_err
+}
+
+if { $strategy_type == "AREA" && $strategy_type_idx >= [llength $area_scripts] } {
+	log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high."
+	synth_strategy_format_err
+}
+
+if { $strategy_type == "DELAY" } {
+	set strategy $strategy_type_idx
+} else {
+	set strategy [expr {[llength $delay_scripts]+$strategy_type_idx}]
+}
+
+
+for { set i 0 } { $i < [llength $::env(VERILOG_FILES)] } { incr i } {
+	read_verilog -sv {*}$vIdirsArgs [lindex $::env(VERILOG_FILES) $i]
+}
+
+if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
+	foreach verilog_file $::env(VERILOG_FILES_BLACKBOX) {
+		read_verilog -sv {*}$vIdirsArgs -lib $verilog_file
+	}
+}
+select -module $vtop
+show -format dot -prefix $::env(TMP_DIR)/synthesis/hierarchy
+select -clear
+
+hierarchy -check -top $vtop
+
+# Infer tri-state buffers.
+set tbuf_map false
+if { [info exists ::env(TRISTATE_BUFFER_MAP)] } {
+        if { [file exists $::env(TRISTATE_BUFFER_MAP)] } {
+                set tbuf_map true
+                tribuf
+        } else {
+          log "WARNING: TRISTATE_BUFFER_MAP is defined but could not be found: $::env(TRISTATE_BUFFER_MAP)"
+        }
+}
+
+if { $::env(SYNTH_NO_FLAT) } {
+	synth -top $vtop
+} else {
+	synth -top $vtop -flatten
+}
+
+share -aggressive
+opt
+opt_clean -purge
+
+tee -o "$::env(yosys_report_file_tag)_pre.stat" stat
+
+# Map tri-state buffers.
+if { $tbuf_map } {
+        log {mapping tbuf}
+        techmap -map $::env(TRISTATE_BUFFER_MAP)
+        simplemap
+}
+
+# handle technology mapping of 4-MUX, and tell Yosys to infer 4-muxes
+if { [info exists ::env(SYNTH_MUX4_MAP)] && [file exists $::env(SYNTH_MUX4_MAP)] } {
+  muxcover -mux4 
+  techmap -map $::env(SYNTH_MUX4_MAP)
+  simplemap
+}
+
+# handle technology mapping of 2-MUX
+if { [info exists ::env(SYNTH_MUX_MAP)] && [file exists $::env(SYNTH_MUX_MAP)] } {
+  techmap -map $::env(SYNTH_MUX_MAP)
+  simplemap
+}
+
+# handle technology mapping of latches
+if { [info exists ::env(SYNTH_LATCH_MAP)] && [file exists $::env(SYNTH_LATCH_MAP)] } {
+	techmap -map $::env(SYNTH_LATCH_MAP)
+	simplemap
+}
+
+dfflibmap -liberty $sclib
+tee -o "$::env(yosys_report_file_tag)_dff.stat" stat
+
+if { [info exists ::env(SYNTH_EXPLORE)] && $::env(SYNTH_EXPLORE) } {
+	design -save myDesign
+
+	for { set index 0 }  { $index < [llength $all_scripts] }  { incr index } {
+		log "\[INFO\]: ABC: WireLoad : S_$index"
+		design -load myDesign
+
+		abc -D $clock_period \
+			-constr "$sdc_file" \
+			-liberty $sclib  \
+			-script [lindex $all_scripts $index]
+
+		setundef -zero
+
+		hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT)
+
+		# get rid of the assignments that make verilog2def fail
+		splitnets
+		opt_clean -purge
+		insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
+
+		tee -o "$::env(yosys_report_file_tag)_$index$chk_ext" check
+		write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(yosys_result_file_tag)_$index.v"
+		design -reset
+	}
+} else {
+
+	log "\[INFO\]: ABC: WireLoad : S_$strategy"
+
+	abc -D $clock_period \
+		-constr "$sdc_file" \
+		-liberty $sclib  \
+		-script [lindex $all_scripts $strategy] \
+		-showtmp;
+
+	setundef -zero
+
+	hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT)
+
+	# get rid of the assignments that make verilog2def fail
+	splitnets
+	opt_clean -purge
+	insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
+
+	tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check
+	write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
+}
+
+if { $::env(SYNTH_NO_FLAT) } {
+	design -reset
+	file copy -force $::env(SAVE_NETLIST) $::env(yosys_tmp_file_tag)_unflat.v
+	read_verilog -sv $::env(SAVE_NETLIST)
+	synth -top $vtop -flatten
+	splitnets
+	opt_clean -purge
+	insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
+	write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
+	tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check
+}
diff --git a/verilog/rtl/digital_core/src/digital_core.sv b/verilog/rtl/digital_core/src/digital_core.sv
index 2ead606..2e042cd 100644
--- a/verilog/rtl/digital_core/src/digital_core.sv
+++ b/verilog/rtl/digital_core/src/digital_core.sv
@@ -112,28 +112,29 @@
 //////////////////////////////////////////////////////////////////////
 
 
-module digital_core 
-#(
-	parameter      SDR_DW   = 8,  // SDR Data Width 
-        parameter      SDR_BW   = 1,  // SDR Byte Width
-	parameter      WB_WIDTH = 32  // WB ADDRESS/DARA WIDTH
- ) (
+module digital_core (
 `ifdef USE_POWER_PINS
+    inout vdda1,	// User area 1 3.3V supply
+    inout vdda2,	// User area 2 3.3V supply
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
     inout vccd1,	// User area 1 1.8V supply
+    inout vccd2,	// User area 2 1.8v supply
     inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
 `endif
     input   wire                       wb_clk_i        ,  // System clock
     input   wire                       user_clock2     ,  // user Clock
     input   wire                       wb_rst_i        ,  // Regular Reset signal
 
-    input   wire                       wbd_ext_cyc_i   ,  // strobe/request
-    input   wire                       wbd_ext_stb_i   ,  // strobe/request
-    input   wire [WB_WIDTH-1:0]        wbd_ext_adr_i   ,  // address
-    input   wire                       wbd_ext_we_i    ,  // write
-    input   wire [WB_WIDTH-1:0]        wbd_ext_dat_i   ,  // data output
-    input   wire [3:0]                 wbd_ext_sel_i   ,  // byte enable
-    output  wire [WB_WIDTH-1:0]        wbd_ext_dat_o   ,  // data input
-    output  wire                       wbd_ext_ack_o   ,  // acknowlegement
+    input   wire                       wbs_cyc_i       ,  // strobe/request
+    input   wire                       wbs_stb_i       ,  // strobe/request
+    input   wire [WB_WIDTH-1:0]        wbs_adr_i       ,  // address
+    input   wire                       wbs_we_i        ,  // write
+    input   wire [WB_WIDTH-1:0]        wbs_dat_i       ,  // data output
+    input   wire [3:0]                 wbs_sel_i       ,  // byte enable
+    output  wire [WB_WIDTH-1:0]        wbs_dat_o       ,  // data input
+    output  wire                       wbs_ack_o       ,  // acknowlegement
 
  
     // Logic Analyzer Signals
@@ -155,6 +156,9 @@
 // Local Parameter Declaration
 // --------------------------------------------------
 
+parameter      SDR_DW   = 8;  // SDR Data Width 
+parameter      SDR_BW   = 1;  // SDR Byte Width
+parameter      WB_WIDTH = 32; // WB ADDRESS/DARA WIDTH
 
 //---------------------------------------------------------------------
 // Wishbone Risc V Instruction Memory Interface
@@ -263,6 +267,30 @@
 wire [7:0]                        cfg_glb_ctrl  ;
 wire [31:0]                       cfg_clk_ctrl1 ;
 wire [31:0]                       cfg_clk_ctrl2 ;
+wire [3:0]                        cfg_cska_wi   ; // clock skew adjust for wishbone interconnect
+wire [3:0]                        cfg_cska_riscv; // clock skew adjust for riscv
+wire [3:0]                        cfg_cska_uart ; // clock skew adjust for uart
+wire [3:0]                        cfg_cska_spi  ; // clock skew adjust for spi
+wire [3:0]                        cfg_cska_sdram; // clock skew adjust for sdram
+wire [3:0]                        cfg_cska_glbl ; // clock skew adjust for global reg
+wire [3:0]                        cfg_cska_wh   ; // clock skew adjust for web host
+
+
+wire                              wbd_clk_wi    ; // clock for wishbone interconnect
+wire                              wbd_clk_riscv ; // clock for riscv
+wire                              wbd_clk_uart  ; // clock for uart
+wire                              wbd_clk_spi   ; // clock for spi
+wire                              wbd_clk_sdram ; // clock for sdram
+wire                              wbd_clk_glbl  ; // clock for global reg
+wire                              wbd_clk_wh    ; // clock for global reg
+
+wire [3:0]                        cfg_cska_sd_co; // clock skew adjust for sdram clock out
+wire [3:0]                        cfg_cska_sd_ci; // clock skew adjust for sdram clock input
+wire [3:0]                        cfg_cska_sp_co; // clock skew adjust for SPI clock out
+
+wire                              io_out_29_    ; // Internally tapped SDRAM clock
+wire                              io_in_29_     ; // Clock Skewed Pad SDRAM clock
+wire                              io_in_30_     ; // SPI clock out
 
 //------------------------------------------------
 // Configuration Parameter
@@ -289,11 +317,22 @@
 /////////////////////////////////////////////////////////
 // Generating acive low wishbone reset                 
 // //////////////////////////////////////////////////////
-assign wbd_int_rst_n = cfg_glb_ctrl[0];
-assign cpu_rst_n     = cfg_glb_ctrl[1];
-assign spi_rst_n     = cfg_glb_ctrl[2];
-assign sdram_rst_n   = cfg_glb_ctrl[3];
+assign wbd_int_rst_n  = cfg_glb_ctrl[0];
+assign cpu_rst_n      = cfg_glb_ctrl[1];
+assign spi_rst_n      = cfg_glb_ctrl[2];
+assign sdram_rst_n    = cfg_glb_ctrl[3];
 
+assign cfg_cska_wi    = cfg_clk_ctrl1[3:0];
+assign cfg_cska_riscv = cfg_clk_ctrl1[7:4];
+assign cfg_cska_uart  = cfg_clk_ctrl1[11:8];
+assign cfg_cska_spi   = cfg_clk_ctrl1[15:12];
+assign cfg_cska_sdram = cfg_clk_ctrl1[19:16];
+assign cfg_cska_glbl  = cfg_clk_ctrl1[23:20];
+assign cfg_cska_wh    = cfg_clk_ctrl1[27:24];
+
+assign cfg_cska_sd_co = cfg_clk_ctrl2[3:0]; // SDRAM clock out control
+assign cfg_cska_sd_ci = cfg_clk_ctrl2[7:4]; // SDRAM clock in control
+assign cfg_cska_sp_co = cfg_clk_ctrl2[11:8];// SPI clock out control
 
 
 wb_host u_wb_host(
@@ -301,19 +340,19 @@
     // Master Port
        .wbm_rst_i        (wb_rst_i             ),  
        .wbm_clk_i        (wb_clk_i             ),  
-       .wbm_cyc_i        (wbd_ext_cyc_i        ),  
-       .wbm_stb_i        (wbd_ext_stb_i        ),  
-       .wbm_adr_i        (wbd_ext_adr_i        ),  
-       .wbm_we_i         (wbd_ext_we_i         ),  
-       .wbm_dat_i        (wbd_ext_dat_i        ),  
-       .wbm_sel_i        (wbd_ext_sel_i        ),  
-       .wbm_dat_o        (wbd_ext_dat_o        ),  
-       .wbm_ack_o        (wbd_ext_ack_o        ),  
+       .wbm_cyc_i        (wbs_cyc_i            ),  
+       .wbm_stb_i        (wbs_stb_i            ),  
+       .wbm_adr_i        (wbs_adr_i            ),  
+       .wbm_we_i         (wbs_we_i             ),  
+       .wbm_dat_i        (wbs_dat_i            ),  
+       .wbm_sel_i        (wbs_sel_i            ),  
+       .wbm_dat_o        (wbs_dat_o            ),  
+       .wbm_ack_o        (wbs_ack_o            ),  
        .wbm_err_o        (                     ),  
 
     // Slave Port
        .wbs_clk_out      (wbd_clk_int          ),  
-       .wbs_clk_i        (wbd_clk_int          ),  
+       .wbs_clk_i        (wbd_clk_wh           ),  
        .wbs_cyc_o        (wbd_int_cyc_i        ),  
        .wbs_stb_o        (wbd_int_stb_i        ),  
        .wbs_adr_o        (wbd_int_adr_i        ),  
@@ -362,8 +401,8 @@
     // .test_rst_n          (1'b1                      ), // Moved inside IP
 
     
-    .wb_rst_n               (wbd_int_rst_n              ),
-    .wb_clk                 (wbd_clk_int               ),
+    .wb_rst_n               (wbd_int_rst_n             ),
+    .wb_clk                 (wbd_clk_riscv             ),
     // Instruction memory interface
     .wbd_imem_stb_o         (wbd_riscv_imem_stb_i      ),
     .wbd_imem_adr_o         (wbd_riscv_imem_adr_i      ),
@@ -399,7 +438,7 @@
 `endif
 ) u_spi_master
 (
-    .mclk                   (wbd_clk_int               ),
+    .mclk                   (wbd_clk_spi               ),
     .rst_n                  (spi_rst_n                 ),
 
     .wbd_stb_i              (wbd_spim_stb_o            ),
@@ -415,7 +454,7 @@
 
     // Pad Interface
     .io_in                  (io_in[35:30]              ),
-    .io_out                 (io_out[35:30]             ),
+    .io_out                 ({io_out[35:31],io_in_30_} ),
     .io_oeb                 (io_oeb[35:30]             )
 
 );
@@ -435,7 +474,7 @@
                     
     // WB bus
     .wb_rst_n               (wbd_int_rst_n              ),
-    .wb_clk_i               (wbd_clk_int                ),
+    .wb_clk_i               (wbd_clk_sdram              ),
     
     .wb_stb_i               (wbd_sdram_stb_o            ),
     .wb_addr_i              (wbd_sdram_adr_o            ),
@@ -452,9 +491,9 @@
     .sdram_resetn           (sdram_rst_n               ),
 
     /** Pad Interface       **/
-    .io_in                  (io_in[29:0]               ),
+    .io_in                  ({io_in_29_,io_in[28:0]}   ),
     .io_oeb                 (io_oeb[29:0]              ),
-    .io_out                 (io_out[29:0]              ),
+    .io_out                 ({io_out_29_,io_out[28:0]} ),
                     
     /* Parameters */
     .sdr_init_done          (sdr_init_done             ),
@@ -473,7 +512,7 @@
 
 
 wb_interconnect  u_intercon (
-         .clk_i         (wbd_clk_int           ), 
+         .clk_i         (wbd_clk_wi            ), 
          .rst_n         (wbd_int_rst_n         ),
 
          // Master 0 Interface
@@ -557,8 +596,9 @@
 
 glbl_cfg   u_glbl_cfg (
 
-       .mclk                   (wbd_clk_int               ),
+       .mclk                   (wbd_clk_glbl              ),
        .reset_n                (wbd_int_rst_n             ),
+       .user_clock1            (wb_clk_i                  ),
        .user_clock2            (user_clock2               ),
        .device_idcode          (                          ),
 
@@ -608,7 +648,7 @@
 
 uart_core   u_uart_core (
         .arst_n                 (wbd_int_rst_n            ), // async reset
-        .app_clk                (wbd_clk_int              ),
+        .app_clk                (wbd_clk_uart             ),
 
         // Reg Bus Interface Signal
        .reg_cs                 (wbd_uart_stb_o            ),
@@ -628,5 +668,128 @@
 
      );
 
+////////////////////////////////////////////////////////////////
+// Clock Skew adjust module
+// ///////////////////////////////////////////////////////////
+
+// Wishbone interconnect clock skew control
+clk_skew_adjust u_skew_wi
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (wbd_clk_int                 ), 
+	       .sel        (cfg_cska_wi                 ), 
+	       .clk_out    (wbd_clk_wi                  ) 
+       );
+
+// riscv clock skew control
+clk_skew_adjust u_skew_riscv
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (wbd_clk_int                 ), 
+	       .sel        (cfg_cska_riscv              ), 
+	       .clk_out    (wbd_clk_riscv               ) 
+       );
+
+// uart clock skew control
+clk_skew_adjust u_skew_uart
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (wbd_clk_int                 ), 
+	       .sel        (cfg_cska_uart               ), 
+	       .clk_out    (wbd_clk_uart                ) 
+       );
+
+// spi clock skew control
+clk_skew_adjust u_skew_spi
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (wbd_clk_int                ), 
+	       .sel        (cfg_cska_spi               ), 
+	       .clk_out    (wbd_clk_spi                ) 
+       );
+
+// sdram clock skew control
+clk_skew_adjust u_skew_sdram
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (wbd_clk_int                ), 
+	       .sel        (cfg_cska_sdram             ), 
+	       .clk_out    (wbd_clk_sdram              ) 
+       );
+
+// global clock skew control
+clk_skew_adjust u_skew_glbl
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (wbd_clk_int               ), 
+	       .sel        (cfg_cska_glbl             ), 
+	       .clk_out    (wbd_clk_glbl              ) 
+       );
+
+// wb_host clock skew control
+clk_skew_adjust u_skew_wh
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (wbd_clk_int               ), 
+	       .sel        (cfg_cska_wh               ), 
+	       .clk_out    (wbd_clk_wh                ) 
+       );
+
+// SDRAM clock out clock skew control
+clk_skew_adjust u_skew_sd_co
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (io_out_29_                ), 
+	       .sel        (cfg_cska_sd_co            ), 
+	       .clk_out    (io_out[29]                ) 
+       );
+
+// Clock Skey for PAD SDRAM clock
+clk_skew_adjust u_skew_sd_ci
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (io_in[29]                 ), 
+	       .sel        (cfg_cska_sd_ci            ), 
+	       .clk_out    (io_in_29_                 ) 
+       );
+
+// Clock Skey for SPI clock out
+clk_skew_adjust u_skew_sp_co
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (io_in_30_                 ), 
+	       .sel        (cfg_cska_sp_co            ), 
+	       .clk_out    (io_out[30]                ) 
+       );
 
 endmodule : digital_core
diff --git a/verilog/rtl/digital_core/src/glbl_cfg.sv b/verilog/rtl/digital_core/src/glbl_cfg.sv
index a91502e..74557e7 100644
--- a/verilog/rtl/digital_core/src/glbl_cfg.sv
+++ b/verilog/rtl/digital_core/src/glbl_cfg.sv
@@ -66,6 +66,7 @@
 module glbl_cfg (
 
         input logic             mclk,
+        input logic             user_clock1,
         input logic             user_clock2,
         input logic             reset_n,
         output logic [31:0]     device_idcode,
@@ -1067,7 +1068,7 @@
 wire   sdram_clk_div;
 wire   sdram_ref_clk;
 
-assign sdram_ref_clk = (cfg_sdram_clk_src_sel) ? user_clock2 : mclk;
+assign sdram_ref_clk = (cfg_sdram_clk_src_sel) ? user_clock2 :user_clock1;
 
 
 
@@ -1090,7 +1091,7 @@
 wire   cpu_clk_div;
 wire   cpu_ref_clk;
 
-assign cpu_ref_clk = (cfg_cpu_clk_src_sel) ? user_clock2 : mclk;
+assign cpu_ref_clk = (cfg_cpu_clk_src_sel) ? user_clock2 : user_clock1;
 assign cpu_clk     = (cfg_cpu_clk_div)     ? cpu_clk_div : cpu_ref_clk;
 
 
@@ -1109,7 +1110,7 @@
 wire   rtc_clk_div;
 wire   rtc_ref_clk;
 
-assign rtc_ref_clk = (cfg_rtc_clk_src_sel) ? user_clock2 : mclk;
+assign rtc_ref_clk = (cfg_rtc_clk_src_sel) ? user_clock2 : user_clock1;
 assign rtc_clk     = (cfg_rtc_clk_div)     ? rtc_clk_div : rtc_ref_clk;
 
 
diff --git a/verilog/rtl/lib/async_wb.sv b/verilog/rtl/lib/async_wb.sv
index 9908e54..df1fbce 100644
--- a/verilog/rtl/lib/async_wb.sv
+++ b/verilog/rtl/lib/async_wb.sv
@@ -15,7 +15,6 @@
 // SPDX-License-Identifier: Apache-2.0
 // SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
 //
-/*********************************************************************
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 ////  Async Wishbone Interface                                    ////
diff --git a/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v b/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v
index dc66c23..2430831 100755
--- a/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v
+++ b/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v
@@ -14,8 +14,8 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 // SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-/*********************************************************************
+///////////////////////////////////////////////////////////////////////////
+
 `define SDR_REQ_ID_W       4
 
 `define SDR_RFSH_TIMER_W    12
diff --git a/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v b/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
index ab49c52..6aba2a6 100755
--- a/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
+++ b/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
@@ -55,6 +55,8 @@
 		  at digital core level
              0.4 - 27th June 2021
 	          Unused port wb_cti_i removed
+             0.5 - 29th June 2021
+	          Wishbone Stagging FF added to break timing path
 
                                                              
  Copyright (C) 2000 Authors and OPENCORES.ORG                
@@ -218,6 +220,17 @@
 wire [APP_DW-1:0]     app_wr_data        ; // sdr write data
 wire  [APP_DW-1:0]    app_rd_data        ; // sdr read data
 
+//--------------------------------------------------
+//  WishBone Stagging FF
+//--------------------------------------------------
+wire                   wb_stag_stb_i     ;
+wire                   wb_stag_ack_o     ;
+wire [APP_AW-1:0]      wb_stag_addr_i    ;
+wire                   wb_stag_we_i      ; // 1 - Write, 0 - Read
+wire [APP_DW-1:0]      wb_stag_dat_i     ;
+wire [APP_DW/8-1:0]    wb_stag_sel_i     ; // Byte enable
+wire  [APP_DW-1:0]     wb_stag_dat_o     ;
+wire                   wb_stag_cyc_i     ;
 //-----------------------------------------------------------------
 // To avoid the logic at digital core, pad control are brought inside the
 // block to support efabless/carvel soc enviornmental support
@@ -254,19 +267,52 @@
 //wire #(1.0) sdram_pad_clk = sdram_clk;
 
 /************** Ends Here **************************/
+
+// Adding Wishbone stagging FF to break timing path
+//
+wb_stagging u_wb_stage (
+         .clk_i                 (wb_clk_i         ), 
+         .rst_n                 (wb_rst_n         ),
+         // WishBone Input master I/P
+         .m_wbd_dat_i           (wb_dat_i         ),
+         .m_wbd_adr_i           (wb_addr_i        ),
+         .m_wbd_sel_i           (wb_sel_i         ),
+         .m_wbd_we_i            (wb_we_i          ),
+         .m_wbd_cyc_i           (wb_cyc_i         ),
+         .m_wbd_stb_i           (wb_stb_i         ),
+         .m_wbd_tid_i           ('h0              ),
+         .m_wbd_dat_o           (wb_dat_o         ),
+         .m_wbd_ack_o           (wb_ack_o         ),
+         .m_wbd_err_o           (                 ),
+
+         // Slave Interface
+         .s_wbd_dat_i          (wb_stag_dat_o     ),
+         .s_wbd_ack_i          (wb_stag_ack_o     ),
+         .s_wbd_err_i          (1'b0              ),
+         .s_wbd_dat_o          (wb_stag_dat_i     ),
+         .s_wbd_adr_o          (wb_stag_addr_i    ),
+         .s_wbd_sel_o          (wb_stag_sel_i     ),
+         .s_wbd_we_o           (wb_stag_we_i      ),
+         .s_wbd_cyc_o          (wb_stag_cyc_i     ),
+         .s_wbd_stb_o          (wb_stag_stb_i     ),
+         .s_wbd_tid_o          (                  )
+
+);
+
+
 wb2sdrc #(.dw(APP_DW),.tw(tw),.bl(bl),.APP_AW(APP_AW)) u_wb2sdrc (
       // WB bus
           .wb_rst_n           (wb_rst_n           ) ,
           .wb_clk_i           (wb_clk_i           ) ,
 
-          .wb_stb_i           (wb_stb_i           ) ,
-          .wb_ack_o           (wb_ack_o           ) ,
-          .wb_addr_i          (wb_addr_i          ) ,
-          .wb_we_i            (wb_we_i            ) ,
-          .wb_dat_i           (wb_dat_i           ) ,
-          .wb_sel_i           (wb_sel_i           ) ,
-          .wb_dat_o           (wb_dat_o           ) ,
-          .wb_cyc_i           (wb_cyc_i           ) ,
+          .wb_stb_i           (wb_stag_stb_i      ) ,
+          .wb_ack_o           (wb_stag_ack_o      ) ,
+          .wb_addr_i          (wb_stag_addr_i     ) ,
+          .wb_we_i            (wb_stag_we_i       ) ,
+          .wb_dat_i           (wb_stag_dat_i      ) ,
+          .wb_sel_i           (wb_stag_sel_i      ) ,
+          .wb_dat_o           (wb_stag_dat_o      ) ,
+          .wb_cyc_i           (wb_stag_cyc_i      ) ,
 
 
       //SDRAM Controller Hand-Shake Signal 
diff --git a/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v b/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v
index 1a6cc6b..f6eadc1 100755
--- a/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v
+++ b/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v
@@ -386,3 +386,4 @@
 
  
 endmodule
+
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
index d2bccd2..1580b36 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
@@ -1,3 +1,4 @@
+/*
 //////////////////////////////////////////////////////////////////////////////
 // SPDX-FileCopyrightText: Syntacore LLC © 2016-2021
 // 
@@ -15,6 +16,7 @@
 // SPDX-License-Identifier: Apache-2.0
 // SPDX-FileContributor: Syntacore LLC
 // //////////////////////////////////////////////////////////////////////////
+*/
 /*
 * @file       <link.ld>
 * @brief      bare metal tests' linker script
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh
index ebe67e6..1b1b273 100644
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh
+++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh
@@ -87,3 +87,4 @@
 } type_scr1_op_width_e;
 
 `endif //SCR1_ARCH_TYPES_SVH
+
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index e31d589..8445819 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -16,10 +16,10 @@
 // Include caravel global defines for the number of the user project IO pads 
 `include "defines.v"
 `define USE_POWER_PINS
+`define UNIT_DELAY #1
 
 `ifdef GL
     // Assume default net type to be wire because GL netlists don't have the wire definitions
-    `default_nettype wire
     `include "gl/user_project_wrapper.v"
     `include "gl/user_proj_example.v"
 `else
@@ -91,5 +91,8 @@
      `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
      `include "syntacore/scr1/src/top/scr1_top_wb.sv"
      `include "lib/sync_fifo.sv"
-
+     // we are using netlist file for clk_skew_adjust as it has 
+     // standard cell + power pin
+     `include "gl/clk_skew_adjust.v"
 `endif
+
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index bf72715..404711c 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -85,8 +85,14 @@
 
 digital_core u_core (
     `ifdef USE_POWER_PINS
-	.vccd1(vccd1),	// User area 1 1.8V power
-	.vssd1(vssd1),	// User area 1 digital ground
+        .vdda1(vdda1),	// User area 1 3.3V supply
+        .vdda2(vdda2),	// User area 2 3.3V supply
+        .vssa1(vssa1),	// User area 1 analog ground
+        .vssa2(vssa2),	// User area 2 analog ground
+        .vccd1(vccd1),	// User area 1 1.8V supply
+        .vccd2(vccd2),	// User area 2 1.8v supply
+        .vssd1(vssd1),	// User area 1 digital ground
+        .vssd2(vssd2),	// User area 2 digital ground
     `endif
 
     .wb_clk_i(wb_clk_i),
@@ -95,14 +101,14 @@
 
     // MGMT SoC Wishbone Slave
 
-    .wbd_ext_cyc_i(wbs_cyc_i),
-    .wbd_ext_stb_i(wbs_stb_i),
-    .wbd_ext_we_i(wbs_we_i),
-    .wbd_ext_sel_i(wbs_sel_i),
-    .wbd_ext_adr_i(wbs_adr_i),
-    .wbd_ext_dat_i(wbs_dat_i),
-    .wbd_ext_ack_o(wbs_ack_o),
-    .wbd_ext_dat_o(wbs_dat_o),
+    .wbs_cyc_i(wbs_cyc_i),
+    .wbs_stb_i(wbs_stb_i),
+    .wbs_we_i(wbs_we_i),
+    .wbs_sel_i(wbs_sel_i),
+    .wbs_adr_i(wbs_adr_i),
+    .wbs_dat_i(wbs_dat_i),
+    .wbs_ack_o(wbs_ack_o),
+    .wbs_dat_o(wbs_dat_o),
 
     // Logic Analyzer
 
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 6464c64..8032f11 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -135,11 +135,12 @@
 logic [31:0]        wbm_adr_int;
 logic               wbm_stb_int;
 
+logic [2:0]         cfg_wb_clk_ctr;
+
 
 assign wbm_rst_n = !wbm_rst_i;
 assign wbs_rst_n = !wbm_rst_i;
 
-assign wbs_clk_out =  wbm_clk_i;
 
 assign  wbm_dat_o   = (reg_sel) ? reg_rdata : wbm_dat_int;  // data input
 assign  wbm_ack_o   = (reg_sel) ? reg_ack   : wbm_ack_int; // acknowlegement
@@ -194,7 +195,7 @@
   reg_out [31:0] = 8'd0;
 
   case (sw_addr [1:0])
-    2'b00 :   reg_out [31:0] = {24'h0,cfg_glb_ctrl [7:0]};     
+    2'b00 :   reg_out [31:0] = {21'h0,cfg_wb_clk_ctr[2:0],cfg_glb_ctrl [7:0]};     
     2'b01 :   reg_out [31:0] = {24'h0,cfg_bank_sel [7:0]};     
     2'b10 :   reg_out [31:0] = cfg_clk_ctrl1 [31:0];    
     2'b11 :   reg_out [31:0] = cfg_clk_ctrl2 [31:0];     
@@ -204,14 +205,15 @@
 
 
 
-generic_register #(8,0  ) u_glb_ctrl (
-	      .we            ({8{sw_wr_en_0}}   ),		 
-	      .data_in       (wbm_dat_i[7:0]    ),
+generic_register #(11,0  ) u_glb_ctrl (
+	      .we            ({11{sw_wr_en_0}}   ),		 
+	      .data_in       (wbm_dat_i[10:0]    ),
 	      .reset_n       (wbm_rst_n         ),
 	      .clk           (wbm_clk_i         ),
 	      
 	      //List of Outs
-	      .data_out      (cfg_glb_ctrl[7:0] )
+	      .data_out      ({cfg_wb_clk_ctr[2:0],
+		               cfg_glb_ctrl[7:0]} )
           );
 
 generic_register #(8,8'h30 ) u_bank_sel (
@@ -282,6 +284,28 @@
     );
 
 
+//----------------------------------
+// Generate Internal WishBone Clock
+//----------------------------------
+logic       wb_clk_div;
+logic       cfg_wb_clk_div;
+logic [1:0] cfg_wb_clk_ratio;
+
+assign    cfg_wb_clk_ratio =  cfg_wb_clk_ctr[1:0];
+assign    cfg_wb_clk_div   =  cfg_wb_clk_ctr[2];
+
+
+assign wbs_clk_out  = (cfg_wb_clk_div)  ? wb_clk_div : wbm_clk_i;
+
+
+clk_ctl #(1) u_wbclk (
+   // Outputs
+       .clk_o         (wb_clk_div      ),
+   // Inputs
+       .mclk          (wbm_clk_i       ),
+       .reset_n       (wbm_rst_n        ), 
+       .clk_div_ratio (cfg_wb_clk_ratio )
+   );
 
 
 endmodule