diff --git a/openlane/mbist1/config.tcl b/openlane/mbist1/config.tcl
index cc310b7..1876487 100755
--- a/openlane/mbist1/config.tcl
+++ b/openlane/mbist1/config.tcl
@@ -79,7 +79,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 200 350"
+set ::env(DIE_AREA) "0 0 200 275"
 
 
 # If you're going to use multiple power domains, then keep this disabled.
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 20feabd..d85c42a 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -115,15 +115,15 @@
 set ::env(GND_PIN) "vssd1 vssd2 vssa1 vssa2"
 
 set ::env(GLB_RT_OBS) " 
-                        li1  200 175  883.1 591.54,\
-                        met1 200 175  883.1 591.54,\
-	                met2 200 175  883.1 591.54,\
-	                met3 200 175  883.1 591.54,\
-	                met4 200 175  883.1 591.54,\
-                        li1  200 1300  883.1 1716.54,\
-                        met1 200 1300  883.1 1716.54,\
-	                met2 200 1300  883.1 1716.54,\
-	                met3 200 1300  883.1 1716.54,\
+                        li1  200 165  883.1 581.54,\
+                        met1 200 165  883.1 581.54,\
+	                met2 200 165  883.1 581.54,\
+	                met3 200 165  883.1 581.54,\
+	                met4 200 195  883.1 581.54,\
+                        li1  200 1325  883.1 1741.54,\
+                        met1 200 1325  883.1 1741.54,\
+	                met2 200 1325  883.1 1741.54,\
+	                met3 200 1325  883.1 1741.54,\
                         li1  200 1850  883.1 2266.54,\
                         met1 200 1850  883.1 2266.54,\
 	                met2 200 1850  883.1 2266.54,\
@@ -181,7 +181,7 @@
 set ::env(QUIT_ON_TR_DRC) "0"
 
 
-set ::env(FP_PDN_HPITCH) "80"
+set ::env(FP_PDN_HPITCH) "90"
 set ::env(FP_PDN_VPITCH) "180"
 set ::env(FP_PDN_HSPACING) "6"
 
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a224082..9de5b13 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -2,10 +2,10 @@
 u_uart_i2c_usb_spi      2200            1400           N
 u_pinmux                2200            2300           N
 u_riscv_top	        200	        700	       N
-u_sram_2kb              200             175            N
+u_sram_2kb              200             165            N
 
 u_mbist1                1100            1300           N
-u_sram1_2kb             200             1300           N
+u_sram1_2kb             200             1325           N
 
 u_mbist2                1100            1850           N
 u_sram2_2kb             200             1850           N
diff --git a/signoff/mbist1/final_summary_report.csv b/signoff/mbist1/final_summary_report.csv
index c629a6b..d452efb 100644
--- a/signoff/mbist1/final_summary_report.csv
+++ b/signoff/mbist1/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/mbist1,mbist_top1,mbist1,flow_completed,0h4m45s,-1,35628.57142857143,0.07,17814.285714285714,21.94,556.2,1247,0,0,0,0,0,0,0,2,0,0,-1,83477,14731,-1.26,-1.78,-1,-1.69,-1,-20.05,-28.55,-1,-34.55,-1,51119249.0,14.63,28.27,23.81,8.18,0.47,-1,1182,2538,325,1649,0,0,0,1156,0,0,0,0,0,0,0,4,231,261,16,240,854,0,1094,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/mbist1,mbist_top1,mbist1,flow_completed,0h4m36s,-1,45345.454545454544,0.055,22672.727272727272,28.31,565.84,1247,0,0,0,0,0,0,0,1,0,0,-1,79820,14384,-1.26,-1.78,-1,-1.47,-1,-20.05,-28.82,-1,-32.82,-1,50155361.0,15.2,37.82,27.67,8.7,0.06,-1,1182,2538,325,1649,0,0,0,1156,0,0,0,0,0,0,0,4,231,261,16,186,665,0,851,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index b190986..11fdeb7 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h38m54s,-1,2.9187422166874217,10.2784,1.4593711083437109,-1,535.91,15,0,0,0,0,0,0,-1,0,0,-1,-1,1472837,10805,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.52,4.64,3.24,0.49,0.54,-1,298,2697,298,2697,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,80,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h37m7s,-1,2.9187422166874217,10.2784,1.4593711083437109,-1,534.86,15,0,0,0,0,0,0,-1,0,0,-1,-1,1473539,10786,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.52,4.54,3.22,0.59,0.54,-1,298,2697,298,2697,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,90,0.55,0.0,sky130_fd_sc_hd,4,0