diff --git a/openlane/Makefile b/openlane/Makefile
index c782204..ecdee61 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -19,7 +19,7 @@
 CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
 CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
 
-OPENLANE_TAG = mpw4
+OPENLANE_TAG = mpw5
 OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)
 OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
 OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
diff --git a/openlane/Read.me b/openlane/Read.me
new file mode 100644
index 0000000..395a9e5
--- /dev/null
+++ b/openlane/Read.me
@@ -0,0 +1,3 @@
+yifive harden with riscduino/openlane:mpw4  (mpw5 version not able to root due to conjuestion)
+Rest of the cores & top-level are  harden with riscduino/openlane:mpw5 docker
+
diff --git a/openlane/pinmux/base.sdc b/openlane/pinmux/base.sdc
index bea31b6..91f9b40 100644
--- a/openlane/pinmux/base.sdc
+++ b/openlane/pinmux/base.sdc
@@ -44,11 +44,16 @@
 set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
 
 
-set_output_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
-set_output_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
 
-set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
-set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+set_output_delay -min -3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -min -3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+
+
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {qspim_rst_n}]
+set_output_delay -min -3.000 -clock [get_clocks {mclk}] -add_delay [get_ports {qspim_rst_n}]
+
 ###############################################################################
 # Environment
 ###############################################################################
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl
index ce6c000..f082733 100755
--- a/openlane/pinmux/config.tcl
+++ b/openlane/pinmux/config.tcl
@@ -49,7 +49,9 @@
      $script_dir/../../verilog/rtl/lib/pulse_gen_type1.sv   \
      $script_dir/../../verilog/rtl/lib/pulse_gen_type2.sv   \
      $script_dir/../../verilog/rtl/lib/ser_inf_32b.sv       \
-     $script_dir/../../verilog/rtl/lib/registers.v"
+     $script_dir/../../verilog/rtl/lib/registers.v          \
+     $script_dir/../../verilog/rtl/lib/ctech_cells.sv     \
+     "
 
 
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -95,6 +97,7 @@
 set ::env(FP_PDN_HWIDTH) 5
 
 set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 
 set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/pinmux/interactive.tcl b/openlane/pinmux/interactive.tcl
deleted file mode 100644
index b44b517..0000000
--- a/openlane/pinmux/interactive.tcl
+++ /dev/null
@@ -1,219 +0,0 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-package require openlane;
-
-
-proc run_placement_step {args} {
-    # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
-    # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
-    # set_def $pdndef
-    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
-        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
-    }
-
-    run_placement
-}
-
-proc run_cts_step {args} {
-    # set_def $::env(opendp_result_file_tag).def
-    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
-        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
-    }
-
-    run_cts
-    run_resizer_timing
-}
-
-proc run_routing_step {args} {
-    # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
-    # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
-    # set_def $resizerdef
-    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
-        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
-    }
-    run_routing
-}
-
-proc run_diode_insertion_2_5_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
-        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
-    }
-	if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
-		run_antenna_check
-		heal_antenna_violators; # modifies the routed DEF
-	}
-
-}
-
-proc run_power_pins_insertion_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
-        set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
-    }
-    if { $::env(LVS_INSERT_POWER_PINS) } {
-		write_powered_verilog
-		set_netlist $::env(lvs_result_file_tag).powered.v
-    }
-
-}
-
-proc run_lvs_step {{ lvs_enabled 1 }} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
-        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
-    }
-	if { $lvs_enabled } {
-		run_magic_spice_export
-		run_lvs; # requires run_magic_spice_export
-	}
-
-}
-
-proc run_drc_step {{ drc_enabled 1 }} {
-    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
-        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
-    }
-	if { $drc_enabled } {
-		run_magic_drc
-		run_klayout_drc
-	}
-}
-
-proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
-    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
-        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
-    }
-	if { $antenna_check_enabled } {
-		run_antenna_check
-	}
-}
-
-proc run_flow {args} {
-       set script_dir [file dirname [file normalize [info script]]]
-
-		set options {
-		{-design required}
-		{-save_path optional}
-		{-no_lvs optional}
-	    {-no_drc optional}
-	    {-no_antennacheck optional}
-	}
-	set flags {-save}
-	parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
-
-	prep {*}$args
-
-        set LVS_ENABLED 1
-        set DRC_ENABLED 0
-        set ANTENNACHECK_ENABLED 1
-
-        set steps [dict create "synthesis" {run_synthesis "" } \
-                "floorplan" {run_floorplan ""} \
-                "placement" {run_placement_step ""} \
-                "cts" {run_cts_step ""} \
-                "routing" {run_routing_step ""}\
-                "diode_insertion" {run_diode_insertion_2_5_step ""} \
-                "power_pins_insertion" {run_power_pins_insertion_step ""} \
-                "gds_magic" {run_magic ""} \
-                "gds_drc_klayout" {run_klayout ""} \
-                "gds_xor_klayout" {run_klayout_gds_xor ""} \
-                "lvs" "run_lvs_step $LVS_ENABLED" \
-                "drc" "run_drc_step $DRC_ENABLED" \
-                "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
-                "cvc" {run_lef_cvc}
-        ]
-
-       set_if_unset arg_values(-to) "cvc";
-
-       if {  [info exists ::env(CURRENT_STEP) ] } {
-           puts "\[INFO\]:Picking up where last execution left off"
-           puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
-       } else {
-           set ::env(CURRENT_STEP) "synthesis";
-       }
-       set_if_unset arg_values(-from) $::env(CURRENT_STEP);
-       set exe 0;
-       dict for {step_name step_exe} $steps {
-           if { [ string equal $arg_values(-from) $step_name ] } {
-               set exe 1;
-           }
-
-           if { $exe } {
-               # For when it fails
-               set ::env(CURRENT_STEP) $step_name
-               [lindex $step_exe 0] [lindex $step_exe 1] ;
-           }
-
-           if { [ string equal $arg_values(-to) $step_name ] } {
-               set exe 0:
-               break;
-           }
-
-       }
-
-       # for when it resumes
-       set steps_as_list [dict keys $steps]
-       set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
-       set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
-
-	if {  [info exists flags_map(-save) ] } {
-		if { ! [info exists arg_values(-save_path)] } {
-			set arg_values(-save_path) ""
-		}
-		save_views 	-lef_path $::env(magic_result_file_tag).lef \
-			-def_path $::env(CURRENT_DEF) \
-			-gds_path $::env(magic_result_file_tag).gds \
-			-mag_path $::env(magic_result_file_tag).mag \
-			-maglef_path $::env(magic_result_file_tag).lef.mag \
-			-spice_path $::env(magic_result_file_tag).spice \
-			-spef_path $::env(CURRENT_SPEF) \
-			-verilog_path $::env(CURRENT_NETLIST) \
-			-save_path $arg_values(-save_path) \
-			-tag $::env(RUN_TAG)
-	}
-
-
-	calc_total_runtime
-	save_state
-	generate_final_summary_report
-	
-	check_timing_violations
-
-	puts_success "Flow Completed Without Fatal Errors."
-
-}
-
-run_flow {*}$argv
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg
index 512813f..42c2cac 100644
--- a/openlane/pinmux/pin_order.cfg
+++ b/openlane/pinmux/pin_order.cfg
@@ -3,6 +3,16 @@
 
 #S
 h_reset_n             000 0 2
+cpu_core_rst_n\[1\]
+cpu_core_rst_n\[0\]
+cpu_intf_rst_n
+qspim_rst_n
+sspim_rst_n
+uart_rst_n
+i2cm_rst_n
+usb_rst_n 
+cfg_riscv_debug_sel\[1\]
+cfg_riscv_debug_sel\[0\]
 user_irq\[0\]
 user_irq\[1\]
 user_irq\[2\]
diff --git a/openlane/qspim/interactive.tcl b/openlane/qspim/interactive.tcl
deleted file mode 100644
index b44b517..0000000
--- a/openlane/qspim/interactive.tcl
+++ /dev/null
@@ -1,219 +0,0 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-package require openlane;
-
-
-proc run_placement_step {args} {
-    # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
-    # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
-    # set_def $pdndef
-    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
-        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
-    }
-
-    run_placement
-}
-
-proc run_cts_step {args} {
-    # set_def $::env(opendp_result_file_tag).def
-    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
-        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
-    }
-
-    run_cts
-    run_resizer_timing
-}
-
-proc run_routing_step {args} {
-    # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
-    # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
-    # set_def $resizerdef
-    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
-        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
-    }
-    run_routing
-}
-
-proc run_diode_insertion_2_5_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
-        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
-    }
-	if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
-		run_antenna_check
-		heal_antenna_violators; # modifies the routed DEF
-	}
-
-}
-
-proc run_power_pins_insertion_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
-        set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
-    }
-    if { $::env(LVS_INSERT_POWER_PINS) } {
-		write_powered_verilog
-		set_netlist $::env(lvs_result_file_tag).powered.v
-    }
-
-}
-
-proc run_lvs_step {{ lvs_enabled 1 }} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
-        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
-    }
-	if { $lvs_enabled } {
-		run_magic_spice_export
-		run_lvs; # requires run_magic_spice_export
-	}
-
-}
-
-proc run_drc_step {{ drc_enabled 1 }} {
-    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
-        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
-    }
-	if { $drc_enabled } {
-		run_magic_drc
-		run_klayout_drc
-	}
-}
-
-proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
-    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
-        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
-    }
-	if { $antenna_check_enabled } {
-		run_antenna_check
-	}
-}
-
-proc run_flow {args} {
-       set script_dir [file dirname [file normalize [info script]]]
-
-		set options {
-		{-design required}
-		{-save_path optional}
-		{-no_lvs optional}
-	    {-no_drc optional}
-	    {-no_antennacheck optional}
-	}
-	set flags {-save}
-	parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
-
-	prep {*}$args
-
-        set LVS_ENABLED 1
-        set DRC_ENABLED 0
-        set ANTENNACHECK_ENABLED 1
-
-        set steps [dict create "synthesis" {run_synthesis "" } \
-                "floorplan" {run_floorplan ""} \
-                "placement" {run_placement_step ""} \
-                "cts" {run_cts_step ""} \
-                "routing" {run_routing_step ""}\
-                "diode_insertion" {run_diode_insertion_2_5_step ""} \
-                "power_pins_insertion" {run_power_pins_insertion_step ""} \
-                "gds_magic" {run_magic ""} \
-                "gds_drc_klayout" {run_klayout ""} \
-                "gds_xor_klayout" {run_klayout_gds_xor ""} \
-                "lvs" "run_lvs_step $LVS_ENABLED" \
-                "drc" "run_drc_step $DRC_ENABLED" \
-                "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
-                "cvc" {run_lef_cvc}
-        ]
-
-       set_if_unset arg_values(-to) "cvc";
-
-       if {  [info exists ::env(CURRENT_STEP) ] } {
-           puts "\[INFO\]:Picking up where last execution left off"
-           puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
-       } else {
-           set ::env(CURRENT_STEP) "synthesis";
-       }
-       set_if_unset arg_values(-from) $::env(CURRENT_STEP);
-       set exe 0;
-       dict for {step_name step_exe} $steps {
-           if { [ string equal $arg_values(-from) $step_name ] } {
-               set exe 1;
-           }
-
-           if { $exe } {
-               # For when it fails
-               set ::env(CURRENT_STEP) $step_name
-               [lindex $step_exe 0] [lindex $step_exe 1] ;
-           }
-
-           if { [ string equal $arg_values(-to) $step_name ] } {
-               set exe 0:
-               break;
-           }
-
-       }
-
-       # for when it resumes
-       set steps_as_list [dict keys $steps]
-       set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
-       set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
-
-	if {  [info exists flags_map(-save) ] } {
-		if { ! [info exists arg_values(-save_path)] } {
-			set arg_values(-save_path) ""
-		}
-		save_views 	-lef_path $::env(magic_result_file_tag).lef \
-			-def_path $::env(CURRENT_DEF) \
-			-gds_path $::env(magic_result_file_tag).gds \
-			-mag_path $::env(magic_result_file_tag).mag \
-			-maglef_path $::env(magic_result_file_tag).lef.mag \
-			-spice_path $::env(magic_result_file_tag).spice \
-			-spef_path $::env(CURRENT_SPEF) \
-			-verilog_path $::env(CURRENT_NETLIST) \
-			-save_path $arg_values(-save_path) \
-			-tag $::env(RUN_TAG)
-	}
-
-
-	calc_total_runtime
-	save_state
-	generate_final_summary_report
-	
-	check_timing_violations
-
-	puts_success "Flow Completed Without Fatal Errors."
-
-}
-
-run_flow {*}$argv
diff --git a/openlane/qspim/base.sdc b/openlane/qspim_top/base.sdc
similarity index 75%
rename from openlane/qspim/base.sdc
rename to openlane/qspim_top/base.sdc
index b18259c..327d1f4 100644
--- a/openlane/qspim/base.sdc
+++ b/openlane/qspim_top/base.sdc
@@ -68,6 +68,12 @@
 set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[1]}]
 set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[2]}]
 set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[3]}]
+
+set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[0]}]
+set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[1]}]
+set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[2]}]
+set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[3]}]
+
 set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[0]}]
 set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[1]}]
 set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[2]}]
@@ -77,6 +83,12 @@
 set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[1]}]
 set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[2]}]
 set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[3]}]
+
+set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[0]}]
+set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[1]}]
+set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[2]}]
+set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[3]}]
+
 set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[0]}]
 set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[1]}]
 set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[2]}]
@@ -257,75 +269,13 @@
 set_max_delay  10.0000 -to [get_ports {spi_debug[8]}]
 set_max_delay  10.0000 -to [get_ports {spi_debug[9]}]
 
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[0]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[10]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[11]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[12]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[13]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[14]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[15]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[16]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[17]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[18]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[19]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[1]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[20]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[21]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[22]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[23]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[24]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[25]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[26]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[27]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[28]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[29]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[2]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[30]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[31]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[3]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[4]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[5]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[6]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[7]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[8]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[9]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}]
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}]
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}]
 
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[0]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[10]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[11]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[12]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[13]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[14]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[15]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[16]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[17]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[18]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[19]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[1]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[20]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[21]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[22]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[23]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[24]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[25]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[26]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[27]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[28]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[29]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[2]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[30]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[31]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[3]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[4]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[5]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[6]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[7]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[8]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[9]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}]
+set_output_delay -min -2.7500 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}]
+set_output_delay -min -2.7500 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[*]}]
+set_output_delay -min -2.7500 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}]
 ###############################################################################
 # Environment
 ###############################################################################
diff --git a/openlane/qspim/config.tcl b/openlane/qspim_top/config.tcl
similarity index 98%
rename from openlane/qspim/config.tcl
rename to openlane/qspim_top/config.tcl
index dd9596a..e2a3b24 100755
--- a/openlane/qspim/config.tcl
+++ b/openlane/qspim_top/config.tcl
@@ -94,6 +94,7 @@
 set ::env(FP_PDN_HWIDTH) 5
 
 set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
diff --git a/openlane/qspim/pdn.tcl b/openlane/qspim_top/pdn.tcl
similarity index 100%
rename from openlane/qspim/pdn.tcl
rename to openlane/qspim_top/pdn.tcl
diff --git a/openlane/qspim/pin_order.cfg b/openlane/qspim_top/pin_order.cfg
similarity index 100%
rename from openlane/qspim/pin_order.cfg
rename to openlane/qspim_top/pin_order.cfg
diff --git a/openlane/qspim/sta.tcl b/openlane/qspim_top/sta.tcl
similarity index 100%
rename from openlane/qspim/sta.tcl
rename to openlane/qspim_top/sta.tcl
diff --git a/openlane/uart_i2cm_usb_spi/interactive.tcl b/openlane/uart_i2cm_usb_spi/interactive.tcl
deleted file mode 100644
index b44b517..0000000
--- a/openlane/uart_i2cm_usb_spi/interactive.tcl
+++ /dev/null
@@ -1,219 +0,0 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-package require openlane;
-
-
-proc run_placement_step {args} {
-    # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
-    # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
-    # set_def $pdndef
-    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
-        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
-    }
-
-    run_placement
-}
-
-proc run_cts_step {args} {
-    # set_def $::env(opendp_result_file_tag).def
-    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
-        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
-    }
-
-    run_cts
-    run_resizer_timing
-}
-
-proc run_routing_step {args} {
-    # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
-    # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
-    # set_def $resizerdef
-    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
-        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
-    }
-    run_routing
-}
-
-proc run_diode_insertion_2_5_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
-        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
-    }
-	if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
-		run_antenna_check
-		heal_antenna_violators; # modifies the routed DEF
-	}
-
-}
-
-proc run_power_pins_insertion_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
-        set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
-    }
-    if { $::env(LVS_INSERT_POWER_PINS) } {
-		write_powered_verilog
-		set_netlist $::env(lvs_result_file_tag).powered.v
-    }
-
-}
-
-proc run_lvs_step {{ lvs_enabled 1 }} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
-        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
-    }
-	if { $lvs_enabled } {
-		run_magic_spice_export
-		run_lvs; # requires run_magic_spice_export
-	}
-
-}
-
-proc run_drc_step {{ drc_enabled 1 }} {
-    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
-        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
-    }
-	if { $drc_enabled } {
-		run_magic_drc
-		run_klayout_drc
-	}
-}
-
-proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
-    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
-        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
-    }
-	if { $antenna_check_enabled } {
-		run_antenna_check
-	}
-}
-
-proc run_flow {args} {
-       set script_dir [file dirname [file normalize [info script]]]
-
-		set options {
-		{-design required}
-		{-save_path optional}
-		{-no_lvs optional}
-	    {-no_drc optional}
-	    {-no_antennacheck optional}
-	}
-	set flags {-save}
-	parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
-
-	prep {*}$args
-
-        set LVS_ENABLED 1
-        set DRC_ENABLED 0
-        set ANTENNACHECK_ENABLED 1
-
-        set steps [dict create "synthesis" {run_synthesis "" } \
-                "floorplan" {run_floorplan ""} \
-                "placement" {run_placement_step ""} \
-                "cts" {run_cts_step ""} \
-                "routing" {run_routing_step ""}\
-                "diode_insertion" {run_diode_insertion_2_5_step ""} \
-                "power_pins_insertion" {run_power_pins_insertion_step ""} \
-                "gds_magic" {run_magic ""} \
-                "gds_drc_klayout" {run_klayout ""} \
-                "gds_xor_klayout" {run_klayout_gds_xor ""} \
-                "lvs" "run_lvs_step $LVS_ENABLED" \
-                "drc" "run_drc_step $DRC_ENABLED" \
-                "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
-                "cvc" {run_lef_cvc}
-        ]
-
-       set_if_unset arg_values(-to) "cvc";
-
-       if {  [info exists ::env(CURRENT_STEP) ] } {
-           puts "\[INFO\]:Picking up where last execution left off"
-           puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
-       } else {
-           set ::env(CURRENT_STEP) "synthesis";
-       }
-       set_if_unset arg_values(-from) $::env(CURRENT_STEP);
-       set exe 0;
-       dict for {step_name step_exe} $steps {
-           if { [ string equal $arg_values(-from) $step_name ] } {
-               set exe 1;
-           }
-
-           if { $exe } {
-               # For when it fails
-               set ::env(CURRENT_STEP) $step_name
-               [lindex $step_exe 0] [lindex $step_exe 1] ;
-           }
-
-           if { [ string equal $arg_values(-to) $step_name ] } {
-               set exe 0:
-               break;
-           }
-
-       }
-
-       # for when it resumes
-       set steps_as_list [dict keys $steps]
-       set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
-       set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
-
-	if {  [info exists flags_map(-save) ] } {
-		if { ! [info exists arg_values(-save_path)] } {
-			set arg_values(-save_path) ""
-		}
-		save_views 	-lef_path $::env(magic_result_file_tag).lef \
-			-def_path $::env(CURRENT_DEF) \
-			-gds_path $::env(magic_result_file_tag).gds \
-			-mag_path $::env(magic_result_file_tag).mag \
-			-maglef_path $::env(magic_result_file_tag).lef.mag \
-			-spice_path $::env(magic_result_file_tag).spice \
-			-spef_path $::env(CURRENT_SPEF) \
-			-verilog_path $::env(CURRENT_NETLIST) \
-			-save_path $arg_values(-save_path) \
-			-tag $::env(RUN_TAG)
-	}
-
-
-	calc_total_runtime
-	save_state
-	generate_final_summary_report
-	
-	check_timing_violations
-
-	puts_success "Flow Completed Without Fatal Errors."
-
-}
-
-run_flow {*}$argv
diff --git a/openlane/uart_i2cm_usb_spi/base.sdc b/openlane/uart_i2cm_usb_spi_top/base.sdc
similarity index 83%
rename from openlane/uart_i2cm_usb_spi/base.sdc
rename to openlane/uart_i2cm_usb_spi_top/base.sdc
index bee06d8..36725cd 100644
--- a/openlane/uart_i2cm_usb_spi/base.sdc
+++ b/openlane/uart_i2cm_usb_spi_top/base.sdc
@@ -52,11 +52,17 @@
 set_input_delay  -min 2.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_wr}]
 
 
-set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
-set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -max 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}]
 
-set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
-set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}]
+set_output_delay -min -2.7500 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -min -2.7500 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}]
+
+set_multicycle_path -setup  -from [get_ports {reg_addr[*]}] -to [get_ports {reg_ack}] 2
+set_multicycle_path -setup  -from [get_ports {reg_addr[*]}] -to [get_ports {reg_rdata[*]}] 2
+
+set_multicycle_path -hold  -from [get_ports {reg_addr[*]}] -to [get_ports {reg_ack}] 1
+set_multicycle_path -hold  -from [get_ports {reg_addr[*]}] -to [get_ports {reg_rdata[*]}] 1
 
 ###############################################################################
 # Environment
diff --git a/openlane/uart_i2cm_usb_spi/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl
similarity index 96%
rename from openlane/uart_i2cm_usb_spi/config.tcl
rename to openlane/uart_i2cm_usb_spi_top/config.tcl
index fa19eff..48ac117 100644
--- a/openlane/uart_i2cm_usb_spi/config.tcl
+++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -115,9 +115,13 @@
 set ::env(FP_PDN_HWIDTH) 5
 
 set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
+
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"
 set ::env(QUIT_ON_LVS_ERROR) "0"
diff --git a/openlane/uart_i2cm_usb_spi/pdn.tcl b/openlane/uart_i2cm_usb_spi_top/pdn.tcl
similarity index 100%
rename from openlane/uart_i2cm_usb_spi/pdn.tcl
rename to openlane/uart_i2cm_usb_spi_top/pdn.tcl
diff --git a/openlane/uart_i2cm_usb_spi/pin_order.cfg b/openlane/uart_i2cm_usb_spi_top/pin_order.cfg
similarity index 100%
rename from openlane/uart_i2cm_usb_spi/pin_order.cfg
rename to openlane/uart_i2cm_usb_spi_top/pin_order.cfg
diff --git a/openlane/uart_i2cm_usb_spi/sta.tcl b/openlane/uart_i2cm_usb_spi_top/sta.tcl
similarity index 100%
rename from openlane/uart_i2cm_usb_spi/sta.tcl
rename to openlane/uart_i2cm_usb_spi_top/sta.tcl
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 8d8c8e0..954a8a9 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -66,30 +66,30 @@
 
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
-        $proj_dir/../../verilog/gl/qspim.v \
+        $proj_dir/../../verilog/gl/qspim_top.v \
         $proj_dir/../../verilog/gl/wb_interconnect.v \
         $proj_dir/../../verilog/gl/pinmux.v     \
-        $proj_dir/../../verilog/gl/uart_i2cm_usb_spi.v     \
+        $proj_dir/../../verilog/gl/uart_i2c_usb_spi_top.v     \
 	$proj_dir/../../verilog/gl/wb_host.v \
 	$proj_dir/../../verilog/gl/yifive.v \
 	$proj_dir/../../verilog/gl/DFFRAM.v \
 	"
 
 set ::env(EXTRA_LEFS) "\
-	$lef_root/qspim.lef \
+	$lef_root/qspim_top.lef \
 	$lef_root/pinmux.lef \
 	$lef_root/wb_interconnect.lef \
-	$lef_root/uart_i2cm_usb_spi.lef \
+	$lef_root/uart_i2c_usb_spi_top.lef \
 	$lef_root/wb_host.lef \
 	$lef_root/yifive.lef \
 	$lef_root/DFFRAM.lef \
 	"
 
 set ::env(EXTRA_GDS_FILES) "\
-	$gds_root/qspim.gds \
+	$gds_root/qspim_top.gds \
 	$gds_root/pinmux.gds \
 	$gds_root/wb_interconnect.gds \
-	$gds_root/uart_i2cm_usb_spi.gds \
+	$gds_root/uart_i2c_usb_spi_top.gds \
 	$gds_root/wb_host.gds \
 	$gds_root/yifive.gds \
 	$gds_root/DFFRAM.gds \
@@ -99,7 +99,8 @@
 
 #set ::env(VERILOG_INCLUDE_DIRS) [glob $proj_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
 
-set ::env(GLB_RT_MAXLAYER) 5
+set ::env(GLB_RT_MAXLAYER) 6
+set ::env(RT_MAX_LAYER) {met5}
 
 set ::env(FP_PDN_CHECK_NODES) 0
 
@@ -116,12 +117,12 @@
 set ::env(GND_PIN) "vssd1"
 
 set ::env(GLB_RT_OBS) " met5  0    0    2920   3520, \
-	                met4  125  950   675   1640, \
-	                met4  125  1800  675   2540, \
-	                met4  125  100   675    840, \
-	                met4  850  100  1400    840, \
-	                met4  325  2650  875  3400, \
-	                met4  1050 2650 1600  3400 \
+	                met4  125  1750  675   2490, \
+	                met4  125  2645  675   3385, \
+	                met4  125  900   675   1640, \
+	                met4  850  110  1400    850, \
+	                met4  850  2645 1400   3385, \
+	                met4  1575 2645 2125   3385 \
 	              "
                       
 set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0"
@@ -160,11 +161,11 @@
 set ::env(CLOCK_TREE_SYNTH) 0
 
 set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_TR_DRC) "1"
 set ::env(QUIT_ON_MAGIC_DRC) "1"
 set ::env(QUIT_ON_NEGATIVE_WNS) "0"
 set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
-set ::env(QUIT_ON_TR_DRC) "0"
 
 set ::env(FP_PDN_IRDROP) "0"
 set ::env(FP_PDN_HORIZONTAL_HALO) "10"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 6f35c2f..8c4c88a 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,15 +1,15 @@
-u_qspi_master           2225             700           N
-u_uart_i2c_usb_spi      2225            1400           N
-u_pinmux                2225            2300           N
+u_qspi_master           2275             710           N
+u_uart_i2c_usb_spi      2275            1410           N
+u_pinmux                2275            2250           N
 
-u_tcm_1KB_mem0          125             945            N 
-u_tcm_1KB_mem1          125             1790           N 
-u_riscv_top	        850	        945	       N
-u_icache_1KB_mem0       125             100            N
-u_icache_1KB_mem1       850             100            N
+u_tcm_1KB_mem0          125             1750           N 
+u_tcm_1KB_mem1          125             2645           N 
+u_riscv_top	        850	        955	       N
+u_icache_1KB_mem0       125             900            N
+u_icache_1KB_mem1       850             110            N
 
-u_dcache_1KB_mem0       325             2635           N
-u_dcache_1KB_mem1       1050            2635           N
+u_dcache_1KB_mem0       850             2645           N
+u_dcache_1KB_mem1       1575            2645           N
 
-u_intercon              1850            700            N
-u_wb_host               1650            200            N
+u_intercon              1850            710            N
+u_wb_host               1750            150            N
diff --git a/openlane/wb_host/base.sdc b/openlane/wb_host/base.sdc
index ee8410c..9d9cc79 100644
--- a/openlane/wb_host/base.sdc
+++ b/openlane/wb_host/base.sdc
@@ -71,19 +71,19 @@
 set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_ack_i}]
 set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[*]}]
 
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
+set_output_delay -max 3.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
+set_output_delay -max 3.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay -max 3.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 3.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
+set_output_delay -max 3.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
+set_output_delay -max 3.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
 
-set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
-set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
-set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
-set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
-set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
-set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
+set_output_delay -min -1.7500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
+set_output_delay -min -1.7500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay -min -1.7500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
+set_output_delay -min -1.7500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
+set_output_delay -min -1.7500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
+set_output_delay -min -1.7500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
 
 ###############################################################################
 # Environment
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index ff38b49..1dabc40 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -75,7 +75,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 350 400"
+set ::env(DIE_AREA) "0 0 350 425"
 
 
 # If you're going to use multiple power domains, then keep this disabled.
@@ -98,6 +98,7 @@
 set ::env(FP_PDN_HWIDTH) 5
 
 set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 
 set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/wb_host/interactive.tcl b/openlane/wb_host/interactive.tcl
deleted file mode 100644
index f59586f..0000000
--- a/openlane/wb_host/interactive.tcl
+++ /dev/null
@@ -1,219 +0,0 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-package require openlane;
-
-
-proc run_placement_step {args} {
-    # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
-    # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
-    # set_def $pdndef
-    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
-        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
-    }
-
-    run_placement
-}
-
-proc run_cts_step {args} {
-    # set_def $::env(opendp_result_file_tag).def
-    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
-        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
-    }
-
-    run_cts
-    run_resizer_timing
-}
-
-proc run_routing_step {args} {
-    # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
-    # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
-    # set_def $resizerdef
-    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
-        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
-    }
-    run_routing
-}
-
-proc run_diode_insertion_2_5_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
-        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
-    }
-	if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
-		run_antenna_check
-		heal_antenna_violators; # modifies the routed DEF
-	}
-
-}
-
-proc run_power_pins_insertion_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
-        set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
-    }
-    if { $::env(LVS_INSERT_POWER_PINS) } {
-		write_powered_verilog
-		set_netlist $::env(lvs_result_file_tag).powered.v
-    }
-
-}
-
-proc run_lvs_step {{ lvs_enabled 1 }} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
-        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
-    }
-	if { $lvs_enabled } {
-		run_magic_spice_export
-		run_lvs; # requires run_magic_spice_export
-	}
-
-}
-
-proc run_drc_step {{ drc_enabled 1 }} {
-    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
-        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
-    }
-	if { $drc_enabled } {
-		run_magic_drc
-		run_klayout_drc
-	}
-}
-
-proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
-    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
-        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
-    }
-	if { $antenna_check_enabled } {
-		run_antenna_check
-	}
-}
-
-proc run_flow {args} {
-       set script_dir [file dirname [file normalize [info script]]]
-
-		set options {
-		{-design required}
-		{-save_path optional}
-		{-no_lvs optional}
-	    {-no_drc optional}
-	    {-no_antennacheck optional}
-	}
-	set flags {-save}
-	parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
-
-	prep {*}$args
-
-        set LVS_ENABLED 1
-        set DRC_ENABLED 1
-        set ANTENNACHECK_ENABLED 1
-
-        set steps [dict create "synthesis" {run_synthesis "" } \
-                "floorplan" {run_floorplan ""} \
-                "placement" {run_placement_step ""} \
-                "cts" {run_cts_step ""} \
-                "routing" {run_routing_step ""}\
-                "diode_insertion" {run_diode_insertion_2_5_step ""} \
-                "power_pins_insertion" {run_power_pins_insertion_step ""} \
-                "gds_magic" {run_magic ""} \
-                "gds_drc_klayout" {run_klayout ""} \
-                "gds_xor_klayout" {run_klayout_gds_xor ""} \
-                "lvs" "run_lvs_step $LVS_ENABLED" \
-                "drc" "run_drc_step $DRC_ENABLED" \
-                "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
-                "cvc" {run_lef_cvc}
-        ]
-
-       set_if_unset arg_values(-to) "cvc";
-
-       if {  [info exists ::env(CURRENT_STEP) ] } {
-           puts "\[INFO\]:Picking up where last execution left off"
-           puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
-       } else {
-           set ::env(CURRENT_STEP) "synthesis";
-       }
-       set_if_unset arg_values(-from) $::env(CURRENT_STEP);
-       set exe 0;
-       dict for {step_name step_exe} $steps {
-           if { [ string equal $arg_values(-from) $step_name ] } {
-               set exe 1;
-           }
-
-           if { $exe } {
-               # For when it fails
-               set ::env(CURRENT_STEP) $step_name
-               [lindex $step_exe 0] [lindex $step_exe 1] ;
-           }
-
-           if { [ string equal $arg_values(-to) $step_name ] } {
-               set exe 0:
-               break;
-           }
-
-       }
-
-       # for when it resumes
-       set steps_as_list [dict keys $steps]
-       set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
-       set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
-
-	if {  [info exists flags_map(-save) ] } {
-		if { ! [info exists arg_values(-save_path)] } {
-			set arg_values(-save_path) ""
-		}
-		save_views 	-lef_path $::env(magic_result_file_tag).lef \
-			-def_path $::env(CURRENT_DEF) \
-			-gds_path $::env(magic_result_file_tag).gds \
-			-mag_path $::env(magic_result_file_tag).mag \
-			-maglef_path $::env(magic_result_file_tag).lef.mag \
-			-spice_path $::env(magic_result_file_tag).spice \
-			-spef_path $::env(CURRENT_SPEF) \
-			-verilog_path $::env(CURRENT_NETLIST) \
-			-save_path $arg_values(-save_path) \
-			-tag $::env(RUN_TAG)
-	}
-
-
-	calc_total_runtime
-	save_state
-	generate_final_summary_report
-	
-	check_timing_violations
-
-	puts_success "Flow Completed Without Fatal Errors."
-
-}
-
-run_flow {*}$argv
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 540187b..3448c6c 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -4,13 +4,7 @@
 
 
 #W
-sspim_rst_n      0000 0 4
-qspim_rst_n
-uart_rst_n
-i2cm_rst_n
-usb_rst_n
-bist_rst_n
-usb_clk
+usb_clk          0000 0 4
 cfg_clk_ctrl1\[31\]
 cfg_clk_ctrl1\[30\]
 cfg_clk_ctrl1\[29\]
@@ -30,7 +24,6 @@
 
 cpu_clk               0100 0 2
 rtc_clk
-cpu_rst_n
 
 
 
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index bc25fd0..d0ccab1 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -44,6 +44,7 @@
         $script_dir/../../verilog/rtl/lib/sync_wbb.sv                \
         $script_dir/../../verilog/rtl/lib/sync_fifo2.sv                \
         $script_dir/../../verilog/rtl/wb_interconnect/src/wb_arb.sv     \
+        $script_dir/../../verilog/rtl/wb_interconnect/src/wb_slave_port.sv  \
         $script_dir/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv  \
 	"
 
@@ -69,7 +70,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 200 2300"
+set ::env(DIE_AREA) "0 0 320 1800"
 
 
 # If you're going to use multiple power domains, then keep this disabled.
@@ -77,17 +78,11 @@
 
 #set ::env(PDN_CFG) $script_dir/pdn.tcl
 
-## PDN
-set ::env(FP_PDN_CORE_RING) 0
-set ::env(FP_PDN_VPITCH) 120
-set ::env(FP_PDN_HPITCH) 120
-
-set ::env(FP_PDN_VWIDTH) 1.6
-set ::env(FP_PDN_CORE_RING_VWIDTH) 1.6
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.30"
+set ::env(PL_TARGET_DENSITY) "0.20"
+set ::env(CELL_PAD) "10"
 
 # helps in anteena fix
 set ::env(USE_ARC_ANTENNA_CHECK) "0"
@@ -118,8 +113,8 @@
 set ::env(GLB_RT_ALLOW_CONGESTION) 0
 set ::env(GLB_RT_OVERFLOW_ITERS) 200
 
-set ::env(GLB_RT_MINLAYER) 2
-set ::env(GLB_RT_MAXLAYER) 6
+set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
 
 
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
diff --git a/openlane/wb_interconnect/interactive.tcl b/openlane/wb_interconnect/interactive.tcl
deleted file mode 100644
index a180a5c..0000000
--- a/openlane/wb_interconnect/interactive.tcl
+++ /dev/null
@@ -1,403 +0,0 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-package require openlane;
-
-
-proc run_placement_step {args} {
-    # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
-    # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
-    # set_def $pdndef
-    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
-        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
-    }
-
-    run_placement
-}
-
-proc run_cts_step {args} {
-    # set_def $::env(opendp_result_file_tag).def
-    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
-        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
-    }
-
-    run_cts
-    run_resizer_timing
-}
-
-proc run_routing_step {args} {
-    # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
-    # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
-    # set_def $resizerdef
-    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
-        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
-    }
-    run_routing
-}
-
-proc run_diode_insertion_2_5_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
-        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
-    }
-	if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
-		run_antenna_check
-		heal_antenna_violators; # modifies the routed DEF
-	}
-
-}
-
-proc run_power_pins_insertion_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
-        set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
-    }
-    if { $::env(LVS_INSERT_POWER_PINS) } {
-		write_powered_verilog
-		set_netlist $::env(lvs_result_file_tag).powered.v
-    }
-
-}
-
-proc run_lvs_step {{ lvs_enabled 1 }} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
-        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
-    }
-	if { $lvs_enabled } {
-		run_magic_spice_export
-		run_lvs; # requires run_magic_spice_export
-	}
-
-}
-
-proc run_drc_step {{ drc_enabled 1 }} {
-    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
-        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
-    }
-	if { $drc_enabled } {
-		run_magic_drc
-		run_klayout_drc
-	}
-}
-
-proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
-    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
-        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
-    }
-	if { $antenna_check_enabled } {
-		run_antenna_check
-	}
-}
-
-proc gen_pdn {args} {
-    puts_info "Generating PDN..."
-    TIMER::timer_start
-	
-    set ::env(SAVE_DEF) [index_file $::env(pdn_tmp_file_tag).def]
-    set ::env(PGA_RPT_FILE) [index_file $::env(pdn_report_file_tag).pga.rpt]
-
-    try_catch $::env(OPENROAD_BIN) -exit $::env(SCRIPTS_DIR)/openroad/pdn.tcl \
-	|& tee $::env(TERMINAL_OUTPUT) [index_file $::env(pdn_log_file_tag).log 0]
-
-
-    TIMER::timer_stop
-    exec echo "[TIMER::get_runtime]" >> [index_file $::env(pdn_log_file_tag)_runtime.txt 0]
-
-	quit_on_unconnected_pdn_nodes
-
-    set_def $::env(SAVE_DEF)
-}
-
-proc run_power_grid_generation {args} {
-	if { [info exists ::env(VDD_NETS)] || [info exists ::env(GND_NETS)] } {
-		# they both must exist and be equal in length
-		# current assumption: they cannot have a common ground
-		if { ! [info exists ::env(VDD_NETS)] || ! [info exists ::env(GND_NETS)] } {
-			puts_err "VDD_NETS and GND_NETS must *both* either be defined or undefined"
-			return -code error
-		}
-		# standard cell power and ground nets are assumed to be the first net 
-		set ::env(VDD_PIN) [lindex $::env(VDD_NETS) 0]
-		set ::env(GND_PIN) [lindex $::env(GND_NETS) 0]
-	} elseif { [info exists ::env(SYNTH_USE_PG_PINS_DEFINES)] } {
-		set ::env(VDD_NETS) [list]
-		set ::env(GND_NETS) [list]
-		# get the pins that are in $yosys_tmp_file_tag.pg_define.v
-		# that are not in $yosys_result_file_tag.v
-		#
-		set full_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_tmp_file_tag).pg_define.v]
-		puts_info $full_pins
-
-		set non_pg_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_result_file_tag).v]
-		puts_info $non_pg_pins
-
-		# assumes the pins are ordered correctly (e.g., vdd1, vss1, vcc1, vss1, ...)
-		foreach {vdd gnd} $full_pins {
-			if { $vdd ne "" && $vdd ni $non_pg_pins } {
-				lappend ::env(VDD_NETS) $vdd
-			}
-			if { $gnd ne "" && $gnd ni $non_pg_pins } {
-				lappend ::env(GND_NETS) $gnd
-			}
-		}
-	} else {
-		set ::env(VDD_NETS) $::env(VDD_PIN)
-		set ::env(GND_NETS) $::env(GND_PIN)
-	}
-
-	puts_info "Power planning the following nets"
-	puts_info "Power: $::env(VDD_NETS)"
-	puts_info "Ground: $::env(GND_NETS)"
-
-	if { [llength $::env(VDD_NETS)] != [llength $::env(GND_NETS)] } {
-		puts_err "VDD_NETS and GND_NETS must be of equal lengths"
-		return -code error
-	}
-
-	# internal macros power connections 
-	if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} {
-		set macro_hooks [dict create]
-		set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
-		foreach pdn_hook $pdn_hooks {
-			set instance_name [lindex $pdn_hook 0]
-			set power_net [lindex $pdn_hook 1]
-			set ground_net [lindex $pdn_hook 2]
-			dict append macro_hooks $instance_name [subst {$power_net $ground_net}]
-		        set power_net_indx [lsearch $::env(VDD_NETS) $power_net]
-		        set ground_net_indx [lsearch $::env(GND_NETS) $ground_net]
-
-		        # make sure that the specified power domains exist.
-		        if { $power_net_indx == -1  || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } {
-		        	puts_err "Can't find $power_net and $ground_net domain. \
-		        	Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)." 
-		        } 
-		}
-		
-	}
-	
-	# generate multiple power grids per pair of (VDD,GND)
-	# offseted by WIDTH + SPACING
-	foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
-		set ::env(VDD_NET) $vdd
-		set ::env(GND_NET) $gnd
-	        puts_info "Connecting Power: $vdd & gnd to All internal macros."
-
-		# internal macros power connections
-		set ::env(FP_PDN_MACROS) ""
-		if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 } {
-			# if macros connections to power are explicitly set
-			# default behavoir macro pins will be connected to the first power domain
-			if { [info exists ::env(FP_PDN_MACRO_HOOKS)] } {
-				set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
-				foreach {instance_name hooks} $macro_hooks {
-					set power [lindex $hooks 0]
-					set ground [lindex $hooks 1]			 
-					if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } {
-						set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
-						puts_info "Connecting $instance_name to $power and $ground nets."
-						lappend ::env(FP_PDN_MACROS) $instance_name
-					}
-				}
-			} 
-		} else {
-			puts_warn "All internal macros will not be connected to power $vdd & $gnd."
-		}
-		
-		gen_pdn
-
-		set ::env(FP_PDN_ENABLE_RAILS) 0
-		set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
-
-		# allow failure until open_pdks is up to date...
-		catch {set ::env(FP_PDN_VOFFSET) [expr $::env(FP_PDN_VOFFSET)+$::env(FP_PDN_VWIDTH)+$::env(FP_PDN_VSPACING)]}
-		catch {set ::env(FP_PDN_HOFFSET) [expr $::env(FP_PDN_HOFFSET)+$::env(FP_PDN_HWIDTH)+$::env(FP_PDN_HSPACING)]}
-
-		catch {set ::env(FP_PDN_CORE_RING_VOFFSET) \
-			[expr $::env(FP_PDN_CORE_RING_VOFFSET)\
-			+2*($::env(FP_PDN_CORE_RING_VWIDTH)\
-			+max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
-		catch {set ::env(FP_PDN_CORE_RING_HOFFSET) [expr $::env(FP_PDN_CORE_RING_HOFFSET)\
-			+2*($::env(FP_PDN_CORE_RING_HWIDTH)+\
-			max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
-
-		puts "FP_PDN_VOFFSET: $::env(FP_PDN_VOFFSET)"
-		puts "FP_PDN_HOFFSET: $::env(FP_PDN_VOFFSET)"
-		puts "FP_PDN_CORE_RING_VOFFSET: $::env(FP_PDN_CORE_RING_VOFFSET)"
-		puts "FP_PDN_CORE_RING_HOFFSET: $::env(FP_PDN_CORE_RING_HOFFSET)"
-	}
-	set ::env(FP_PDN_ENABLE_RAILS) 1
-}
-
-
-proc run_floorplan {args} {
-		puts_info "Running Floorplanning..."
-		# |----------------------------------------------------|
-		# |----------------   2. FLOORPLAN   ------------------|
-		# |----------------------------------------------------|
-		#
-		# intial fp
-		init_floorplan
-
-
-		# place io
-		if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
-				place_io_ol
-		} else {
-			if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
-				place_io
-				global_placement_or
-				place_contextualized_io \
-					-lef $::env(FP_CONTEXT_LEF) \
-					-def $::env(FP_CONTEXT_DEF)
-			} else {
-				place_io
-			}
-		}
-
-		apply_def_template
-
-		if { [info exist ::env(EXTRA_LEFS)] } {
-			if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
-				file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(TMP_DIR)/macro_placement.cfg
-				manual_macro_placement f
-			} else {
-				global_placement_or
-				basic_macro_placement
-			}
-		}
-
-		# tapcell
-		tap_decap_or
-		scrot_klayout -layout $::env(CURRENT_DEF)
-		# power grid generation
-		run_power_grid_generation
-}
-
-proc run_flow {args} {
-       set script_dir [file dirname [file normalize [info script]]]
-
-		set options {
-		{-design required}
-		{-save_path optional}
-		{-no_lvs optional}
-	    {-no_drc optional}
-	    {-no_antennacheck optional}
-	}
-	set flags {-save}
-	parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
-
-	prep {*}$args
-
-        set LVS_ENABLED 1
-        set DRC_ENABLED 0
-        set ANTENNACHECK_ENABLED 1
-
-        set steps [dict create "synthesis" {run_synthesis "" } \
-                "floorplan" {run_floorplan ""} \
-                "placement" {run_placement_step ""} \
-                "cts" {run_cts_step ""} \
-                "routing" {run_routing_step ""}\
-                "diode_insertion" {run_diode_insertion_2_5_step ""} \
-                "power_pins_insertion" {run_power_pins_insertion_step ""} \
-                "gds_magic" {run_magic ""} \
-                "gds_drc_klayout" {run_klayout ""} \
-                "gds_xor_klayout" {run_klayout_gds_xor ""} \
-                "lvs" "run_lvs_step $LVS_ENABLED" \
-                "drc" "run_drc_step $DRC_ENABLED" \
-                "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
-                "cvc" {run_lef_cvc}
-        ]
-
-       set_if_unset arg_values(-to) "cvc";
-
-       if {  [info exists ::env(CURRENT_STEP) ] } {
-           puts "\[INFO\]:Picking up where last execution left off"
-           puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
-       } else {
-           set ::env(CURRENT_STEP) "synthesis";
-       }
-       set_if_unset arg_values(-from) $::env(CURRENT_STEP);
-       set exe 0;
-       dict for {step_name step_exe} $steps {
-           if { [ string equal $arg_values(-from) $step_name ] } {
-               set exe 1;
-           }
-
-           if { $exe } {
-               # For when it fails
-               set ::env(CURRENT_STEP) $step_name
-               [lindex $step_exe 0] [lindex $step_exe 1] ;
-           }
-
-           if { [ string equal $arg_values(-to) $step_name ] } {
-               set exe 0:
-               break;
-           }
-
-       }
-
-       # for when it resumes
-       set steps_as_list [dict keys $steps]
-       set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
-       set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
-
-	if {  [info exists flags_map(-save) ] } {
-		if { ! [info exists arg_values(-save_path)] } {
-			set arg_values(-save_path) ""
-		}
-		save_views 	-lef_path $::env(magic_result_file_tag).lef \
-			-def_path $::env(CURRENT_DEF) \
-			-gds_path $::env(magic_result_file_tag).gds \
-			-mag_path $::env(magic_result_file_tag).mag \
-			-maglef_path $::env(magic_result_file_tag).lef.mag \
-			-spice_path $::env(magic_result_file_tag).spice \
-			-spef_path $::env(CURRENT_SPEF) \
-			-verilog_path $::env(CURRENT_NETLIST) \
-			-save_path $arg_values(-save_path) \
-			-tag $::env(RUN_TAG)
-	}
-
-
-	calc_total_runtime
-	save_state
-	generate_final_summary_report
-	
-	check_timing_violations
-
-	puts_success "Flow Completed Without Fatal Errors."
-
-}
-
-run_flow {*}$argv
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index ae3e4b5..e722a83 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -732,7 +732,7 @@
 s1_wbd_ack_i        
 s1_wbd_cyc_o  
 
-ch_data_in\[68\]  1600 0 2  
+ch_data_in\[68\]  1400 0 2  
 ch_data_in\[67\]
 ch_data_in\[66\]
 ch_data_in\[65\]
@@ -788,7 +788,7 @@
 ch_data_out\[12\]
 ch_clk_out\[3\]
 
-s2_wbd_stb_o         1800 0 2
+s2_wbd_stb_o         1500 0 2
 s2_wbd_we_o         
 s2_wbd_adr_o\[7\]   
 s2_wbd_adr_o\[6\]   
diff --git a/openlane/yifive/config.tcl b/openlane/yifive/config.tcl
index c0a0db0..dc97db9 100755
--- a/openlane/yifive/config.tcl
+++ b/openlane/yifive/config.tcl
@@ -106,7 +106,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) [list 0.0 0.0 825.0 1550.0]
+set ::env(DIE_AREA) [list 0.0 0.0 815.0 1540.0]
 
 
 # If you're going to use multiple power domains, then keep this disabled.
@@ -116,7 +116,7 @@
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.34"
+set ::env(PL_TARGET_DENSITY) "0.32"
 set ::env(FP_CORE_UTIL) "50"
 
 
@@ -125,6 +125,7 @@
 
 
 set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
@@ -133,7 +134,16 @@
 set ::env(QUIT_ON_MAGIC_DRC) "1"
 set ::env(QUIT_ON_LVS_ERROR) "0"
 set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
+set ::env(QUIT_ON_SETUP_VIOLATIONS) "0"
+set ::env(QUIT_ON_HOLD_VIOLATIONS) "0"
+set ::env(QUIT_ON_ILLEGAL_OVERLAPS) "1"
+
+
+
+
+
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) "1"
 
 #Need to cross-check why global timing opimization creating setup vio with hugh hold fix
-set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1"
 
diff --git a/openlane/yifive/interactive.tcl b/openlane/yifive/interactive.tcl
deleted file mode 100644
index b44b517..0000000
--- a/openlane/yifive/interactive.tcl
+++ /dev/null
@@ -1,219 +0,0 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-package require openlane;
-
-
-proc run_placement_step {args} {
-    # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
-    # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
-    # set_def $pdndef
-    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
-        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
-    }
-
-    run_placement
-}
-
-proc run_cts_step {args} {
-    # set_def $::env(opendp_result_file_tag).def
-    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
-        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
-    }
-
-    run_cts
-    run_resizer_timing
-}
-
-proc run_routing_step {args} {
-    # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
-    # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
-    # set_def $resizerdef
-    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
-        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
-    }
-    run_routing
-}
-
-proc run_diode_insertion_2_5_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
-        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
-    }
-	if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
-		run_antenna_check
-		heal_antenna_violators; # modifies the routed DEF
-	}
-
-}
-
-proc run_power_pins_insertion_step {args} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
-        set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
-    }
-    if { $::env(LVS_INSERT_POWER_PINS) } {
-		write_powered_verilog
-		set_netlist $::env(lvs_result_file_tag).powered.v
-    }
-
-}
-
-proc run_lvs_step {{ lvs_enabled 1 }} {
-    # set_def $::env(tritonRoute_result_file_tag).def
-    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
-        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
-    }
-	if { $lvs_enabled } {
-		run_magic_spice_export
-		run_lvs; # requires run_magic_spice_export
-	}
-
-}
-
-proc run_drc_step {{ drc_enabled 1 }} {
-    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
-        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
-    }
-	if { $drc_enabled } {
-		run_magic_drc
-		run_klayout_drc
-	}
-}
-
-proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
-    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
-        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
-    } else {
-        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
-    }
-	if { $antenna_check_enabled } {
-		run_antenna_check
-	}
-}
-
-proc run_flow {args} {
-       set script_dir [file dirname [file normalize [info script]]]
-
-		set options {
-		{-design required}
-		{-save_path optional}
-		{-no_lvs optional}
-	    {-no_drc optional}
-	    {-no_antennacheck optional}
-	}
-	set flags {-save}
-	parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
-
-	prep {*}$args
-
-        set LVS_ENABLED 1
-        set DRC_ENABLED 0
-        set ANTENNACHECK_ENABLED 1
-
-        set steps [dict create "synthesis" {run_synthesis "" } \
-                "floorplan" {run_floorplan ""} \
-                "placement" {run_placement_step ""} \
-                "cts" {run_cts_step ""} \
-                "routing" {run_routing_step ""}\
-                "diode_insertion" {run_diode_insertion_2_5_step ""} \
-                "power_pins_insertion" {run_power_pins_insertion_step ""} \
-                "gds_magic" {run_magic ""} \
-                "gds_drc_klayout" {run_klayout ""} \
-                "gds_xor_klayout" {run_klayout_gds_xor ""} \
-                "lvs" "run_lvs_step $LVS_ENABLED" \
-                "drc" "run_drc_step $DRC_ENABLED" \
-                "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
-                "cvc" {run_lef_cvc}
-        ]
-
-       set_if_unset arg_values(-to) "cvc";
-
-       if {  [info exists ::env(CURRENT_STEP) ] } {
-           puts "\[INFO\]:Picking up where last execution left off"
-           puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
-       } else {
-           set ::env(CURRENT_STEP) "synthesis";
-       }
-       set_if_unset arg_values(-from) $::env(CURRENT_STEP);
-       set exe 0;
-       dict for {step_name step_exe} $steps {
-           if { [ string equal $arg_values(-from) $step_name ] } {
-               set exe 1;
-           }
-
-           if { $exe } {
-               # For when it fails
-               set ::env(CURRENT_STEP) $step_name
-               [lindex $step_exe 0] [lindex $step_exe 1] ;
-           }
-
-           if { [ string equal $arg_values(-to) $step_name ] } {
-               set exe 0:
-               break;
-           }
-
-       }
-
-       # for when it resumes
-       set steps_as_list [dict keys $steps]
-       set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
-       set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
-
-	if {  [info exists flags_map(-save) ] } {
-		if { ! [info exists arg_values(-save_path)] } {
-			set arg_values(-save_path) ""
-		}
-		save_views 	-lef_path $::env(magic_result_file_tag).lef \
-			-def_path $::env(CURRENT_DEF) \
-			-gds_path $::env(magic_result_file_tag).gds \
-			-mag_path $::env(magic_result_file_tag).mag \
-			-maglef_path $::env(magic_result_file_tag).lef.mag \
-			-spice_path $::env(magic_result_file_tag).spice \
-			-spef_path $::env(CURRENT_SPEF) \
-			-verilog_path $::env(CURRENT_NETLIST) \
-			-save_path $arg_values(-save_path) \
-			-tag $::env(RUN_TAG)
-	}
-
-
-	calc_total_runtime
-	save_state
-	generate_final_summary_report
-	
-	check_timing_violations
-
-	puts_success "Flow Completed Without Fatal Errors."
-
-}
-
-run_flow {*}$argv
diff --git a/signoff/pinmux/PDK_SOURCES b/signoff/pinmux/PDK_SOURCES
index ca3684a..22e7dc1 100644
--- a/signoff/pinmux/PDK_SOURCES
+++ b/signoff/pinmux/PDK_SOURCES
@@ -1,6 +1,3 @@
--ne openlane 
-8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
--ne skywater-pdk 
-c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
--ne open_pdks 
-14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index 3bac00d..a03bb10 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h8m51s,-1,42496.969696969696,0.2475,21248.484848484848,25.12,693.05,5259,0,0,0,0,0,0,-1,1,0,-1,-1,388178,55535,0.0,0.0,-1,-0.21,-1,0.0,0.0,-1,-0.21,-1,284496978.0,1.93,41.73,29.37,8.68,0.49,-1,3370,8310,523,5463,0,0,0,3952,0,0,0,0,0,0,0,4,1188,1209,11,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h8m12s0ms,0h5m24s0ms,44129.29292929293,0.2475,22064.646464646466,26.19,882.68,5461,0,0,0,0,0,0,0,-1,0,-1,-1,446336,56211,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,349213339.0,0.0,58.21,42.89,33.48,21.65,-1,3480,8519,562,5601,0,0,0,4063,123,107,40,77,933,109,14,285,1086,1034,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim/PDK_SOURCES b/signoff/qspim/PDK_SOURCES
index ca3684a..22e7dc1 100644
--- a/signoff/qspim/PDK_SOURCES
+++ b/signoff/qspim/PDK_SOURCES
@@ -1,6 +1,3 @@
--ne openlane 
-8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
--ne skywater-pdk 
-c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
--ne open_pdks 
-14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/qspim/final_summary_report.csv b/signoff/qspim/final_summary_report.csv
index f03da6c..88bd26a 100644
--- a/signoff/qspim/final_summary_report.csv
+++ b/signoff/qspim/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h14m22s,-1,69204.04040404041,0.2475,34602.020202020205,39.6,779.71,8564,0,0,0,0,0,0,-1,1,0,-1,-1,417412,80389,-0.29,-5.32,-1,0.0,-1,-14.71,-2179.87,-1,0.0,-1,263659655.0,0.0,40.7,36.95,6.51,0.87,-1,7378,11042,803,4466,0,0,0,8352,0,0,0,0,0,0,0,4,2000,2523,24,388,3234,0,3622,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.42,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/qspim,qspim_top,qspim,flow completed,0h11m57s0ms,0h8m37s0ms,65696.9696969697,0.2475,32848.48484848485,37.92,1063.97,8130,0,0,0,0,0,0,0,-1,0,-1,-1,419590,71747,-0.55,-5.04,-1,0.0,0.0,-21.45,-1943.78,-1,0.0,0.0,256460720.0,0.0,50.47,49.05,23.05,22.36,-1,7374,11038,803,4466,0,0,0,8348,263,96,195,114,1420,214,34,1460,1553,1517,17,388,3234,0,3622,100.0,10.0,10,AREA 0,4,50,1,100,100,0.42,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb_spi/final_summary_report.csv b/signoff/uart_i2cm_usb_spi/final_summary_report.csv
index 82f2b7b..1c71b64 100644
--- a/signoff/uart_i2cm_usb_spi/final_summary_report.csv
+++ b/signoff/uart_i2cm_usb_spi/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow_completed,0h13m36s,-1,63977.14285714286,0.35,31988.57142857143,37.54,836.07,11196,0,0,0,0,0,0,-1,1,0,-1,-1,434083,97891,-4.52,-4.86,-1,-4.69,-1,-141.37,-151.91,-1,-139.26,-1,264395920.0,0.39,30.63,28.98,0.99,0.4,-1,8563,12970,1541,5891,0,0,0,9737,0,0,0,0,0,0,0,4,2730,2694,26,498,4643,0,5141,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.45,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow_completed,0h16m31s,-1,64462.85714285714,0.35,32231.42857142857,37.52,801.87,11281,0,0,0,0,0,0,0,1,0,-1,-1,442250,99040,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,270825594.0,3.05,31.16,29.59,1.14,0.29,-1,8696,13075,1555,5877,0,0,0,9816,0,0,0,0,0,0,0,4,2700,2702,26,498,4643,0,5141,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.45,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
new file mode 100644
index 0000000..80c7664
--- /dev/null
+++ b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane N/A
diff --git a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
new file mode 100644
index 0000000..22e7dc1
--- /dev/null
+++ b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
@@ -0,0 +1,3 @@
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv b/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv
new file mode 100644
index 0000000..ac30b2a
--- /dev/null
+++ b/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/uart_i2cm_usb_spi_top,uart_i2c_usb_spi_top,uart_i2cm_usb_spi_top,flow completed,0h15m33s0ms,0h11m2s0ms,69400.0,0.35,34700.0,39.27,1463.03,12145,0,0,0,0,0,0,0,-1,0,-1,-1,630996,105793,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,373528655.0,0.0,53.48,52.78,23.7,25.92,-1,8698,13063,1552,5853,0,0,0,9820,378,189,259,276,2194,356,86,807,2409,2348,19,498,4643,0,5141,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 6959204..4680658 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h33m21s0ms,0h4m6s0ms,-2.0,-1,-1,-1,540.64,12,0,0,0,0,0,0,0,0,2,-1,-1,1256374,6915,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.81,7.25,0.67,0.31,-1,225,2313,225,2313,0,0,0,12,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,130,0.55,0.3,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h30m35s0ms,0h4m36s0ms,-2.0,-1,-1,-1,547.92,12,0,0,0,0,0,0,0,0,0,-1,-1,1395458,6924,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.97,8.97,0.84,0.47,0.0,226,2315,226,2315,0,0,0,12,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,130,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES
index ca3684a..22e7dc1 100644
--- a/signoff/wb_host/PDK_SOURCES
+++ b/signoff/wb_host/PDK_SOURCES
@@ -1,6 +1,3 @@
--ne openlane 
-8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
--ne skywater-pdk 
-c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
--ne open_pdks 
-14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 24b958a..d3d1f84 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h6m52s,-1,59300.0,0.14,29650.0,37.93,636.42,4151,0,0,0,0,0,0,0,2,0,0,-1,215349,39348,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,160042151.0,7.36,37.22,36.69,1.49,0.3,-1,3488,6161,1030,3559,0,0,0,3786,0,0,0,0,0,0,0,4,1232,1202,17,278,1833,0,2111,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.38,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_host,wb_host,wb_host,flow completed,0h5m24s0ms,0h3m35s0ms,60517.64705882353,0.14875,30258.823529411766,36.67,759.34,4501,0,0,0,0,0,0,0,9,0,0,-1,206351,36529,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,156181924.0,0.0,45.83,48.0,4.16,12.69,-1,3461,6134,1009,3538,0,0,0,3773,372,52,74,184,652,130,23,458,1014,989,11,296,1950,0,2246,100.0,10.0,10,AREA 0,4,50,1,100,100,0.38,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES
index ca3684a..22e7dc1 100644
--- a/signoff/wb_interconnect/PDK_SOURCES
+++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -1,6 +1,3 @@
--ne openlane 
-8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
--ne skywater-pdk 
-c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
--ne open_pdks 
-14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index dc04ace..5385acd 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h8m15s,-1,17786.95652173913,0.46,8893.478260869564,8.68,721.65,4091,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,640876,41064,-0.73,-6.41,-1,-1.56,-1,-52.16,-1603.55,-1,-180.97,-1,557971394.0,0.0,10.49,40.22,1.32,33.74,0.0,1458,4661,237,3439,0,0,0,2319,0,0,0,0,0,0,0,4,1150,1018,18,1674,5873,0,7547,90.9090909090909,11,10,AREA 0,2,50,1,120,120,0.3,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h40m59s0ms,0h35m23s0ms,37937.5,0.5760000000000001,18968.75,16.98,1388.21,10926,0,0,0,0,0,0,0,-1,0,-1,-1,1075525,94792,-1.53,-3.34,-1,-2.98,-3.4,-106.67,-233.97,-1,-293.74,-303.87,834639052.0,0.0,25.33,47.4,4.97,27.65,-1,3846,12928,637,9716,0,0,0,5341,269,12,304,131,626,98,13,1402,1753,1688,16,1306,7532,0,8838,74.6268656716418,13.4,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,10,4
diff --git a/signoff/yifive/final_summary_report.csv b/signoff/yifive/final_summary_report.csv
index 4a26323..c0b31b8 100644
--- a/signoff/yifive/final_summary_report.csv
+++ b/signoff/yifive/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,1h0m15s,-1,53775.953079178886,1.27875,26887.976539589443,30.43,1603.14,34383,0,-1,-1,-1,-1,0,-1,-1,0,-1,-1,2656544,381348,-15.47,-42.07,-1,-2.29,-1,-34148.14,-19180.15,-1,-43.72,-1,1952929426.0,10.78,39.67,51.49,5.51,10.2,-1,28691,48378,1777,21057,0,0,0,34243,0,0,0,0,0,0,0,4,8316,8735,54,1122,17734,0,18856,90.9090909090909,11,10,AREA 0,4,50,1,153.6,153.18,0.34,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,1h8m10s,-1,54876.90223886543,1.2551,27438.451119432713,30.94,1597.95,34438,0,0,0,0,0,0,0,40,0,-1,-1,2726452,382921,-15.47,-41.5,-1,-1.15,-1,-34139.48,-18385.69,-1,-8.8,-1,2033771950.0,21.88,40.38,55.32,5.28,9.71,-1,28675,48362,1777,21057,0,0,0,34227,0,0,0,0,0,0,0,4,8315,8734,55,1116,17360,0,18476,90.9090909090909,11,10,AREA 0,4,50,1,153.6,153.18,0.32,0.0,sky130_fd_sc_hd,4,4
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl
index b9f1c98..464c419 100644
--- a/sta/scripts/caravel_timing.tcl
+++ b/sta/scripts/caravel_timing.tcl
@@ -45,9 +45,9 @@
 	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel.v	
 
 	# User project netlist
-        read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/qspim_top.v
         read_verilog $::env(USER_ROOT)/verilog/gl/yifive.v  
-        read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2cm_usb_spi.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v
         read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v  
         read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
         read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v
@@ -161,6 +161,8 @@
 
 
 	read_sdc -echo ./sdc/caravel.sdc	
+	set_propagated_clock [all_clocks]
+
 	check_setup  -verbose >  unconstraints.rpt
 	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
 	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
diff --git a/sta/scripts/pinmux_timing.tcl b/sta/scripts/pinmux_timing.tcl
new file mode 100644
index 0000000..17786bc
--- /dev/null
+++ b/sta/scripts/pinmux_timing.tcl
@@ -0,0 +1,48 @@
+
+        set ::env(USER_ROOT)    "/home/dinesha/workarea/opencore/git/riscduino"
+        #set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe"
+        #set ::env(CARAVEL_PDK_ROOT)  "/opt/pdk_mpw4"
+        set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel"
+        set ::env(CARAVEL_PDK_ROOT)  "/opt/pdk_mpw4"
+
+        read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib	
+
+	# User project netlist
+        read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v  
+
+
+	link_design pinmux
+
+
+	## User Project Spef
+        read_spef  $::env(USER_ROOT)/spef/pinmux.spef
+
+
+	read_sdc -echo ./sdc/pinmux.sdc	
+	set_propagated_clock [all_clocks]
+
+	check_setup  -verbose >  unconstraints.rpt
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_worst_slack -max 	
+	report_worst_slack -min 	
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10	
+	report_check_types -max_slew -max_capacitance -max_fanout -violators  > slew.cap.fanout.vio.rpt
+
diff --git a/sta/scripts/qspim.tcl b/sta/scripts/qspim.tcl
new file mode 100644
index 0000000..c4ff524
--- /dev/null
+++ b/sta/scripts/qspim.tcl
@@ -0,0 +1,47 @@
+
+        set ::env(USER_ROOT)    "/home/dinesha/workarea/opencore/git/riscduino"
+        #set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe"
+        #set ::env(CARAVEL_PDK_ROOT)  "/opt/pdk_mpw4"
+        set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel"
+        set ::env(CARAVEL_PDK_ROOT)  "/opt/pdk_mpw4"
+
+        read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib	
+
+	# User project netlist
+        read_verilog $::env(USER_ROOT)/verilog/gl/qspim_top.v  
+
+
+	link_design qspim_top
+
+
+	## User Project Spef
+        read_spef  $::env(USER_ROOT)/spef/qspim_top.spef
+
+
+	read_sdc -echo ./sdc/qspim.sdc	
+	set_propagated_clock [all_clocks]
+	check_setup  -verbose >  unconstraints.rpt
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_worst_slack -max 	
+	report_worst_slack -min 	
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10	
+	report_check_types -max_slew -max_capacitance -max_fanout -violators  > slew.cap.fanout.vio.rpt
+
diff --git a/sta/scripts/riscdunio.tcl b/sta/scripts/riscdunio.tcl
new file mode 100644
index 0000000..486242c
--- /dev/null
+++ b/sta/scripts/riscdunio.tcl
@@ -0,0 +1,88 @@
+
+        set ::env(USER_ROOT)    "/home/dinesha/workarea/opencore/git/riscduino"
+        #set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe"
+        #set ::env(CARAVEL_PDK_ROOT)  "/opt/pdk_mpw4"
+        set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel"
+        set ::env(CARAVEL_PDK_ROOT)  "/opt/pdk_mpw4"
+
+        read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib	
+
+	puts "IP   :: Total Cell :: Total register"
+        read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
+	link_design qspim_top
+	set tcell [llength [get_cell -hier *]]
+	set tregs [llength [all_registers]]
+	puts "qspim :: $tcell :: $tregs "
+
+        read_verilog $::env(USER_ROOT)/verilog/gl/yifive.v  
+	link_design ycr1_top_wb
+	set tcell [llength [get_cell -hier *]]
+	set tregs [llength [all_registers]]
+	puts "yifive :: $tcell :: $tregs "
+
+        read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2cm_usb_spi.v
+	link_design uart_i2c_usb_spi_top
+	set tcell [llength [get_cell -hier *]]
+	set tregs [llength [all_registers]]
+	puts "uart_i2cm_usb_spi :: $tcell :: $tregs "
+
+        read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v  
+	link_design wb_host
+	set tcell [llength [get_cell -hier *]]
+	set tregs [llength [all_registers]]
+	puts "wb_host :: $tcell :: $tregs "
+
+        read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
+	link_design wb_interconnect
+	set tcell [llength [get_cell -hier *]]
+	set tregs [llength [all_registers]]
+	puts "wb_interconnect :: $tcell :: $tregs "
+
+        read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v
+	link_design pinmux
+	set tcell [llength [get_cell -hier *]]
+	set tregs [llength [all_registers]]
+	puts "pinmux :: $tcell :: $tregs "
+
+        read_verilog $::env(USER_ROOT)/verilog/gl/DFFRAM.v
+	link_design DFFRAM
+	set tcell [llength [get_cell -hier *]]
+	set tregs [llength [all_registers]]
+	puts "DFFRAM :: $tcell :: $tregs "
+
+        read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v  
+        read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/DFFRAM.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v  
+        read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2cm_usb_spi.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/yifive.v  
+
+	link_design user_project_wrapper
+	set tcell [llength [get_cell -hier *]]
+	set tregs [llength [all_registers]]
+	puts "user_project_wrapper :: $tcell :: $tregs "
+
+
+
+
+
diff --git a/sta/scripts/uart_i2c_usb_spi_timing.tcl b/sta/scripts/uart_i2c_usb_spi_timing.tcl
new file mode 100644
index 0000000..2377763
--- /dev/null
+++ b/sta/scripts/uart_i2c_usb_spi_timing.tcl
@@ -0,0 +1,47 @@
+
+        set ::env(USER_ROOT)    "/home/dinesha/workarea/opencore/git/riscduino"
+        #set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe"
+        #set ::env(CARAVEL_PDK_ROOT)  "/opt/pdk_mpw4"
+        set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel"
+        set ::env(CARAVEL_PDK_ROOT)  "/opt/pdk_mpw4"
+
+        read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib	
+
+	# User project netlist
+        read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v  
+
+
+	link_design uart_i2c_usb_spi_top
+
+
+	## User Project Spef
+        read_spef  $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef
+
+
+	read_sdc -echo ./sdc/uart_i2c_usb_spi.sdc	
+	set_propagated_clock [all_clocks]
+	check_setup  -verbose >  unconstraints.rpt
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_worst_slack -max 	
+	report_worst_slack -min 	
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10	
+	report_check_types -max_slew -max_capacitance -max_fanout -violators  > slew.cap.fanout.vio.rpt
+
diff --git a/sta/scripts/wb_host.tcl b/sta/scripts/wb_host.tcl
new file mode 100644
index 0000000..38b0454
--- /dev/null
+++ b/sta/scripts/wb_host.tcl
@@ -0,0 +1,46 @@
+
+        set ::env(USER_ROOT)    "/home/dinesha/workarea/opencore/git/riscduino"
+        #set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe"
+        #set ::env(CARAVEL_PDK_ROOT)  "/opt/pdk_mpw4"
+        set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel"
+        set ::env(CARAVEL_PDK_ROOT)  "/opt/pdk_mpw4"
+
+        read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib	
+
+	# User project netlist
+        read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v  
+
+
+	link_design wb_host
+
+
+	## User Project Spef
+        read_spef  $::env(USER_ROOT)/spef/wb_host.spef
+
+
+	read_sdc -echo ./sdc/wb_host.sdc	
+	check_setup  -verbose >  unconstraints.rpt
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_worst_slack -max 	
+	report_worst_slack -min 	
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10	
+	report_check_types -max_slew -max_capacitance -max_fanout -violators  > slew.cap.fanout.vio.rpt
+
diff --git a/sta/scripts/yifive_timing.tcl b/sta/scripts/yifive_timing.tcl
index 02d4e58..2dcd8e5 100644
--- a/sta/scripts/yifive_timing.tcl
+++ b/sta/scripts/yifive_timing.tcl
@@ -36,6 +36,8 @@
 
 
 	read_sdc -echo ./sdc/yifive.sdc	
+	set_propagated_clock [all_clocks]
+
 	check_setup  -verbose >  unconstraints.rpt
 	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
 	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc
index 448e929..5aa1b71 100644
--- a/sta/sdc/caravel.sdc
+++ b/sta/sdc/caravel.sdc
@@ -48,12 +48,12 @@
 
 set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[0]}]
 set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[1]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[2]}]
 set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[3]}]
 
 set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}]
 set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}]
-set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
 set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}]
 
 set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}]
diff --git a/sta/sdc/pinmux.sdc b/sta/sdc/pinmux.sdc
new file mode 100644
index 0000000..e0601e3
--- /dev/null
+++ b/sta/sdc/pinmux.sdc
@@ -0,0 +1,66 @@
+###############################################################################
+# Created by write_sdc
+# Thu Nov 11 05:33:42 2021
+###############################################################################
+current_design pinmux
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_propagated_clock [get_clocks {mclk}]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+### ClkSkew Adjust
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[3]}]
+
+
+set_max_delay   3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay   2 -to   [get_ports {wbd_clk_pinmux}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_pinmux
+
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {h_reset_n}]
+
+set_input_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}]
+set_input_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
+
+
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+
+set_output_delay -min -3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -min -3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+
+
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {qspim_rst_n}]
+set_output_delay -min -3.000 -clock [get_clocks {mclk}] -add_delay [get_ports {qspim_rst_n}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs]
+set cap_load 0.0334
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/openlane/qspim/base.sdc b/sta/sdc/qspim.sdc
similarity index 74%
copy from openlane/qspim/base.sdc
copy to sta/sdc/qspim.sdc
index b18259c..1b732a6 100644
--- a/openlane/qspim/base.sdc
+++ b/sta/sdc/qspim.sdc
@@ -68,6 +68,12 @@
 set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[1]}]
 set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[2]}]
 set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[3]}]
+
+set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[0]}]
+set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[1]}]
+set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[2]}]
+set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[3]}]
+
 set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[0]}]
 set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[1]}]
 set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[2]}]
@@ -77,6 +83,12 @@
 set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[1]}]
 set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[2]}]
 set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[3]}]
+
+set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[0]}]
+set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[1]}]
+set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[2]}]
+set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[3]}]
+
 set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[0]}]
 set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[1]}]
 set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[2]}]
@@ -257,80 +269,18 @@
 set_max_delay  10.0000 -to [get_ports {spi_debug[8]}]
 set_max_delay  10.0000 -to [get_ports {spi_debug[9]}]
 
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[0]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[10]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[11]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[12]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[13]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[14]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[15]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[16]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[17]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[18]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[19]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[1]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[20]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[21]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[22]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[23]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[24]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[25]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[26]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[27]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[28]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[29]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[2]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[30]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[31]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[3]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[4]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[5]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[6]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[7]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[8]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[9]}]
-set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}]
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}]
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}]
 
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[0]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[10]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[11]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[12]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[13]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[14]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[15]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[16]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[17]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[18]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[19]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[1]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[20]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[21]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[22]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[23]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[24]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[25]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[26]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[27]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[28]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[29]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[2]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[30]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[31]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[3]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[4]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[5]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[6]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[7]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[8]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[9]}]
-set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}]
+set_output_delay -min -2.7500 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}]
+set_output_delay -min -2.7500 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[*]}]
+set_output_delay -min -2.7500 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}]
 ###############################################################################
 # Environment
 ###############################################################################
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs]
+set cap_load 0.0334
 puts "\[INFO\]: Setting load to: $cap_load"
 set_load  $cap_load [all_outputs]
 ###############################################################################
diff --git a/openlane/uart_i2cm_usb_spi/base.sdc b/sta/sdc/uart_i2c_usb_spi.sdc
similarity index 80%
copy from openlane/uart_i2cm_usb_spi/base.sdc
copy to sta/sdc/uart_i2c_usb_spi.sdc
index bee06d8..f73aa1b 100644
--- a/openlane/uart_i2cm_usb_spi/base.sdc
+++ b/sta/sdc/uart_i2c_usb_spi.sdc
@@ -52,17 +52,23 @@
 set_input_delay  -min 2.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_wr}]
 
 
-set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
-set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -max 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}]
 
-set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
-set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}]
+set_output_delay -min -2.7500 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -min -2.7500 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}]
+
+set_multicycle_path -setup  -from [get_ports {reg_addr[*]}] -to [get_ports {reg_ack}] 2
+set_multicycle_path -setup  -from [get_ports {reg_addr[*]}] -to [get_ports {reg_rdata[*]}] 2
+
+set_multicycle_path -hold  -from [get_ports {reg_addr[*]}] -to [get_ports {reg_ack}] 1
+set_multicycle_path -hold  -from [get_ports {reg_addr[*]}] -to [get_ports {reg_rdata[*]}] 1
 
 ###############################################################################
 # Environment
 ###############################################################################
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs]
+set cap_load 0.0334
 puts "\[INFO\]: Setting load to: $cap_load"
 set_load  $cap_load [all_outputs]
 
diff --git a/sta/sdc/wb_host.sdc b/sta/sdc/wb_host.sdc
new file mode 100644
index 0000000..40a67a7
--- /dev/null
+++ b/sta/sdc/wb_host.sdc
@@ -0,0 +1,103 @@
+###############################################################################
+# Created by write_sdc
+# Wed Nov 10 16:52:52 2021
+###############################################################################
+current_design wb_host
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wbm_clk_i -period 10.0000 [get_ports {wbm_clk_i}]
+create_clock -name wbs_clk_i -period 10.0000 [get_ports {wbs_clk_i}]
+create_clock -name uart_clk -period 100.0000 [get_pins {u_uart2wb.u_core.u_uart_clk.u_mux/X}]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {uart_clk}]  \
+ -group [get_clocks {wbs_clk_i}] \
+ -group [get_clocks {wbm_clk_i}] -comment {Async Clock group}
+
+### ClkSkew Adjust
+set_case_analysis 0 [get_ports {cfg_cska_wh[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[3]}]
+
+
+set_max_delay   3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay   2 -to   [get_ports {wbd_clk_wh}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_wh
+
+### WBM I/F
+#Strobe is registered inside the wb_host before generating chip select
+# So wbm_adr_i  wbm_we_i wbm_sel_i wbm_dat_i are having 2 cycle setup
+set_multicycle_path -setup  -from [get_ports {wbm_adr_i[*]}] 2
+set_multicycle_path -setup  -from [get_ports {wbm_cyc_i}]  2
+set_multicycle_path -setup  -from [get_ports {wbm_dat_i[*]}] 2
+set_multicycle_path -setup  -from [get_ports {wbm_sel_i[*]}] 2
+set_multicycle_path -setup  -from [get_ports {wbm_we_i}] 2
+
+set_multicycle_path -hold  -from [get_ports {wbm_adr_i[*]}] 2
+set_multicycle_path -hold  -from [get_ports {wbm_cyc_i}]  2
+set_multicycle_path -hold  -from [get_ports {wbm_dat_i[*]}] 2
+set_multicycle_path -hold  -from [get_ports {wbm_sel_i[*]}] 2
+set_multicycle_path -hold  -from [get_ports {wbm_we_i}] 2
+
+#
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_rst_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_stb_i}]
+
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_rst_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_stb_i}]
+
+set_output_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_ack_o}]
+set_output_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[*]}]
+set_output_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_err_o}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_ack_o}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_err_o}]
+# WBS I/F
+set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
+
+set_output_delay -min -1.2500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
+set_output_delay -min -1.2500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay -min -1.2500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
+set_output_delay -min -1.2500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
+set_output_delay -min -1.2500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
+set_output_delay -min -1.2500 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs]
+set cap_load 0.0334
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+###############################################################################
+# Design Rules
+###############################################################################
+
+#disable clock gating check at static clock select pins
+set_false_path -through [get_pins u_cpu_ref_sel.u_mux/S]
+set_false_path -through [get_pins u_cpu_clk_sel.u_mux/S]
+set_false_path -through [get_pins u_wbs_clk_sel.u_mux/S]
+set_false_path -through [get_pins u_usb_clk_sel.u_mux/S]
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index 2bc1cfb..97b1d80 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -78,6 +78,9 @@
 `include "mt48lc8m8a2.v"
 `include "is62wvs1288.v"
 
+
+`define ADDR_SPACE_PINMUX  32'h3002_0000
+
 localparam [31:0]      YCR1_SIM_EXIT_ADDR      = 32'h0000_00F8;
 localparam [31:0]      YCR1_SIM_PRINT_ADDR     = 32'hF000_0000;
 localparam [31:0]      YCR1_SIM_EXT_IRQ_ADDR   = 32'hF000_0100;
@@ -289,7 +292,7 @@
 	        repeat (2) @(posedge clock);
 		#1;
 		// Remove WB and SPI Reset, Keep SDARM and CORE under Reset
-                wb_user_core_write('h3080_0000,'h5);
+                wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F);
 
 		// CS#2 Switch to QSPI Mode
                 wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
@@ -381,7 +384,7 @@
 //  ----------------------------------------------------
 
    wire flash_clk = io_out[24];
-   wire flash_csb = io_out[28];
+   wire flash_csb = io_out[25];
    // Creating Pad Delay
    wire #1 io_oeb_29 = io_oeb[29];
    wire #1 io_oeb_30 = io_oeb[30];
@@ -416,7 +419,7 @@
        );
 
 
-   wire spiram_csb = io_out[26];
+   wire spiram_csb = io_out[27];
 
    is62wvs1288 #(.mem_file_name("none"))
 	u_sram (
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 3b15b3d..99e0acb 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -242,8 +242,8 @@
          wb_user_core_write('h3080_0000,'h1);
 
 	 wb_user_core_read_check(32'h30020058,read_data,32'h8273_8343);
-	 wb_user_core_read_check(32'h3002005C,read_data,32'h1902_2022);
-	 wb_user_core_read_check(32'h30020060,read_data,32'h0003_6000);
+	 wb_user_core_read_check(32'h3002005C,read_data,32'h0203_2022);
+	 wb_user_core_read_check(32'h30020060,read_data,32'h0003_7000);
 
       end
    
diff --git a/verilog/dv/user_sspi/Makefile b/verilog/dv/user_sspi/Makefile
new file mode 100644
index 0000000..2a8d7f1
--- /dev/null
+++ b/verilog/dv/user_sspi/Makefile
@@ -0,0 +1,99 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
+UPRJ_BEHAVIOURAL_MODELS = ../model
+UPRJ_BEHAVIOURAL_AGENTS = ../agents
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
+UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
+UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
+
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
+GCC64_PREFIX?=riscv64-unknown-elf
+
+## RISCV GCC 
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/opt/pdk/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+.SUFFIXES:
+
+PATTERN = user_sspi
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+	-I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
+	$< -o $@ 
+    else  
+	iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+	-I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
+	$< -o $@ 
+   endif
+else  
+	iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.hex: 
+	echo @"This is user boot test, noting to compile the mangment core code"
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.vvp *.vcd *.log *.fst
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_sspi/flash1.hex b/verilog/dv/user_sspi/flash1.hex
new file mode 100755
index 0000000..e3c4b1b
--- /dev/null
+++ b/verilog/dv/user_sspi/flash1.hex
@@ -0,0 +1,26 @@
+@00000000
+00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f
+40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f
+50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f
+60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f
+70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f
+80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f
+90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f
+a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af
+b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf
+c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf
+d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df
+e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef
+f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff
+
+@00000100
+00 11 22 33 44 55 66 77 88 99 AA BB CC DD EE FF 
+
+@00000200
+11 11 11 11 22 22 22 22 33 33 33 33 44 44 44 44
+55 55 55 55 66 66 66 66 77 77 77 77 88 88 88 88
+99 99 99 99 AA AA AA AA AA BB BB BB BB CC CC CC
+DD DD DD DD EE EE EE EE FF FF FF FF 00 00 00 00
diff --git a/verilog/dv/user_sspi/sspi_task.v b/verilog/dv/user_sspi/sspi_task.v
new file mode 100755
index 0000000..1ce38eb
--- /dev/null
+++ b/verilog/dv/user_sspi/sspi_task.v
@@ -0,0 +1,350 @@
+
+// #################################################################
+// Module: spi tasks
+//
+// Description : All ST and ATMEL commands are made into tasks
+// Note: CMD+ADDRESS Sent is Big Endian
+//       Write Data/Read Data Send as Little endian to match RISCV
+//       Data accesss
+// #################################################################
+
+parameter LITTLE_ENDIAN  = 1'b0;
+parameter BIG_ENDIAN     = 1'b1;
+
+event      sspi_error_detected;
+reg  [1:0] sspi_chip_no;
+
+integer sspi_err_cnt;
+
+task sspi_init;
+begin
+   sspi_err_cnt = 0;
+   sspi_chip_no = 0;
+end 
+endtask 
+
+
+always @sspi_error_detected
+begin
+    `TB_GLBL.test_err;
+     sspi_err_cnt = sspi_err_cnt + 1;
+end
+//***** Read Double Word Data from Specific Address ******//
+task sspi_dw_read;
+    input    [7:0]  cmd;
+    input    [23:0] address;
+    output   [31:0] read_data;
+    reg      [31:0] read_data;
+begin
+      sspi_write_dword({cmd,address[23:0]},BIG_ENDIAN,8'h0);
+      sspi_write_byte(32'h00,BIG_ENDIAN,8'h0);  // 8 Bit Dummy Cycle
+      sspi_read_dword(LITTLE_ENDIAN,read_data,8'h1);
+
+end
+endtask
+
+task sspi_dw_write;
+    input    [7:0]  cmd;
+    input    [23:0] address;
+    input   [31:0] write_data;
+begin
+      sspi_write_dword({cmd,address[23:0]},BIG_ENDIAN,8'h0);
+      sspi_write_dword(write_data,LITTLE_ENDIAN,8'h1);
+
+end
+endtask
+
+task sspi_dw_read_check;
+    input    [7:0]  cmd;
+    input    [23:0] address;
+    input    [31:0] exp_data;
+    reg      [31:0] read_data;
+begin
+      sspi_write_dword({cmd,address[23:0]},BIG_ENDIAN,8'h0);
+      sspi_write_byte(32'h00,BIG_ENDIAN,8'h0);  // 8 Bit Dummy Cycle
+      sspi_read_dword(LITTLE_ENDIAN,read_data,8'h1);
+      if(read_data != exp_data) begin
+         -> sspi_error_detected;
+         $display("%m : ERROR :  Address: %x Exp : %x Rxd : %x",address,exp_data,read_data);
+      end else begin
+         $display("%m : STATUS : Address: %x Matched : %x ",address,read_data);
+      end
+
+end
+endtask
+
+// Write One Byte
+task sspi_write_byte;
+    input [7:0] datain;
+    input       endian;
+    input [7:0] cs_byte;
+    reg  [31:0] read_data;
+    begin
+
+      @(posedge `TB_GLBL.clock) 
+      `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h4,{datain,24'h0});
+      `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h0,{1'b1,5'h0,
+	                        endian,
+                                spi_chip_no[1:0],
+                                2'b0,    // Write Operatopm
+                                2'b0,    // Single Transfer
+                                6'h10,    // sck clock period
+                                5'h2,    // cs setup/hold period
+                                cs_byte }); // cs bit 0x40 for 1 byte transaction
+      
+     `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+     while(read_data[31]) begin
+        @(posedge `TB_GLBL.clock) ;
+        `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+      end 
+    end
+endtask
+
+//***** ST : Write Enable task ******//
+task sspi_write_dword;
+    input [31:0] cmd;
+    input        endian; // 0 - Little,1 - Big
+    input [7:0]  cs_byte;
+    reg   [31:0] read_data;
+    begin
+      @(posedge `TB_GLBL.clock) 
+      `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h4,{cmd});
+      `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h0,{1'b1,5'h0,
+	                        endian,
+                                spi_chip_no[1:0],
+                                2'b0,    // Write Operatopm
+                                2'h3,    // 4 Transfer
+                                6'h10,    // sck clock period
+                                5'h2,    // cs setup/hold period
+                                cs_byte[7:0] }); // cs bit information
+      
+     `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+     while(read_data[31]) begin
+        @(posedge `TB_GLBL.clock) ;
+        `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+      end 
+    end
+endtask
+
+
+//***** ST : Write Enable task ******//
+task sspi_read_dword;
+    input         endian;
+    output [31:0] dataout;
+    input  [7:0]  cs_byte;
+    reg    [31:0] read_data;
+    begin
+
+      @(posedge `TB_GLBL.clock) 
+      `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h0,{1'b1,5'h0,
+	                        endian,
+                                spi_chip_no[1:0],
+                                2'b1,    // Read Operatopm
+                                2'h3,    // 4 Transfer
+                                6'h10,    // sck clock period
+                                5'h2,    // cs setup/hold period
+                                cs_byte[7:0] }); // cs bit information
+      
+     `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+
+     while(read_data[31]) begin
+        @(posedge `TB_GLBL.clock) ;
+        `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+     end 
+
+     `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h8,dataout);
+
+    end
+endtask
+
+
+
+task sspi_sector_errase;
+    input [23:0] address;
+    reg   [31:0] read_data;
+    begin
+
+      @(posedge `TB_GLBL.clock) ;
+      `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h4,{8'hD8,address[23:0]});
+      `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h0,{1'b1,5'h0,
+	                        BIG_ENDIAN,
+                                spi_chip_no[1:0],
+                                2'b0,    // Write Operatopm
+                                2'h3,    // 4 Transfer
+                                6'h10,    // sck clock period
+                                5'h2,    // cs setup/hold period
+                                8'h1 }); // cs bit information
+      
+     `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+
+      $display("%t : %m : Sending Sector Errase for Address : %x",$time,address);
+      
+
+     `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+     while(read_data[31]) begin
+        @(posedge `TB_GLBL.clock) ;
+        `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+     end 
+   end
+endtask
+
+
+task sspi_page_write;
+    input [23:0] address;
+    reg [7:0] i;
+    reg [31:0] write_data;
+    begin
+
+      sspi_write_dword({8'h02,address[23:0]},BIG_ENDIAN,8'h0);
+
+      for(i = 0; i < 252 ; i = i + 4) begin
+         write_data [31:24]  = i;
+         write_data [23:16]  = i+1;
+         write_data [15:8]   = i+2;
+         write_data [7:0]    = i+3;
+         sspi_write_dword(write_data,LITTLE_ENDIAN,8'h0);
+         $display("%m : Writing Data-%d : %x",i,write_data);
+      end
+     
+      // Writting last 4 byte with de-selecting the chip select 
+         write_data [31:24]  = i;
+         write_data [23:16]  = i+1;
+         write_data [15:8]   = i+2;
+         write_data [7:0]    = i+3;
+      sspi_write_dword(write_data,LITTLE_ENDIAN,8'h1);
+      $display("%m : Writing Data-%d : %x",i,write_data);
+
+    end
+endtask
+
+
+task sspi_page_read_verify;
+    input [23:0] address;
+    reg   [31:0] read_data;
+    reg [7:0] i;
+    reg [31:0] exp_data;
+    begin
+
+      sspi_write_dword({8'h03,address[23:0]},BIG_ENDIAN,8'h0);
+
+      for(i = 0; i < 252 ; i = i + 4) begin
+         exp_data [31:24]  = i;
+         exp_data [23:16]  = i+1;
+         exp_data [15:8]   = i+2;
+         exp_data [7:0]    = i+3;
+         sspi_read_dword(LITTLE_ENDIAN,read_data,8'h0);
+         if(read_data != exp_data) begin
+            -> sspi_error_detected;
+            $display("%m : ERROR : Data:%d-> Exp : %x Rxd : %x",i,exp_data,read_data);
+         end else begin
+            $display("%m : STATUS :  Data:%d Matched : %x ",i,read_data);
+         end
+
+      end
+     
+      // Reading last 4 byte with de-selecting the chip select 
+         exp_data [31:24]  = i;
+         exp_data [23:16]  = i+1;
+         exp_data [15:8]   = i+2;
+         exp_data [7:0]    = i+3;
+
+         sspi_read_dword(LITTLE_ENDIAN,read_data,8'h1);
+         if(read_data != exp_data) begin
+            -> sspi_error_detected;
+            $display("%m : ERROR : Data:%d-> Exp : %x Rxd : %x",i,exp_data,read_data);
+         end else begin
+            $display("%m : STATUS :  Data:%d Matched : %x ",i,read_data);
+         end
+
+    end
+endtask
+
+
+
+
+task sspi_op_over;
+    reg [31:0] read_data;
+    begin
+     `TB_GLBL.wb_user_core_read('h0,read_data);
+      while(read_data[31]) begin
+        @(posedge `TB_GLBL.clock) ;
+        `TB_GLBL.wb_user_core_read('h0,read_data);
+      end 
+      #100;
+    end
+endtask
+
+task sspi_wait_busy;
+    reg [31:0] read_data;
+    reg        exit_flag;
+    integer    pretime;
+    begin
+
+    read_data = 1;
+    pretime = $time;
+
+     
+  exit_flag = 1;
+   while(exit_flag == 1) begin 
+
+    `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h4,{8'h05,24'h0});
+    `TB_GLBL.wb_user_core_write(`ADDR_SPACE_SSPI+'h0,{1'b1,5'h0,
+	                        BIG_ENDIAN,
+                                spi_chip_no[1:0],
+                                2'b0,    // Write Operation
+                                2'b0,    // 1 Transfer
+                                6'h10,    // sck clock period
+                                5'h2,    // cs setup/hold period
+                                8'h0 }); // cs bit information
+
+
+        `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+        while(read_data[31]) begin
+          @(posedge `TB_GLBL.clock) ;
+          `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+        end 
+
+     // Send Status Request Cmd
+
+
+      `TB_GLBL.wb_user_core_write('h0,{1'b1,5'h0,
+	                        BIG_ENDIAN,
+                                spi_chip_no[1:0],
+                                2'b1,    // Read Operation
+                                2'b0,    // 1 Transfer
+                                6'h10,    // sck clock period
+                                5'h2,    // cs setup/hold period
+                                8'h40 }); // cs bit information
+
+        
+        `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+        while(read_data[31]) begin
+          @(posedge `TB_GLBL.clock) ;
+          `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h0,read_data);
+        end 
+      
+        `TB_GLBL.wb_user_core_read(`ADDR_SPACE_SSPI+'h8,read_data);
+        exit_flag = read_data[24];
+        $display("Total time Elapsed: %0t(us): %m : Checking the SPI RDStatus : %x",($time - pretime)/1000000 ,read_data);
+      repeat (1000) @ (posedge `TB_GLBL.clock) ;
+     end
+  end
+endtask
+
+
+
+task sspi_tb_status;
+begin
+
+   $display("#############################");
+   $display("   Test Statistic            ");
+   if(sspi_err_cnt >0) begin 
+      $display("TEST STATUS : FAILED ");
+      $display("TOTAL ERROR COUNT : %d ",sspi_err_cnt);
+   end else begin
+      $display("TEST STATUS : PASSED ");
+   end
+   $display("#############################");
+end
+endtask
+
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v
new file mode 100644
index 0000000..6dcea02
--- /dev/null
+++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -0,0 +1,473 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Standalone User validation Test bench                       ////
+////                                                              ////
+////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/yifive_r0.git              ////
+////  http://www.opencores.org/cores/yifive/                      ////
+////                                                              ////
+////  Description                                                 ////
+////   This is a standalone test bench to validate the            ////
+////   Digital core flash access through External WB i/F.         ////
+////   1.  Check SPI Read Identification                          ////
+////   2.  Check the Direct Memory Read (Qual/Single/Quad)        ////        
+////   3.  Direct SPI Memory Prefetch - 3DW                       ////
+////   4.  Direct SPI Memory Prefetch - 2DW                       ////
+////   5.  Direct SPI Memory Prefetch - 1DW                       ////
+////   6.  Direct SPI Memory Prefetch - 7DW                       ////
+////   7.  1DW  Indirect Read                                     ////
+////   8.  2DW  Indirect Read                                     ////
+////   9.  3DW  Indirect Read                                     ////
+////   10. 4DW  Indirect Read                                     ////
+////   11. 5DW  Indirect Read                                     ////
+////   12. 8DW  Indirect Read                                     ////
+////   13. Sector Erase command + Page Write & Read Back          ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 01 Oct 2021, Dinesh A                               ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+// Note in caravel, 0x30XX_XXXX only come to user interface
+// So, using wb_host bank select we have changing MSB address [31:24] = 0x10
+`define ADDR_SPACE_UART    32'h3001_0000
+`define ADDR_SPACE_SSPI    32'h3001_00C0
+`define ADDR_SPACE_PINMUX  32'h3002_0000
+
+`define TB_GLBL    user_sspi_tb
+
+`include "uprj_netlists.v"
+`include "is62wvs1288.v"
+
+
+module user_sspi_tb;
+	reg clock;
+	reg wb_rst_i;
+	reg power1, power2;
+	reg power3, power4;
+
+        reg        wbd_ext_cyc_i;  // strobe/request
+        reg        wbd_ext_stb_i;  // strobe/request
+        reg [31:0] wbd_ext_adr_i;  // address
+        reg        wbd_ext_we_i;  // write
+        reg [31:0] wbd_ext_dat_i;  // data output
+        reg [3:0]  wbd_ext_sel_i;  // byte enable
+
+        wire [31:0] wbd_ext_dat_o;  // data input
+        wire        wbd_ext_ack_o;  // acknowlegement
+        wire        wbd_ext_err_o;  // error
+
+	// User I/O
+	wire [37:0] io_oeb;
+	wire [37:0] io_out;
+	wire [37:0] io_in;
+
+
+	reg [1:0] spi_chip_no;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+	reg        test_fail;
+	reg [31:0] read_data;
+
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+                wbd_ext_cyc_i ='h0;  // strobe/request
+                wbd_ext_stb_i ='h0;  // strobe/request
+                wbd_ext_adr_i ='h0;  // address
+                wbd_ext_we_i  ='h0;  // write
+                wbd_ext_dat_i ='h0;  // data output
+                wbd_ext_sel_i ='h0;  // byte enable
+	end
+
+	`ifdef WFDUMP
+	   initial begin
+	   	$dumpfile("simx.vcd");
+	   	$dumpvars(5, user_sspi_tb);
+	   end
+       `endif
+
+	initial begin
+		$dumpon;
+
+		#200; // Wait for reset removal
+	        repeat (10) @(posedge clock);
+		$display("Monitor: Standalone User Risc Boot Test Started");
+
+		// Remove Wb Reset
+		wb_user_core_write('h3080_0000,'h1);
+
+                // Enable SPI Multi Functional Ports
+                wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h400);
+
+	        repeat (2) @(posedge clock);
+		#1;
+
+                // Remove the reset
+		// Remove WB and SPI/UART Reset, Keep CORE under Reset
+                wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h01F);
+
+
+		test_fail = 0;
+		sspi_init();
+	        repeat (200) @(posedge clock);
+                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
+                $display("############################################");
+                $display("   Testing IS62/65WVS1288GALL SSRAM Read/Write Access       ");
+                $display("############################################");
+		// SSPI Indirect RAM READ ACCESS-
+		// Byte Read Option
+		// <Instr:0x3> <Addr:24Bit Address> <Read Data Out>
+                spi_chip_no = 2'b00; // Select the Chip Select to zero
+		sspi_dw_read_check(8'h03,24'h0000,32'h03020100);
+		sspi_dw_read_check(8'h03,24'h0004,32'h07060504);
+		sspi_dw_read_check(8'h03,24'h0008,32'h0b0a0908);
+		sspi_dw_read_check(8'h03,24'h000C,32'h0f0e0d0c);
+		sspi_dw_read_check(8'h03,24'h0010,32'h13121110);
+		sspi_dw_read_check(8'h03,24'h0014,32'h17161514);
+		sspi_dw_read_check(8'h03,24'h0018,32'h1B1A1918);
+		sspi_dw_read_check(8'h03,24'h001C,32'h1F1E1D1C);
+
+		sspi_dw_read_check(8'h03,24'h0040,32'h43424140);
+		sspi_dw_read_check(8'h03,24'h0044,32'h47464544);
+		sspi_dw_read_check(8'h03,24'h0048,32'h4B4A4948);
+		sspi_dw_read_check(8'h03,24'h004C,32'h4F4E4D4C);
+
+		sspi_dw_read_check(8'h03,24'h00a0,32'ha3a2a1a0);
+		sspi_dw_read_check(8'h03,24'h00a4,32'ha7a6a5a4);
+		sspi_dw_read_check(8'h03,24'h00a8,32'habaaa9a8);
+		sspi_dw_read_check(8'h03,24'h00aC,32'hafaeadac);
+
+		sspi_dw_read_check(8'h03,24'h0200,32'h11111111);
+		sspi_dw_read_check(8'h03,24'h0204,32'h22222222);
+		sspi_dw_read_check(8'h03,24'h0208,32'h33333333);
+		sspi_dw_read_check(8'h03,24'h020C,32'h44444444);
+
+		// SPI Write
+		sspi_dw_write(8'h02,24'h0000,32'h00112233);
+		sspi_dw_write(8'h02,24'h0004,32'h44556677);
+		sspi_dw_write(8'h02,24'h0008,32'h8899AABB);
+		sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF);
+
+		sspi_dw_write(8'h02,24'h0200,32'h11223344);
+		sspi_dw_write(8'h02,24'h0204,32'h55667788);
+		sspi_dw_write(8'h02,24'h0208,32'h99AABBCC);
+		sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00);
+
+		// SPI Read Check
+		sspi_dw_read_check(8'h03,24'h0000,32'h00112233);
+		sspi_dw_read_check(8'h03,24'h0004,32'h44556677);
+		sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB);
+		sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF);
+
+		sspi_dw_read_check(8'h03,24'h0200,32'h11223344);
+		sspi_dw_read_check(8'h03,24'h0204,32'h55667788);
+		sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC);
+		sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00);
+
+
+		repeat (100) @(posedge clock);
+			// $display("+1000 cycles");
+
+          	if(test_fail == 0) begin
+		   `ifdef GL
+	    	       $display("Monitor: SPI Master Mode (GL) Passed");
+		   `else
+		       $display("Monitor: SPI Master Mode (RTL) Passed");
+		   `endif
+	        end else begin
+		    `ifdef GL
+	    	        $display("Monitor: SPI Master Mode (GL) Failed");
+		    `else
+		        $display("Monitor: SPI Master Mode (RTL) Failed");
+		    `endif
+		 end
+	    	$display("###################################################");
+	        $finish;
+	end
+
+	initial begin
+		wb_rst_i <= 1'b1;
+		#100;
+		wb_rst_i <= 1'b0;	    	// Release reset
+	end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+    .vccd1(USER_VDD1V8),	// User area 1 1.8V supply
+    .vssd1(VSS),	// User area 1 digital ground
+`endif
+    .wb_clk_i        (clock),  // System clock
+    .user_clock2     (1'b1),  // Real-time clock
+    .wb_rst_i        (wb_rst_i),  // Regular Reset signal
+
+    .wbs_cyc_i   (wbd_ext_cyc_i),  // strobe/request
+    .wbs_stb_i   (wbd_ext_stb_i),  // strobe/request
+    .wbs_adr_i   (wbd_ext_adr_i),  // address
+    .wbs_we_i    (wbd_ext_we_i),  // write
+    .wbs_dat_i   (wbd_ext_dat_i),  // data output
+    .wbs_sel_i   (wbd_ext_sel_i),  // byte enable
+
+    .wbs_dat_o   (wbd_ext_dat_o),  // data input
+    .wbs_ack_o   (wbd_ext_ack_o),  // acknowlegement
+
+ 
+    // Logic Analyzer Signals
+    .la_data_in      ('1) ,
+    .la_data_out     (),
+    .la_oenb         ('0),
+ 
+
+    // IOs
+    .io_in          (io_in)  ,
+    .io_out         (io_out) ,
+    .io_oeb         (io_oeb) ,
+
+    .user_irq       () 
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+
+    end
+`endif    
+
+//------------------------------------------------------
+//  Integrate the Serial flash with qurd support to
+//  user core using the gpio pads
+//  ----------------------------------------------------
+   wire flash_io1;
+   wire flash_clk = io_out[16];
+   wire spiram_csb = io_out[13];
+   tri  #1 flash_io0 = io_out[15];
+   assign io_in[14] = flash_io1;
+
+   tri  #1 flash_io2 = 1'b1;
+   tri  #1 flash_io3 = 1'b1;
+
+
+   is62wvs1288 #(.mem_file_name("flash1.hex"))
+	u_sfram (
+         // Data Inputs/Outputs
+           .io0     (flash_io0),
+           .io1     (flash_io1),
+           // Controls
+           .clk    (flash_clk),
+           .csb    (spiram_csb),
+           .io2    (flash_io2),
+           .io3    (flash_io3)
+    );
+
+
+//----------------------------------------------------
+//  Task
+// --------------------------------------------------
+task test_err;
+begin
+     test_fail = 1;
+end
+endtask
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h1;  // write
+  wbd_ext_dat_i =data;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  //$display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  if(data !== cmp_data) begin
+     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+     user_sspi_tb.test_fail = 1;
+  end else begin
+     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  end
+  repeat (2) @(posedge clock);
+end
+endtask
+
+
+`ifdef GL
+
+wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+
+wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
+wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
+wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
+wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
+wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
+wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
+wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
+
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
+wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE  user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+    if(`RISC_CORE.wbd_imem_ack_i)
+          $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+    if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+    if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+`include "sspi_task.v"
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index da87d24..8f900b1 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -763,7 +763,7 @@
 //-----------------------------------------
 // Software Reg-2, Release date: <DAY><MONTH><YEAR>
 // ----------------------------------------
-gen_32b_reg  #(32'h1902_2022) u_reg_23	(
+gen_32b_reg  #(32'h0203_2022) u_reg_23	(
 	      //List of Inputs
 	      .reset_n    (h_reset_n     ),
 	      .clk        (mclk          ),
@@ -776,9 +776,9 @@
 	      );
 
 //-----------------------------------------
-// Software Reg-3: Poject Revison 3.6 = 0003600
+// Software Reg-3: Poject Revison 3.7 = 0003700
 // ----------------------------------------
-gen_32b_reg  #(32'h0003_6000) u_reg_24	(
+gen_32b_reg  #(32'h0003_7000) u_reg_24	(
 	      //List of Inputs
 	      .reset_n    (h_reset_n     ),
 	      .clk        (mclk          ),
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 95c770a..9aa0469 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -101,6 +101,7 @@
      `include "lib/sync_wbb.sv"
      `include "lib/sync_fifo2.sv"
      `include "wb_interconnect/src/wb_arb.sv"
+     `include "wb_interconnect/src/wb_slave_port.sv"
      `include "wb_interconnect/src/wb_interconnect.sv"
 
 
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 1ca7c78..68ba561 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -187,9 +187,11 @@
 ////           spi clock config = 0x2                             ////
 ////        2. spi_oen generation fix for different spi mode      ////
 ////        3. spi_csn de-assertion fix for different spi clk div ////
-////    3.7  Mar 2, Dinesh A                                      ////
+////    3.7  Mar 2 2022, Dinesh A                                 ////
 ////       1. qspi cs# port mapping changed from io 28:25 to 25:28////
 ////       2. sspi, bug fix in reg access and endian support added////
+////       3. Wishbone interconnect now support cross-connect     ////
+////          feature
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 470a421..55bf9fb 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -82,13 +82,6 @@
        output logic                usb_clk          ,
        // Global Reset control
        output logic                wbd_int_rst_n    ,
-       output logic                cpu_rst_n        ,
-       output logic                qspim_rst_n        ,
-       output logic                sspim_rst_n      ,
-       output logic                uart_rst_n       ,
-       output logic                i2cm_rst_n       ,
-       output logic                usb_rst_n        ,
-       output logic                bist_rst_n        ,
 
     // Master Port
        input   logic               wbm_rst_i        ,  // Regular Reset signal
@@ -191,13 +184,6 @@
 
 
 ctech_buf u_buf_wb_rst        (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n));
-ctech_buf u_buf_cpu_rst       (.A(cfg_glb_ctrl[1]),.X(cpu_rst_n));
-ctech_buf u_buf_qspim_rst     (.A(cfg_glb_ctrl[2]),.X(qspim_rst_n));
-ctech_buf u_buf_sspim_rst     (.A(cfg_glb_ctrl[3]),.X(sspim_rst_n));
-ctech_buf u_buf_uart_rst      (.A(cfg_glb_ctrl[4]),.X(uart_rst_n));
-ctech_buf u_buf_i2cm_rst      (.A(cfg_glb_ctrl[5]),.X(i2cm_rst_n));
-ctech_buf u_buf_usb_rst       (.A(cfg_glb_ctrl[6]),.X(usb_rst_n));
-ctech_buf u_buf_bist_rst      (.A(cfg_glb_ctrl[7]),.X(bist_rst_n));
 
 //--------------------------------------------------------------------------------
 // Look like wishbone reset removed early than user Power up sequence
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index 7e062f0..fd68e08 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -240,18 +240,28 @@
   logic  	wbd_err;
 } type_wb_rd_intf;
 
-
-// Master Write Interface
-type_wb_wr_intf  m0_wb_wr;
-type_wb_wr_intf  m1_wb_wr;
-type_wb_wr_intf  m2_wb_wr;
-type_wb_wr_intf  m3_wb_wr;
-
 // Master Read Interface
-type_wb_rd_intf  m0_wb_rd;
-type_wb_rd_intf  m1_wb_rd;
-type_wb_rd_intf  m2_wb_rd;
-type_wb_rd_intf  m3_wb_rd;
+type_wb_rd_intf  m0_bus_rd;
+type_wb_rd_intf  m1_bus_rd;
+type_wb_rd_intf  m2_bus_rd;
+type_wb_rd_intf  m3_bus_rd;
+
+
+type_wb_rd_intf  m0_s0_wb_rd;
+type_wb_rd_intf  m1_s0_wb_rd;
+type_wb_rd_intf  m2_s0_wb_rd;
+type_wb_rd_intf  m3_s0_wb_rd;
+
+type_wb_rd_intf  m0_s1_wb_rd;
+type_wb_rd_intf  m1_s1_wb_rd;
+type_wb_rd_intf  m2_s1_wb_rd;
+type_wb_rd_intf  m3_s1_wb_rd;
+
+type_wb_rd_intf  m0_s2_wb_rd;
+type_wb_rd_intf  m1_s2_wb_rd;
+type_wb_rd_intf  m2_s2_wb_rd;
+type_wb_rd_intf  m3_s2_wb_rd;
+
 
 // Slave Write Interface
 type_wb_wr_intf  s0_wb_wr;
@@ -264,12 +274,6 @@
 type_wb_rd_intf  s2_wb_rd;
 
 
-type_wb_wr_intf  m_bus_wr;  // Multiplexed Master I/F
-type_wb_rd_intf  m_bus_rd;  // Multiplexed Slave I/F
-
-type_wb_wr_intf  s_bus_wr;  // Multiplexed Master I/F
-type_wb_rd_intf  s_bus_rd;  // Multiplexed Slave I/F
-
 // channel repeater
 assign ch_clk_out  = ch_clk_in;
 assign ch_data_out = ch_data_in;
@@ -331,73 +335,321 @@
                               (m3_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : 
                               (m3_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX : 
 			      4'b0000; 
-//----------------------------------------
-// Master Mapping
-// -------------------------------------
-assign m0_wb_wr.wbd_dat = m0_wbd_dat_i;
-assign m0_wb_wr.wbd_adr = {m0_wbd_adr_i[31:2],2'b00};
-assign m0_wb_wr.wbd_sel = m0_wbd_sel_i;
-assign m0_wb_wr.wbd_bl  = 'h1;
-assign m0_wb_wr.wbd_bry = 'b1;
-assign m0_wb_wr.wbd_we  = m0_wbd_we_i;
-assign m0_wb_wr.wbd_cyc = m0_wbd_cyc_i;
-assign m0_wb_wr.wbd_stb = m0_wbd_stb_i;
-assign m0_wb_wr.wbd_tid = m0_wbd_tid_i;
 
-assign m1_wb_wr.wbd_dat = m1_wbd_dat_i;
-assign m1_wb_wr.wbd_adr = {m1_wbd_adr_i[31:2],2'b00};
-assign m1_wb_wr.wbd_sel = m1_wbd_sel_i;
-assign m1_wb_wr.wbd_bl  = 'h1;
-assign m1_wb_wr.wbd_bry = 'b1;
-assign m1_wb_wr.wbd_we  = m1_wbd_we_i;
-assign m1_wb_wr.wbd_cyc = m1_wbd_cyc_i;
-assign m1_wb_wr.wbd_stb = m1_wbd_stb_i;
-assign m1_wb_wr.wbd_tid = m1_wbd_tid_i;
 
-assign m2_wb_wr.wbd_dat = m2_wbd_dat_i;
-assign m2_wb_wr.wbd_adr = {m2_wbd_adr_i[31:2],2'b00};
-assign m2_wb_wr.wbd_sel = m2_wbd_sel_i;
-assign m2_wb_wr.wbd_bl  = m2_wbd_bl_i;
-assign m2_wb_wr.wbd_bry = m2_wbd_bry_i;
-assign m2_wb_wr.wbd_we  = m2_wbd_we_i;
-assign m2_wb_wr.wbd_cyc = m2_wbd_cyc_i;
-assign m2_wb_wr.wbd_stb = m2_wbd_stb_i;
-assign m2_wb_wr.wbd_tid = m2_wbd_tid_i;
+// Target Port -0
+wb_slave_port  u_s0 (
 
-assign m3_wb_wr.wbd_dat = 'h0;
-assign m3_wb_wr.wbd_adr = {m3_wbd_adr_i[31:2],2'b00};
-assign m3_wb_wr.wbd_sel = m3_wbd_sel_i;
-assign m3_wb_wr.wbd_bl  = m3_wbd_bl_i;
-assign m3_wb_wr.wbd_bry = m3_wbd_bry_i;
-assign m3_wb_wr.wbd_we  = m3_wbd_we_i;
-assign m3_wb_wr.wbd_cyc = m3_wbd_cyc_i;
-assign m3_wb_wr.wbd_stb = m3_wbd_stb_i;
-assign m3_wb_wr.wbd_tid = m3_wbd_tid_i;
+          .clk_i                   (clk_i                  ), 
+          .rst_n                   (rst_n                  ),
+	  .cfg_slave_id            (TARGET_SPI_MEM         ),
 
-assign m0_wbd_dat_o  =  m0_wb_rd.wbd_dat;
-assign m0_wbd_ack_o  =  m0_wb_rd.wbd_ack;
-assign m0_wbd_lack_o =  m0_wb_rd.wbd_lack;
-assign m0_wbd_err_o  =  m0_wb_rd.wbd_err;
+         // Master 0 Interface
+          .m0_wbd_dat_i            (m0_wbd_dat_i           ),
+          .m0_wbd_adr_i            (m0_wbd_adr_i           ),
+          .m0_wbd_sel_i            (m0_wbd_sel_i           ),
+          .m0_wbd_we_i             (m0_wbd_we_i            ),
+          .m0_wbd_cyc_i            (m0_wbd_cyc_i           ),
+          .m0_wbd_stb_i            (m0_wbd_stb_i           ),
+	  .m0_wbd_tid_i            (m0_wbd_tid_i           ),
+          .m0_wbd_dat_o            (m0_s0_wb_rd.wbd_dat    ),
+          .m0_wbd_ack_o            (m0_s0_wb_rd.wbd_ack    ),
+          .m0_wbd_lack_o           (m0_s0_wb_rd.wbd_lack   ),
+          .m0_wbd_err_o            (m0_s0_wb_rd.wbd_err    ),
+         
+         // Master 1 Interface
+          .m1_wbd_dat_i            (m1_wbd_dat_i           ),
+          .m1_wbd_adr_i            (m1_wbd_adr_i           ),
+          .m1_wbd_sel_i            (m1_wbd_sel_i           ),
+          .m1_wbd_we_i             (m1_wbd_we_i            ),
+          .m1_wbd_cyc_i            (m1_wbd_cyc_i           ),
+          .m1_wbd_stb_i            (m1_wbd_stb_i           ),
+	  .m1_wbd_tid_i            (m1_wbd_tid_i           ),
+          .m1_wbd_dat_o            (m1_s0_wb_rd.wbd_dat    ),
+          .m1_wbd_ack_o            (m1_s0_wb_rd.wbd_ack    ),
+          .m1_wbd_lack_o           (m1_s0_wb_rd.wbd_lack   ),
+          .m1_wbd_err_o            (m1_s0_wb_rd.wbd_err    ),
+         
+         // Master 2 Interface
+          .m2_wbd_dat_i            (m2_wbd_dat_i           ),
+          .m2_wbd_adr_i            (m2_wbd_adr_i           ),
+          .m2_wbd_sel_i            (m2_wbd_sel_i           ),
+          .m2_wbd_bl_i             (m2_wbd_bl_i            ),
+          .m2_wbd_bry_i            (m2_wbd_bry_i           ),
+          .m2_wbd_we_i             (m2_wbd_we_i            ),
+          .m2_wbd_cyc_i            (m2_wbd_cyc_i           ),
+          .m2_wbd_stb_i            (m2_wbd_stb_i           ),
+	  .m2_wbd_tid_i            (m2_wbd_tid_i           ),
+          .m2_wbd_dat_o            (m2_s0_wb_rd.wbd_dat    ),
+          .m2_wbd_ack_o            (m2_s0_wb_rd.wbd_ack    ),
+          .m2_wbd_lack_o           (m2_s0_wb_rd.wbd_lack   ),
+          .m2_wbd_err_o            (m2_s0_wb_rd.wbd_err    ),
 
-assign m1_wbd_dat_o  =  m1_wb_rd.wbd_dat;
-assign m1_wbd_ack_o  =  m1_wb_rd.wbd_ack;
-assign m1_wbd_lack_o =  m1_wb_rd.wbd_lack;
-assign m1_wbd_err_o  =  m1_wb_rd.wbd_err;
+         // Master 3 Interface
+          .m3_wbd_adr_i            (m3_wbd_adr_i           ),
+          .m3_wbd_sel_i            (m3_wbd_sel_i           ),
+          .m3_wbd_bl_i             (m3_wbd_bl_i            ),
+          .m3_wbd_bry_i            (m3_wbd_bry_i           ),
+          .m3_wbd_we_i             (m3_wbd_we_i            ),
+          .m3_wbd_cyc_i            (m3_wbd_cyc_i           ),
+          .m3_wbd_stb_i            (m3_wbd_stb_i           ),
+	  .m3_wbd_tid_i            (m3_wbd_tid_i           ),
+          .m3_wbd_dat_o            (m3_s0_wb_rd.wbd_dat    ),
+          .m3_wbd_ack_o            (m3_s0_wb_rd.wbd_ack    ),
+          .m3_wbd_lack_o           (m3_s0_wb_rd.wbd_lack   ),
+          .m3_wbd_err_o            (m3_s0_wb_rd.wbd_err    ),
+         
+         
+         // Slave  Interface
+          .s_wbd_dat_i            (s0_wb_rd.wbd_dat        ),
+          .s_wbd_ack_i            (s0_wb_rd.wbd_ack        ),
+          .s_wbd_lack_i           (s0_wb_rd.wbd_lack       ),
+          .s_wbd_dat_o            (s0_wb_wr.wbd_dat        ),
+          .s_wbd_adr_o            (s0_wb_wr.wbd_adr        ),
+          .s_wbd_bry_o            (s0_wb_wr.wbd_bry        ),
+          .s_wbd_bl_o             (s0_wb_wr.wbd_bl         ),
+          .s_wbd_sel_o            (s0_wb_wr.wbd_sel        ),
+          .s_wbd_we_o             (s0_wb_wr.wbd_we         ),  
+          .s_wbd_cyc_o            (s0_wb_wr.wbd_cyc        ),
+          .s_wbd_stb_o            (s0_wb_wr.wbd_stb        )
+         
+	);
 
-assign m2_wbd_dat_o  =  m2_wb_rd.wbd_dat;
-assign m2_wbd_ack_o  =  m2_wb_rd.wbd_ack;
-assign m2_wbd_lack_o =  m2_wb_rd.wbd_lack;
-assign m2_wbd_err_o  =  m2_wb_rd.wbd_err;
+// Target Port -1
+wb_slave_port  u_s1 (
 
-assign m3_wbd_dat_o  =  m3_wb_rd.wbd_dat;
-assign m3_wbd_ack_o  =  m3_wb_rd.wbd_ack;
-assign m3_wbd_lack_o =  m3_wb_rd.wbd_lack;
-assign m3_wbd_err_o  =  m3_wb_rd.wbd_err;
+          .clk_i                   (clk_i                  ), 
+          .rst_n                   (rst_n                  ),
+	  .cfg_slave_id            (TARGET_UART            ),
+
+         // Master 0 Interface
+          .m0_wbd_dat_i            (m0_wbd_dat_i           ),
+          .m0_wbd_adr_i            (m0_wbd_adr_i           ),
+          .m0_wbd_sel_i            (m0_wbd_sel_i           ),
+          .m0_wbd_we_i             (m0_wbd_we_i            ),
+          .m0_wbd_cyc_i            (m0_wbd_cyc_i           ),
+          .m0_wbd_stb_i            (m0_wbd_stb_i           ),
+	  .m0_wbd_tid_i            (m0_wbd_tid_i           ),
+          .m0_wbd_dat_o            (m0_s1_wb_rd.wbd_dat    ),
+          .m0_wbd_ack_o            (m0_s1_wb_rd.wbd_ack    ),
+          .m0_wbd_lack_o           (m0_s1_wb_rd.wbd_lack   ),
+          .m0_wbd_err_o            (m0_s1_wb_rd.wbd_err    ),
+         
+         // Master 1 Interface
+          .m1_wbd_dat_i            (m1_wbd_dat_i           ),
+          .m1_wbd_adr_i            (m1_wbd_adr_i           ),
+          .m1_wbd_sel_i            (m1_wbd_sel_i           ),
+          .m1_wbd_we_i             (m1_wbd_we_i            ),
+          .m1_wbd_cyc_i            (m1_wbd_cyc_i           ),
+          .m1_wbd_stb_i            (m1_wbd_stb_i           ),
+	  .m1_wbd_tid_i            (m1_wbd_tid_i           ),
+          .m1_wbd_dat_o            (m1_s1_wb_rd.wbd_dat    ),
+          .m1_wbd_ack_o            (m1_s1_wb_rd.wbd_ack    ),
+          .m1_wbd_lack_o           (m1_s1_wb_rd.wbd_lack   ),
+          .m1_wbd_err_o            (m1_s1_wb_rd.wbd_err    ),
+         
+         // Master 2 Interface
+          .m2_wbd_dat_i            (m2_wbd_dat_i           ),
+          .m2_wbd_adr_i            (m2_wbd_adr_i           ),
+          .m2_wbd_sel_i            (m2_wbd_sel_i           ),
+          .m2_wbd_bl_i             (m2_wbd_bl_i            ),
+          .m2_wbd_bry_i            (m2_wbd_bry_i           ),
+          .m2_wbd_we_i             (m2_wbd_we_i            ),
+          .m2_wbd_cyc_i            (m2_wbd_cyc_i           ),
+          .m2_wbd_stb_i            (m2_wbd_stb_i           ),
+	  .m2_wbd_tid_i            (m2_wbd_tid_i           ),
+          .m2_wbd_dat_o            (m2_s1_wb_rd.wbd_dat    ),
+          .m2_wbd_ack_o            (m2_s1_wb_rd.wbd_ack    ),
+          .m2_wbd_lack_o           (m2_s1_wb_rd.wbd_lack   ),
+          .m2_wbd_err_o            (m2_s1_wb_rd.wbd_err    ),
+
+         // Master 3 Interface
+          .m3_wbd_adr_i            (m3_wbd_adr_i           ),
+          .m3_wbd_sel_i            (m3_wbd_sel_i           ),
+          .m3_wbd_bl_i             (m3_wbd_bl_i            ),
+          .m3_wbd_bry_i            (m3_wbd_bry_i           ),
+          .m3_wbd_we_i             (m3_wbd_we_i            ),
+          .m3_wbd_cyc_i            (m3_wbd_cyc_i           ),
+          .m3_wbd_stb_i            (m3_wbd_stb_i           ),
+	  .m3_wbd_tid_i            (m3_wbd_tid_i           ),
+          .m3_wbd_dat_o            (m3_s1_wb_rd.wbd_dat    ),
+          .m3_wbd_ack_o            (m3_s1_wb_rd.wbd_ack    ),
+          .m3_wbd_lack_o           (m3_s1_wb_rd.wbd_lack   ),
+          .m3_wbd_err_o            (m3_s1_wb_rd.wbd_err    ),
+         
+         
+         // Slave  Interface
+          .s_wbd_dat_i            (s1_wb_rd.wbd_dat        ),
+          .s_wbd_ack_i            (s1_wb_rd.wbd_ack        ),
+          .s_wbd_lack_i           (s1_wb_rd.wbd_lack       ),
+          .s_wbd_dat_o            (s1_wb_wr.wbd_dat        ),
+          .s_wbd_adr_o            (s1_wb_wr.wbd_adr        ),
+          .s_wbd_bry_o            (s1_wb_wr.wbd_bry        ),
+          .s_wbd_bl_o             (s1_wb_wr.wbd_bl         ),
+          .s_wbd_sel_o            (s1_wb_wr.wbd_sel        ),
+          .s_wbd_we_o             (s1_wb_wr.wbd_we         ),  
+          .s_wbd_cyc_o            (s1_wb_wr.wbd_cyc        ),
+          .s_wbd_stb_o            (s1_wb_wr.wbd_stb        )
+         
+	);
+
+// Target Port -2
+wb_slave_port  u_s2 (
+
+          .clk_i                   (clk_i                  ), 
+          .rst_n                   (rst_n                  ),
+	  .cfg_slave_id            (TARGET_PINMUX          ),
+
+         // Master 0 Interface
+          .m0_wbd_dat_i            (m0_wbd_dat_i           ),
+          .m0_wbd_adr_i            (m0_wbd_adr_i           ),
+          .m0_wbd_sel_i            (m0_wbd_sel_i           ),
+          .m0_wbd_we_i             (m0_wbd_we_i            ),
+          .m0_wbd_cyc_i            (m0_wbd_cyc_i           ),
+          .m0_wbd_stb_i            (m0_wbd_stb_i           ),
+	  .m0_wbd_tid_i            (m0_wbd_tid_i           ),
+          .m0_wbd_dat_o            (m0_s2_wb_rd.wbd_dat    ),
+          .m0_wbd_ack_o            (m0_s2_wb_rd.wbd_ack    ),
+          .m0_wbd_lack_o           (m0_s2_wb_rd.wbd_lack   ),
+          .m0_wbd_err_o            (m0_s2_wb_rd.wbd_err    ),
+         
+         // Master 1 Interface
+          .m1_wbd_dat_i            (m1_wbd_dat_i           ),
+          .m1_wbd_adr_i            (m1_wbd_adr_i           ),
+          .m1_wbd_sel_i            (m1_wbd_sel_i           ),
+          .m1_wbd_we_i             (m1_wbd_we_i            ),
+          .m1_wbd_cyc_i            (m1_wbd_cyc_i           ),
+          .m1_wbd_stb_i            (m1_wbd_stb_i           ),
+	  .m1_wbd_tid_i            (m1_wbd_tid_i           ),
+          .m1_wbd_dat_o            (m1_s2_wb_rd.wbd_dat    ),
+          .m1_wbd_ack_o            (m1_s2_wb_rd.wbd_ack    ),
+          .m1_wbd_lack_o           (m1_s2_wb_rd.wbd_lack   ),
+          .m1_wbd_err_o            (m1_s2_wb_rd.wbd_err    ),
+         
+         // Master 2 Interface
+          .m2_wbd_dat_i            (m2_wbd_dat_i           ),
+          .m2_wbd_adr_i            (m2_wbd_adr_i           ),
+          .m2_wbd_sel_i            (m2_wbd_sel_i           ),
+          .m2_wbd_bl_i             (m2_wbd_bl_i            ),
+          .m2_wbd_bry_i            (m2_wbd_bry_i           ),
+          .m2_wbd_we_i             (m2_wbd_we_i            ),
+          .m2_wbd_cyc_i            (m2_wbd_cyc_i           ),
+          .m2_wbd_stb_i            (m2_wbd_stb_i           ),
+	  .m2_wbd_tid_i            (m2_wbd_tid_i           ),
+          .m2_wbd_dat_o            (m2_s2_wb_rd.wbd_dat    ),
+          .m2_wbd_ack_o            (m2_s2_wb_rd.wbd_ack    ),
+          .m2_wbd_lack_o           (m2_s2_wb_rd.wbd_lack   ),
+          .m2_wbd_err_o            (m2_s2_wb_rd.wbd_err    ),
+
+         // Master 3 Interface
+          .m3_wbd_adr_i            (m3_wbd_adr_i           ),
+          .m3_wbd_sel_i            (m3_wbd_sel_i           ),
+          .m3_wbd_bl_i             (m3_wbd_bl_i            ),
+          .m3_wbd_bry_i            (m3_wbd_bry_i           ),
+          .m3_wbd_we_i             (m3_wbd_we_i            ),
+          .m3_wbd_cyc_i            (m3_wbd_cyc_i           ),
+          .m3_wbd_stb_i            (m3_wbd_stb_i           ),
+	  .m3_wbd_tid_i            (m3_wbd_tid_i           ),
+          .m3_wbd_dat_o            (m3_s2_wb_rd.wbd_dat    ),
+          .m3_wbd_ack_o            (m3_s2_wb_rd.wbd_ack    ),
+          .m3_wbd_lack_o           (m3_s2_wb_rd.wbd_lack   ),
+          .m3_wbd_err_o            (m3_s2_wb_rd.wbd_err    ),
+         
+         
+         // Slave  Interface
+          .s_wbd_dat_i            (s2_wb_rd.wbd_dat        ),
+          .s_wbd_ack_i            (s2_wb_rd.wbd_ack        ),
+          .s_wbd_lack_i           (s2_wb_rd.wbd_lack       ),
+          .s_wbd_dat_o            (s2_wb_wr.wbd_dat        ),
+          .s_wbd_adr_o            (s2_wb_wr.wbd_adr        ),
+          .s_wbd_bry_o            (s2_wb_wr.wbd_bry        ),
+          .s_wbd_bl_o             (s2_wb_wr.wbd_bl         ),
+          .s_wbd_sel_o            (s2_wb_wr.wbd_sel        ),
+          .s_wbd_we_o             (s2_wb_wr.wbd_we         ),  
+          .s_wbd_cyc_o            (s2_wb_wr.wbd_cyc        ),
+          .s_wbd_stb_o            (s2_wb_wr.wbd_stb        )
+         
+	);
+
+/////////////////////////////////////////////////
+// Master-0 Mapping
+// ---------------------------------------------
+
+assign m0_wbd_dat_o  = m0_bus_rd.wbd_dat;
+assign m0_wbd_ack_o  = m0_bus_rd.wbd_ack;
+assign m0_wbd_lack_o = m0_bus_rd.wbd_lack;
+assign m0_wbd_err_o  = m0_bus_rd.wbd_err;
+
+always_comb begin
+     case(m0_wbd_tid_i)
+        TARGET_SPI_MEM:	   m0_bus_rd = m0_s0_wb_rd;
+        TARGET_SPI_REG:	   m0_bus_rd = m0_s0_wb_rd;
+        TARGET_UART:	   m0_bus_rd = m0_s1_wb_rd;
+        TARGET_PINMUX:	   m0_bus_rd = m0_s2_wb_rd;
+        default:           m0_bus_rd = m0_s0_wb_rd;
+     endcase			
+end
+
+/////////////////////////////////////////////////
+// Master-1 Mapping
+// ---------------------------------------------
+
+assign m1_wbd_dat_o  = m1_bus_rd.wbd_dat;
+assign m1_wbd_ack_o  = m1_bus_rd.wbd_ack;
+assign m1_wbd_lack_o = m1_bus_rd.wbd_lack;
+assign m1_wbd_err_o  = m1_bus_rd.wbd_err;
+
+always_comb begin
+     case(m1_wbd_tid_i)
+        TARGET_SPI_MEM:	   m1_bus_rd = m1_s0_wb_rd;
+        TARGET_SPI_REG:	   m1_bus_rd = m1_s0_wb_rd;
+        TARGET_UART:	   m1_bus_rd = m1_s1_wb_rd;
+        TARGET_PINMUX:	   m1_bus_rd = m1_s2_wb_rd;
+        default:           m1_bus_rd = m1_s0_wb_rd;
+     endcase			
+end
+
+/////////////////////////////////////////////////
+// Master-2 Mapping
+// ---------------------------------------------
+
+assign m2_wbd_dat_o  = m2_bus_rd.wbd_dat;
+assign m2_wbd_ack_o  = m2_bus_rd.wbd_ack;
+assign m2_wbd_lack_o = m2_bus_rd.wbd_lack;
+assign m2_wbd_err_o  = m2_bus_rd.wbd_err;
+
+always_comb begin
+     case(m2_wbd_tid_i)
+        TARGET_SPI_MEM:	   m2_bus_rd = m2_s0_wb_rd;
+        TARGET_SPI_REG:	   m2_bus_rd = m2_s0_wb_rd;
+        TARGET_UART:	   m2_bus_rd = m2_s1_wb_rd;
+        TARGET_PINMUX:	   m2_bus_rd = m2_s2_wb_rd;
+        default:           m2_bus_rd = m2_s0_wb_rd;
+     endcase			
+end
+
+/////////////////////////////////////////////////
+// Master-3 Mapping
+// ---------------------------------------------
+
+assign m3_wbd_dat_o  = m3_bus_rd.wbd_dat;
+assign m3_wbd_ack_o  = m3_bus_rd.wbd_ack;
+assign m3_wbd_lack_o = m3_bus_rd.wbd_lack;
+assign m3_wbd_err_o  = m3_bus_rd.wbd_err;
+
+always_comb begin
+     case(m3_wbd_tid_i)
+        TARGET_SPI_MEM:	   m3_bus_rd = m3_s0_wb_rd;
+        TARGET_SPI_REG:	   m3_bus_rd = m3_s0_wb_rd;
+        TARGET_UART:	   m3_bus_rd = m3_s1_wb_rd;
+        TARGET_PINMUX:	   m3_bus_rd = m3_s2_wb_rd;
+        default:           m3_bus_rd = m3_s0_wb_rd;
+     endcase			
+end
 
 //----------------------------------------
 // Slave Mapping
 // -------------------------------------
-// Masked Now and added stagging FF now
  assign  s0_wbd_dat_o =  s0_wb_wr.wbd_dat ;
  assign  s0_wbd_adr_o =  s0_wb_wr.wbd_adr ;
  assign  s0_wbd_sel_o =  s0_wb_wr.wbd_sel ;
@@ -439,93 +691,8 @@
  assign s2_wb_rd.wbd_err  = 1'b0; // s2_wbd_err_i ; - unused
 
 
-//
-// arbitor 
-//
-logic [1:0]  gnt;
-
-wb_arb	u_wb_arb(
-	.clk(clk_i), 
-	.rstn(rst_n),
-	.req({	m3_wbd_stb_i & !m3_wbd_lack_o,
-	        m2_wbd_stb_i & !m2_wbd_lack_o,
-		m1_wbd_stb_i & !m1_wbd_lack_o,
-		m0_wbd_stb_i & !m0_wbd_lack_o}),
-	.gnt(gnt)
-);
 
 
-// Generate Multiplexed Master Interface based on grant
-always_comb begin
-     case(gnt)
-        3'h0:	   m_bus_wr = m0_wb_wr;
-        3'h1:	   m_bus_wr = m1_wb_wr;
-        3'h2:	   m_bus_wr = m2_wb_wr;
-        3'h3:	   m_bus_wr = m3_wb_wr;
-        default:   m_bus_wr = m0_wb_wr;
-     endcase			
-end
-
-
-// Generate Multiplexed Slave Interface based on target Id
-wire [3:0] s_wbd_tid =  s_bus_wr.wbd_tid; // to fix iverilog warning
-always_comb begin
-     case(s_wbd_tid)
-        4'h0:	   s_bus_rd = s0_wb_rd;
-        4'h1:	   s_bus_rd = s1_wb_rd;
-        4'h2:	   s_bus_rd = s2_wb_rd;
-        default:   s_bus_rd = s0_wb_rd;
-     endcase			
-end
-
-
-// Connect Master => Slave
-assign  s0_wb_wr = (s_wbd_tid == 3'b000) ? s_bus_wr : 'h0;
-assign  s1_wb_wr = (s_wbd_tid == 3'b001) ? s_bus_wr : 'h0;
-assign  s2_wb_wr = (s_wbd_tid == 3'b010) ? s_bus_wr : 'h0;
-
-// Connect Slave to Master
-assign  m0_wb_rd = (gnt == 2'b00) ? m_bus_rd : 'h0;
-assign  m1_wb_rd = (gnt == 2'b01) ? m_bus_rd : 'h0;
-assign  m2_wb_rd = (gnt == 2'b10) ? m_bus_rd : 'h0;
-assign  m3_wb_rd = (gnt == 2'b11) ? m_bus_rd : 'h0;
-
-
-// Stagging FF to break write and read timing path
-sync_wbb u_sync_wbb(
-         .clk_i            (clk_i               ), 
-         .rst_n            (rst_n               ),
-         // WishBone Input master I/P
-         .wbm_dat_i      (m_bus_wr.wbd_dat    ),
-         .wbm_adr_i      (m_bus_wr.wbd_adr    ),
-         .wbm_sel_i      (m_bus_wr.wbd_sel    ),
-         .wbm_bl_i       (m_bus_wr.wbd_bl     ),
-         .wbm_bry_i      (m_bus_wr.wbd_bry    ),
-         .wbm_we_i       (m_bus_wr.wbd_we     ),
-         .wbm_cyc_i      (m_bus_wr.wbd_cyc    ),
-         .wbm_stb_i      (m_bus_wr.wbd_stb    ),
-         .wbm_tid_i      (m_bus_wr.wbd_tid    ),
-         .wbm_dat_o      (m_bus_rd.wbd_dat    ),
-         .wbm_ack_o      (m_bus_rd.wbd_ack    ),
-         .wbm_lack_o     (m_bus_rd.wbd_lack   ),
-         .wbm_err_o      (m_bus_rd.wbd_err    ),
-
-         // Slave Interface
-         .wbs_dat_i      (s_bus_rd.wbd_dat    ),
-         .wbs_ack_i      (s_bus_rd.wbd_ack    ),
-         .wbs_lack_i     (s_bus_rd.wbd_lack   ),
-         .wbs_err_i      (s_bus_rd.wbd_err    ),
-         .wbs_dat_o      (s_bus_wr.wbd_dat    ),
-         .wbs_adr_o      (s_bus_wr.wbd_adr    ),
-         .wbs_sel_o      (s_bus_wr.wbd_sel    ),
-         .wbs_bl_o       (s_bus_wr.wbd_bl     ),
-         .wbs_bry_o      (s_bus_wr.wbd_bry    ),
-         .wbs_we_o       (s_bus_wr.wbd_we     ),
-         .wbs_cyc_o      (s_bus_wr.wbd_cyc    ),
-         .wbs_stb_o      (s_bus_wr.wbd_stb    ),
-         .wbs_tid_o      (s_bus_wr.wbd_tid    )
-
-);
 
 
 endmodule
diff --git a/verilog/rtl/wb_interconnect/src/wb_slave_port.sv b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
new file mode 100644
index 0000000..87f0d4a
--- /dev/null
+++ b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
@@ -0,0 +1,289 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Wishbone interconnect for slave port                        ////
+////                                                              ////
+////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+////	1. This block implement simple round robine request       ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - Mar 2, 2022, Dinesh A                               ////
+//////////////////////////////////////////////////////////////////////
+
+
+
+module wb_slave_port  (
+         input logic		clk_i, 
+         input logic            rst_n,
+
+         input logic [3:0]      cfg_slave_id,
+
+         
+         // Master 0 Interface
+         input   logic	[31:0]	m0_wbd_dat_i,
+         input   logic  [31:0]	m0_wbd_adr_i,
+         input   logic  [3:0]	m0_wbd_sel_i,
+         input   logic  	m0_wbd_we_i,
+         input   logic  	m0_wbd_cyc_i,
+         input   logic  	m0_wbd_stb_i,
+         input   logic  [3:0]   m0_wbd_tid_i,
+         output  logic	[31:0]	m0_wbd_dat_o,
+         output  logic		m0_wbd_ack_o,
+         output  logic		m0_wbd_lack_o,
+         output  logic		m0_wbd_err_o,
+         
+         // Master 1 Interface
+         input	logic [31:0]	m1_wbd_dat_i,
+         input	logic [31:0]	m1_wbd_adr_i,
+         input	logic [3:0]	m1_wbd_sel_i,
+         input	logic 	        m1_wbd_we_i,
+         input	logic 	        m1_wbd_cyc_i,
+         input	logic 	        m1_wbd_stb_i,
+         input  logic [3:0]     m1_wbd_tid_i,
+         output	logic [31:0]	m1_wbd_dat_o,
+         output	logic 	        m1_wbd_ack_o,
+         output	logic 	        m1_wbd_lack_o,
+         output	logic 	        m1_wbd_err_o,
+         
+         // Master 2 Interface
+         input	logic [31:0]	m2_wbd_dat_i,
+         input	logic [31:0]	m2_wbd_adr_i,
+         input	logic [3:0]	m2_wbd_sel_i,
+         input	logic [9:0]	m2_wbd_bl_i,
+         input	logic    	m2_wbd_bry_i,
+         input	logic 	        m2_wbd_we_i,
+         input	logic 	        m2_wbd_cyc_i,
+         input	logic 	        m2_wbd_stb_i,
+         input  logic [3:0]     m2_wbd_tid_i,
+         output	logic [31:0]	m2_wbd_dat_o,
+         output	logic 	        m2_wbd_ack_o,
+         output	logic 	        m2_wbd_lack_o,
+         output	logic 	        m2_wbd_err_o,
+         
+         // Master 3 Interface
+         input	logic [31:0]	m3_wbd_adr_i,
+         input	logic [3:0]	m3_wbd_sel_i,
+         input	logic [9:0]	m3_wbd_bl_i,
+         input	logic    	m3_wbd_bry_i,
+         input	logic 	        m3_wbd_we_i,
+         input	logic 	        m3_wbd_cyc_i,
+         input	logic 	        m3_wbd_stb_i,
+         input  logic [3:0]     m3_wbd_tid_i,
+         output	logic [31:0]	m3_wbd_dat_o,
+         output	logic 	        m3_wbd_ack_o,
+         output	logic 	        m3_wbd_lack_o,
+         output	logic 	        m3_wbd_err_o,
+         
+         // Slave 0 Interface
+         input	logic [31:0]	s_wbd_dat_i,
+         input	logic 	        s_wbd_ack_i,
+         input	logic 	        s_wbd_lack_i,
+         output	logic [31:0]	s_wbd_dat_o,
+         output	logic [31:0]	s_wbd_adr_o,
+         output	logic [3:0]	s_wbd_sel_o,
+         output	logic [9:0]	s_wbd_bl_o,
+         output	logic 	        s_wbd_bry_o,
+         output	logic 	        s_wbd_we_o,
+         output	logic 	        s_wbd_cyc_o,
+         output	logic 	        s_wbd_stb_o
+
+	);
+
+// WishBone Wr Interface
+typedef struct packed { 
+  logic	[31:0]	wbd_dat;
+  logic  [31:0]	wbd_adr;
+  logic  [3:0]	wbd_sel;
+  logic  [9:0]	wbd_bl;
+  logic  	wbd_bry;
+  logic  	wbd_we;
+  logic  	wbd_cyc;
+  logic  	wbd_stb;
+  logic [3:0] 	wbd_tid; // target id
+} type_wb_wr_intf;
+
+// WishBone Rd Interface
+typedef struct packed { 
+  logic	[31:0]	wbd_dat;
+  logic  	wbd_ack;
+  logic  	wbd_lack;
+  logic  	wbd_err;
+} type_wb_rd_intf;
+
+
+// Master Write Interface
+type_wb_wr_intf  m0_wb_wr;
+type_wb_wr_intf  m1_wb_wr;
+type_wb_wr_intf  m2_wb_wr;
+type_wb_wr_intf  m3_wb_wr;
+
+// Master Read Interface
+type_wb_rd_intf  m0_wb_rd;
+type_wb_rd_intf  m1_wb_rd;
+type_wb_rd_intf  m2_wb_rd;
+type_wb_rd_intf  m3_wb_rd;
+
+wire m0_stb_i = (m0_wbd_stb_i & (m0_wbd_tid_i== cfg_slave_id));
+wire m1_stb_i = (m1_wbd_stb_i & (m1_wbd_tid_i== cfg_slave_id));
+wire m2_stb_i = (m2_wbd_stb_i & (m2_wbd_tid_i== cfg_slave_id));
+wire m3_stb_i = (m3_wbd_stb_i & (m3_wbd_tid_i== cfg_slave_id));
+
+type_wb_wr_intf  m_bus_wr;  // Multiplexed Master I/F
+type_wb_rd_intf  m_bus_rd;  // Multiplexed Slave I/F
+
+//----------------------------------------
+// Master Mapping
+// -------------------------------------
+assign m0_wb_wr.wbd_dat = m0_wbd_dat_i;
+assign m0_wb_wr.wbd_adr = {m0_wbd_adr_i[31:2],2'b00};
+assign m0_wb_wr.wbd_sel = m0_wbd_sel_i;
+assign m0_wb_wr.wbd_bl  = 'h1;
+assign m0_wb_wr.wbd_bry = 'b1;
+assign m0_wb_wr.wbd_we  = m0_wbd_we_i;
+assign m0_wb_wr.wbd_cyc = m0_wbd_cyc_i;
+assign m0_wb_wr.wbd_stb = m0_stb_i;
+assign m0_wb_wr.wbd_tid = m0_wbd_tid_i;
+
+assign m1_wb_wr.wbd_dat = m1_wbd_dat_i;
+assign m1_wb_wr.wbd_adr = {m1_wbd_adr_i[31:2],2'b00};
+assign m1_wb_wr.wbd_sel = m1_wbd_sel_i;
+assign m1_wb_wr.wbd_bl  = 'h1;
+assign m1_wb_wr.wbd_bry = 'b1;
+assign m1_wb_wr.wbd_we  = m1_wbd_we_i;
+assign m1_wb_wr.wbd_cyc = m1_wbd_cyc_i;
+assign m1_wb_wr.wbd_stb = m1_stb_i;
+assign m1_wb_wr.wbd_tid = m1_wbd_tid_i;
+
+assign m2_wb_wr.wbd_dat = m2_wbd_dat_i;
+assign m2_wb_wr.wbd_adr = {m2_wbd_adr_i[31:2],2'b00};
+assign m2_wb_wr.wbd_sel = m2_wbd_sel_i;
+assign m2_wb_wr.wbd_bl  = m2_wbd_bl_i;
+assign m2_wb_wr.wbd_bry = m2_wbd_bry_i;
+assign m2_wb_wr.wbd_we  = m2_wbd_we_i;
+assign m2_wb_wr.wbd_cyc = m2_wbd_cyc_i;
+assign m2_wb_wr.wbd_stb = m2_stb_i;
+assign m2_wb_wr.wbd_tid = m2_wbd_tid_i;
+
+assign m3_wb_wr.wbd_dat = 'h0;
+assign m3_wb_wr.wbd_adr = {m3_wbd_adr_i[31:2],2'b00};
+assign m3_wb_wr.wbd_sel = m3_wbd_sel_i;
+assign m3_wb_wr.wbd_bl  = m3_wbd_bl_i;
+assign m3_wb_wr.wbd_bry = m3_wbd_bry_i;
+assign m3_wb_wr.wbd_we  = m3_wbd_we_i;
+assign m3_wb_wr.wbd_cyc = m3_wbd_cyc_i;
+assign m3_wb_wr.wbd_stb = m3_stb_i;
+assign m3_wb_wr.wbd_tid = m3_wbd_tid_i;
+
+assign m0_wbd_dat_o  =  m0_wb_rd.wbd_dat;
+assign m0_wbd_ack_o  =  m0_wb_rd.wbd_ack;
+assign m0_wbd_lack_o =  m0_wb_rd.wbd_lack;
+assign m0_wbd_err_o  =  m0_wb_rd.wbd_err;
+
+assign m1_wbd_dat_o  =  m1_wb_rd.wbd_dat;
+assign m1_wbd_ack_o  =  m1_wb_rd.wbd_ack;
+assign m1_wbd_lack_o =  m1_wb_rd.wbd_lack;
+assign m1_wbd_err_o  =  m1_wb_rd.wbd_err;
+
+assign m2_wbd_dat_o  =  m2_wb_rd.wbd_dat;
+assign m2_wbd_ack_o  =  m2_wb_rd.wbd_ack;
+assign m2_wbd_lack_o =  m2_wb_rd.wbd_lack;
+assign m2_wbd_err_o  =  m2_wb_rd.wbd_err;
+
+assign m3_wbd_dat_o  =  m3_wb_rd.wbd_dat;
+assign m3_wbd_ack_o  =  m3_wb_rd.wbd_ack;
+assign m3_wbd_lack_o =  m3_wb_rd.wbd_lack;
+assign m3_wbd_err_o  =  m3_wb_rd.wbd_err;
+
+//
+// arbitor 
+//
+logic [1:0]  gnt;
+wb_arb	u_wb_arb(
+	.clk(clk_i), 
+	.rstn(rst_n),
+	.req({	m3_stb_i & !m3_wbd_lack_o,
+	        m2_stb_i & !m2_wbd_lack_o,
+		m1_stb_i & !m1_wbd_lack_o,
+		m0_stb_i & !m0_wbd_lack_o}),
+	.gnt(gnt)
+);
+
+// Generate Multiplexed Master Interface based on grant
+always_comb begin
+     case(gnt)
+        3'h0:	   m_bus_wr = m0_wb_wr;
+        3'h1:	   m_bus_wr = m1_wb_wr;
+        3'h2:	   m_bus_wr = m2_wb_wr;
+        3'h3:	   m_bus_wr = m3_wb_wr;
+        default:   m_bus_wr = m0_wb_wr;
+     endcase			
+end
+
+// Stagging FF to break write and read timing path
+sync_wbb u_sync_wbb(
+         .clk_i            (clk_i               ), 
+         .rst_n            (rst_n               ),
+         // WishBone Input master I/P
+         .wbm_dat_i      (m_bus_wr.wbd_dat    ),
+         .wbm_adr_i      (m_bus_wr.wbd_adr    ),
+         .wbm_sel_i      (m_bus_wr.wbd_sel    ),
+         .wbm_bl_i       (m_bus_wr.wbd_bl     ),
+         .wbm_bry_i      (m_bus_wr.wbd_bry    ),
+         .wbm_we_i       (m_bus_wr.wbd_we     ),
+         .wbm_cyc_i      (m_bus_wr.wbd_cyc    ),
+         .wbm_stb_i      (m_bus_wr.wbd_stb    ),
+         .wbm_tid_i      (m_bus_wr.wbd_tid    ),
+         .wbm_dat_o      (m_bus_rd.wbd_dat    ),
+         .wbm_ack_o      (m_bus_rd.wbd_ack    ),
+         .wbm_lack_o     (m_bus_rd.wbd_lack   ),
+         .wbm_err_o      (m_bus_rd.wbd_err    ),
+
+         // Slave Interface
+         .wbs_dat_i      (s_wbd_dat_i    ),
+         .wbs_ack_i      (s_wbd_ack_i    ),
+         .wbs_lack_i     (s_wbd_lack_i   ),
+         .wbs_err_i      (1'b0           ),
+         .wbs_dat_o      (s_wbd_dat_o    ),
+         .wbs_adr_o      (s_wbd_adr_o    ),
+         .wbs_sel_o      (s_wbd_sel_o    ),
+         .wbs_bl_o       (s_wbd_bl_o     ),
+         .wbs_bry_o      (s_wbd_bry_o    ),
+         .wbs_we_o       (s_wbd_we_o     ),
+         .wbs_cyc_o      (s_wbd_cyc_o    ),
+         .wbs_stb_o      (s_wbd_stb_o    ),
+         .wbs_tid_o      (               )
+
+);
+
+// Connect Slave to Master
+assign  m0_wb_rd = (gnt == 2'b00) ? m_bus_rd : 'h0;
+assign  m1_wb_rd = (gnt == 2'b01) ? m_bus_rd : 'h0;
+assign  m2_wb_rd = (gnt == 2'b10) ? m_bus_rd : 'h0;
+assign  m3_wb_rd = (gnt == 2'b11) ? m_bus_rd : 'h0;
+
+endmodule