diff --git a/.gitmodules b/.gitmodules
index 4798126..a20fefd 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,4 @@
 [submodule "caravel"]
 	path = caravel
 	url = https://github.com/efabless/caravel-lite.git
+	branch = mpw-two
diff --git a/openlane/glbl_cfg/config.tcl b/openlane/glbl_cfg/config.tcl
index 3dbd66b..bbdfe91 100755
--- a/openlane/glbl_cfg/config.tcl
+++ b/openlane/glbl_cfg/config.tcl
@@ -5,6 +5,8 @@
 # Name
 set ::env(DESIGN_NAME) glbl_cfg
 
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
@@ -56,3 +58,5 @@
 set ::env(GLB_RT_MAXLAYER) 4
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
diff --git a/openlane/sdram/config.tcl b/openlane/sdram/config.tcl
index 45febad..bea0aba 100755
--- a/openlane/sdram/config.tcl
+++ b/openlane/sdram/config.tcl
@@ -6,11 +6,14 @@
 set ::env(DESIGN_NAME) sdrc_top
 
 
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
 set ::env(CLOCK_PORT) "wb_clk_i sdram_clk"
 
+set ::env(SYNTH_MAX_FANOUT) 4
 
 # Sources
 # -------
diff --git a/openlane/spi_master/config.tcl b/openlane/spi_master/config.tcl
index 2e9aa93..6e48edb 100755
--- a/openlane/spi_master/config.tcl
+++ b/openlane/spi_master/config.tcl
@@ -6,6 +6,9 @@
 
 set ::env(DESIGN_NAME) spim_top
 
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
 set ::env(CLOCK_PORT) "mclk"
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index 568494b..7daaadb 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl
@@ -5,6 +5,8 @@
 # Name
 set ::env(DESIGN_NAME) scr1_top_wb
 
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
@@ -75,7 +77,6 @@
 
 
 set ::env(PL_ROUTABILITY_DRIVEN) 1
-#set ::env(PL_BASIC_PLACEMENT) "1"
 
 set ::env(FP_IO_VEXTEND) 4
 set ::env(FP_IO_HEXTEND) 4
diff --git a/openlane/uart/config.tcl b/openlane/uart/config.tcl
index b43cb74..e48f62c 100644
--- a/openlane/uart/config.tcl
+++ b/openlane/uart/config.tcl
@@ -6,11 +6,14 @@
 set ::env(DESIGN_NAME) uart_core
 
 
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
 set ::env(CLOCK_PORT) "app_clk"
 
+set ::env(SYNTH_MAX_FANOUT) 4
 
 # Sources
 # -------
@@ -63,3 +66,5 @@
 set ::env(GLB_RT_MAXLAYER) 4
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 3908fab..7661525 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -26,6 +26,10 @@
 #section end
 
 # User Configurations
+#
+set ::env(DESIGN_IS_CORE) 1
+set ::env(FP_PDN_CORE_RING) 1
+
 
 ## Source Verilog Files
 set ::env(VERILOG_FILES) "\
@@ -83,7 +87,7 @@
 
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
 
-set ::env(GLB_RT_MAXLAYER) 5
+set ::env(GLB_RT_MAXLAYER) 6
 
 set ::env(FP_PDN_CHECK_NODES) 0
 
@@ -109,51 +113,4 @@
 
 set ::env(PL_DIAMOND_SEARCH_HEIGHT) "250"
 
-set ::env(GLB_RT_OBS) " \
-           met1 300.000000  2700.000000 700.000000  3300.000000, \
-           met2 300.000000  2700.000000 700.000000  3300.000000, \
-           met3 300.000000  2700.000000 700.000000  3300.000000, \
-           met4 300.000000  2700.000000 700.000000  3300.000000, \
-           met5 300.000000  2700.000000 700.000000  3300.000000, \
-           met1 1000.000000 2700.000000 1700.000000 3200.000000, \
-           met2 1000.000000 2700.000000 1700.000000 3200.000000, \
-           met3 1000.000000 2700.000000 1700.000000 3200.000000, \
-           met4 1000.000000 2700.000000 1700.000000 3200.000000, \
-           met5 1000.000000 2700.000000 1700.000000 3200.000000, \
-           met1 2000.000000 2700.000000 2300.000000 3100.000000, \
-           met2 2000.000000 2700.000000 2300.000000 3100.000000, \
-           met3 2000.000000 2700.000000 2300.000000 3100.000000, \
-           met4 2000.000000 2700.000000 2300.000000 3100.000000, \
-           met5 2000.000000 2700.000000 2300.000000 3100.000000, \
-           met1 300.000000  800.000000  1800.000000  2000.000000, \
-           met2 300.000000  800.000000  1800.000000  2000.000000, \
-           met3 300.000000  800.000000  1800.000000  2000.000000, \
-           met4 300.000000  800.000000  1800.000000  2000.000000, \
-           met5 300.000000  800.000000  1800.000000  2000.000000, \
-           met1 2000.000000  1600.000000  2300.000000  2000.000000, \
-           met2 2000.000000  1600.000000  2300.000000  2000.000000, \
-           met3 2000.000000  1600.000000  2300.000000  2000.000000, \
-           met4 2000.000000  1600.000000  2300.000000  2000.000000, \
-           met5 2000.000000  1600.000000  2300.000000  2000.000000, \
-           met1 300.0000 450.0000 650.0000 500.0000, \
-           met2 300.0000 450.0000 650.0000 500.0000, \
-           met3 300.0000 450.0000 650.0000 500.0000, \
-           met4 300.0000 450.0000 650.0000 500.0000, \
-           met5 300.0000 450.0000 650.0000 500.0000, \
-           met1 300.0000 1000.0000 650.0000 1100.0000, \
-           met2 300.0000 1000.0000 650.0000 1100.0000, \
-           met3 300.0000 1000.0000 650.0000 1100.0000, \
-           met4 300.0000 1000.0000 650.0000 1100.0000, \
-           met5 300.0000 1000.0000 650.0000 1100.0000, \
-           met1 300.0000 1700.0000 350.0000 1750.0000, \
-           met2 300.0000 1700.0000 350.0000 1750.0000, \
-           met3 300.0000 1700.0000 350.0000 1750.0000, \
-           met4 300.0000 1700.0000 350.0000 1750.0000, \
-           met5 300.0000 1700.0000 350.0000 1750.0000, \
-           met1 300.0000 3150.0000 350.0000 3200.0000, \
-           met2 300.0000 3150.0000 350.0000 3200.0000, \
-           met3 300.0000 3150.0000 350.0000 3200.0000, \
-           met4 300.0000 3150.0000 350.0000 3200.0000, \
-           met5 300.0000 3150.0000 350.0000 3200.0000 \
-           "
 
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 26d4b30..9ef1988 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,7 +1,7 @@
-u_core.u_riscv_top	       300	       800	       N
-u_core.u_glbl_cfg              2000            2700            N
-u_core.u_uart_core             2000            1600            N
-u_core.u_intercon              300             2300            N
 u_core.u_spi_master            300             2700            N
 u_core.u_sdram_ctrl            1000            2700            N
+u_core.u_glbl_cfg              2000            2700            N
+u_core.u_riscv_top	       500	       800	       N
+u_core.u_uart_core             2200            1600            N
+u_core.u_intercon              300             2300            N
 u_core.u_wb_host               300             300             N
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 6706f2a..d7c4471 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -6,6 +6,9 @@
 
 set ::env(DESIGN_NAME) wb_host
 
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
 set ::env(CLOCK_PORT) "wbm_clk_i wbs_clk_i"
@@ -55,3 +58,5 @@
 set ::env(GLB_RT_MAXLAYER) 4
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 
+set ::env(DIODE_INSERTION_STRATEGY) 5
+
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index dca5594..488bc22 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -4,6 +4,7 @@
 
 #E
 wbs_clk_i     0000 0 2   
+wbs_clk_out   
 
 
 
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 144a5f2..9fcb282 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -5,7 +5,9 @@
 # Name
 set ::env(DESIGN_NAME) wb_interconnect
 
-#set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
@@ -37,33 +39,26 @@
 # Floorplanning
 # -------------
 
-#set ::env(PL_BASIC_PLACEMENT) 1
-#set ::env(FP_DEF_TEMPLATE) $script_dir/floorplan.def
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 2000 200"
+set ::env(DIE_AREA) "0 0 2200 200"
 
 
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
 
-set ::env(FP_PDN_VPITCH) 50
 #set ::env(PDN_CFG) $script_dir/pdn.tcl
 
-set ::env(FP_VERTICAL_HALO) 6
-set ::env(PL_TARGET_DENSITY) 0.32
-set ::env(PL_TARGET_DENSITY_CELLS) 0.2
-set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
-set ::env(CELL_PAD) 4
 
-set ::env(GLB_RT_ADJUSTMENT) 0
-set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
-set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
-set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
-set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
-set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
-set ::env(GLB_RT_TILES) 14
-set ::env(GLB_RT_MAXLAYER) 5
+set ::env(PL_ROUTABILITY_DRIVEN) 1
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+
+set ::env(GLB_RT_MAXLAYER) 4
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
-
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index 120e132..d9a23b2 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -114,7 +114,9 @@
 m0_wbd_err_o        
 m0_wbd_cyc_i        
 
-m1_wbd_stb_i        0500 0 2
+
+
+m1_wbd_stb_i        200 0 2
 m1_wbd_we_i         
 m1_wbd_adr_i\[31\]  
 m1_wbd_adr_i\[30\]  
@@ -220,7 +222,113 @@
 m1_wbd_err_o        
 m1_wbd_cyc_i        
 
-s3_wbd_stb_o        1700 0 2
+m2_wbd_stb_i        0700 0 2
+m2_wbd_we_i         
+m2_wbd_adr_i\[31\]  
+m2_wbd_adr_i\[30\]  
+m2_wbd_adr_i\[29\]  
+m2_wbd_adr_i\[28\]  
+m2_wbd_adr_i\[27\]  
+m2_wbd_adr_i\[26\]  
+m2_wbd_adr_i\[25\]  
+m2_wbd_adr_i\[24\]  
+m2_wbd_adr_i\[23\]  
+m2_wbd_adr_i\[22\]  
+m2_wbd_adr_i\[21\]  
+m2_wbd_adr_i\[20\]  
+m2_wbd_adr_i\[19\]  
+m2_wbd_adr_i\[18\]  
+m2_wbd_adr_i\[17\]  
+m2_wbd_adr_i\[16\]  
+m2_wbd_adr_i\[15\]  
+m2_wbd_adr_i\[14\]  
+m2_wbd_adr_i\[13\]  
+m2_wbd_adr_i\[12\]  
+m2_wbd_adr_i\[11\]  
+m2_wbd_adr_i\[10\]  
+m2_wbd_adr_i\[9\]   
+m2_wbd_adr_i\[8\]   
+m2_wbd_adr_i\[7\]   
+m2_wbd_adr_i\[6\]   
+m2_wbd_adr_i\[5\]   
+m2_wbd_adr_i\[4\]   
+m2_wbd_adr_i\[3\]   
+m2_wbd_adr_i\[2\]   
+m2_wbd_adr_i\[1\]   
+m2_wbd_adr_i\[0\]   
+m2_wbd_sel_i\[3\]   
+m2_wbd_sel_i\[2\]   
+m2_wbd_sel_i\[1\]   
+m2_wbd_sel_i\[0\]   
+m2_wbd_dat_i\[31\]  
+m2_wbd_dat_i\[30\]  
+m2_wbd_dat_i\[29\]  
+m2_wbd_dat_i\[28\]  
+m2_wbd_dat_i\[27\]  
+m2_wbd_dat_i\[26\]  
+m2_wbd_dat_i\[25\]  
+m2_wbd_dat_i\[24\]  
+m2_wbd_dat_i\[23\]  
+m2_wbd_dat_i\[22\]  
+m2_wbd_dat_i\[21\]  
+m2_wbd_dat_i\[20\]  
+m2_wbd_dat_i\[19\]  
+m2_wbd_dat_i\[18\]  
+m2_wbd_dat_i\[17\]  
+m2_wbd_dat_i\[16\]  
+m2_wbd_dat_i\[15\]  
+m2_wbd_dat_i\[14\]  
+m2_wbd_dat_i\[13\]  
+m2_wbd_dat_i\[12\]  
+m2_wbd_dat_i\[11\]  
+m2_wbd_dat_i\[10\]  
+m2_wbd_dat_i\[9\]   
+m2_wbd_dat_i\[8\]   
+m2_wbd_dat_i\[7\]   
+m2_wbd_dat_i\[6\]   
+m2_wbd_dat_i\[5\]   
+m2_wbd_dat_i\[4\]   
+m2_wbd_dat_i\[3\]   
+m2_wbd_dat_i\[2\]   
+m2_wbd_dat_i\[1\]   
+m2_wbd_dat_i\[0\]   
+m2_wbd_dat_o\[31\]  
+m2_wbd_dat_o\[30\]  
+m2_wbd_dat_o\[29\]  
+m2_wbd_dat_o\[28\]  
+m2_wbd_dat_o\[27\]  
+m2_wbd_dat_o\[26\]  
+m2_wbd_dat_o\[25\]  
+m2_wbd_dat_o\[24\]  
+m2_wbd_dat_o\[23\]  
+m2_wbd_dat_o\[22\]  
+m2_wbd_dat_o\[21\]  
+m2_wbd_dat_o\[20\]  
+m2_wbd_dat_o\[19\]  
+m2_wbd_dat_o\[18\]  
+m2_wbd_dat_o\[17\]  
+m2_wbd_dat_o\[16\]  
+m2_wbd_dat_o\[15\]  
+m2_wbd_dat_o\[14\]  
+m2_wbd_dat_o\[13\]  
+m2_wbd_dat_o\[12\]  
+m2_wbd_dat_o\[11\]  
+m2_wbd_dat_o\[10\]  
+m2_wbd_dat_o\[9\]   
+m2_wbd_dat_o\[8\]   
+m2_wbd_dat_o\[7\]   
+m2_wbd_dat_o\[6\]   
+m2_wbd_dat_o\[5\]   
+m2_wbd_dat_o\[4\]   
+m2_wbd_dat_o\[3\]   
+m2_wbd_dat_o\[2\]   
+m2_wbd_dat_o\[1\]   
+m2_wbd_dat_o\[0\]   
+m2_wbd_ack_o        
+m2_wbd_err_o        
+m2_wbd_cyc_i        
+
+s3_wbd_stb_o        1900 0 2
 s3_wbd_we_o         
 s3_wbd_adr_o\[7\]   
 s3_wbd_adr_o\[6\]   
@@ -542,109 +650,3 @@
 s2_wbd_ack_i        
 s2_wbd_cyc_o        
 
-#W
-m2_wbd_stb_i        0 0 2
-m2_wbd_we_i         
-m2_wbd_adr_i\[31\]  
-m2_wbd_adr_i\[30\]  
-m2_wbd_adr_i\[29\]  
-m2_wbd_adr_i\[28\]  
-m2_wbd_adr_i\[27\]  
-m2_wbd_adr_i\[26\]  
-m2_wbd_adr_i\[25\]  
-m2_wbd_adr_i\[24\]  
-m2_wbd_adr_i\[23\]  
-m2_wbd_adr_i\[22\]  
-m2_wbd_adr_i\[21\]  
-m2_wbd_adr_i\[20\]  
-m2_wbd_adr_i\[19\]  
-m2_wbd_adr_i\[18\]  
-m2_wbd_adr_i\[17\]  
-m2_wbd_adr_i\[16\]  
-m2_wbd_adr_i\[15\]  
-m2_wbd_adr_i\[14\]  
-m2_wbd_adr_i\[13\]  
-m2_wbd_adr_i\[12\]  
-m2_wbd_adr_i\[11\]  
-m2_wbd_adr_i\[10\]  
-m2_wbd_adr_i\[9\]   
-m2_wbd_adr_i\[8\]   
-m2_wbd_adr_i\[7\]   
-m2_wbd_adr_i\[6\]   
-m2_wbd_adr_i\[5\]   
-m2_wbd_adr_i\[4\]   
-m2_wbd_adr_i\[3\]   
-m2_wbd_adr_i\[2\]   
-m2_wbd_adr_i\[1\]   
-m2_wbd_adr_i\[0\]   
-m2_wbd_sel_i\[3\]   
-m2_wbd_sel_i\[2\]   
-m2_wbd_sel_i\[1\]   
-m2_wbd_sel_i\[0\]   
-m2_wbd_dat_i\[31\]  
-m2_wbd_dat_i\[30\]  
-m2_wbd_dat_i\[29\]  
-m2_wbd_dat_i\[28\]  
-m2_wbd_dat_i\[27\]  
-m2_wbd_dat_i\[26\]  
-m2_wbd_dat_i\[25\]  
-m2_wbd_dat_i\[24\]  
-m2_wbd_dat_i\[23\]  
-m2_wbd_dat_i\[22\]  
-m2_wbd_dat_i\[21\]  
-m2_wbd_dat_i\[20\]  
-m2_wbd_dat_i\[19\]  
-m2_wbd_dat_i\[18\]  
-m2_wbd_dat_i\[17\]  
-m2_wbd_dat_i\[16\]  
-m2_wbd_dat_i\[15\]  
-m2_wbd_dat_i\[14\]  
-m2_wbd_dat_i\[13\]  
-m2_wbd_dat_i\[12\]  
-m2_wbd_dat_i\[11\]  
-m2_wbd_dat_i\[10\]  
-m2_wbd_dat_i\[9\]   
-m2_wbd_dat_i\[8\]   
-m2_wbd_dat_i\[7\]   
-m2_wbd_dat_i\[6\]   
-m2_wbd_dat_i\[5\]   
-m2_wbd_dat_i\[4\]   
-m2_wbd_dat_i\[3\]   
-m2_wbd_dat_i\[2\]   
-m2_wbd_dat_i\[1\]   
-m2_wbd_dat_i\[0\]   
-m2_wbd_dat_o\[31\]  
-m2_wbd_dat_o\[30\]  
-m2_wbd_dat_o\[29\]  
-m2_wbd_dat_o\[28\]  
-m2_wbd_dat_o\[27\]  
-m2_wbd_dat_o\[26\]  
-m2_wbd_dat_o\[25\]  
-m2_wbd_dat_o\[24\]  
-m2_wbd_dat_o\[23\]  
-m2_wbd_dat_o\[22\]  
-m2_wbd_dat_o\[21\]  
-m2_wbd_dat_o\[20\]  
-m2_wbd_dat_o\[19\]  
-m2_wbd_dat_o\[18\]  
-m2_wbd_dat_o\[17\]  
-m2_wbd_dat_o\[16\]  
-m2_wbd_dat_o\[15\]  
-m2_wbd_dat_o\[14\]  
-m2_wbd_dat_o\[13\]  
-m2_wbd_dat_o\[12\]  
-m2_wbd_dat_o\[11\]  
-m2_wbd_dat_o\[10\]  
-m2_wbd_dat_o\[9\]   
-m2_wbd_dat_o\[8\]   
-m2_wbd_dat_o\[7\]   
-m2_wbd_dat_o\[6\]   
-m2_wbd_dat_o\[5\]   
-m2_wbd_dat_o\[4\]   
-m2_wbd_dat_o\[3\]   
-m2_wbd_dat_o\[2\]   
-m2_wbd_dat_o\[1\]   
-m2_wbd_dat_o\[0\]   
-m2_wbd_ack_o        
-m2_wbd_err_o        
-m2_wbd_cyc_i        
diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
index f301c47..cddcb14 100644
--- a/signoff/glbl_cfg/final_summary_report.csv
+++ b/signoff/glbl_cfg/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h4m50s,0h3m3s,47033.33333333334,0.12,23516.66666666667,37,549.19,2822,0,0,0,0,0,0,0,1,0,-1,0,141778,20879,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,114388749,0.0,22.5,30.02,0.23,-1,-1,2676,2872,476,672,0,0,0,2822,1,0,3,9,474,0,3,571,588,548,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h5m48s,0h3m34s,47033.33333333334,0.12,23516.66666666667,41,556.01,2822,0,0,0,0,0,0,0,2,0,-1,0,156023,24257,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,114388749,0.0,31.41,31.61,0.34,-1,-1,2676,2872,476,672,0,0,0,2822,1,0,3,9,474,0,3,571,588,548,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
index 9bc481d..5971cda 100644
--- a/signoff/sdram/final_summary_report.csv
+++ b/signoff/sdram/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h9m21s,0h5m21s,37194.28571428572,0.35,18597.14285714286,25,636.34,6509,0,0,0,0,0,0,0,10,0,-1,0,288514,47774,-3.59,-3.59,-3.59,-3.59,-4.29,-3.59,-3.59,-3.59,-3.59,-4.29,227214856,0.0,19.78,15.07,1.47,-1,-1,6444,6672,1140,1368,0,0,0,6509,132,107,80,108,350,212,30,2197,1189,1088,29,350,4248,0,4598,69.97900629811058,14.29,10,AREA 0,5,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h8m14s,0h4m9s,39520.0,0.35,19760.0,26,632.18,6916,0,0,0,0,0,0,0,10,0,-1,0,290277,48450,-3.59,-3.59,-3.59,-3.59,-4.13,-3.59,-3.59,-3.59,-3.59,-4.13,232393261,0.0,19.76,15.43,1.33,-1,-1,6851,7079,1140,1368,0,0,0,6916,132,107,80,108,350,212,30,2197,1189,1088,27,350,4248,0,4598,70.7714083510262,14.129999999999999,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
index 5e8e8e6..e0a826c 100644
--- a/signoff/spi_master/final_summary_report.csv
+++ b/signoff/spi_master/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h9m29s,0h6m55s,25416.66666666667,0.24,12708.333333333336,19,587.51,3050,0,0,0,0,0,0,0,5,0,-1,0,162786,26689,-1.48,-1.48,-1.55,-1.55,-2.28,-86.69,-86.69,-158.7,-158.7,-255.68,121954058,0.0,9.59,19.86,0.04,-1,-1,3016,3128,433,545,0,0,0,3050,83,0,92,79,1118,89,19,920,527,458,28,424,2889,0,3313,81.43322475570034,12.28,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h8m3s,0h5m35s,25416.66666666667,0.24,12708.333333333336,19,591.97,3050,0,0,0,0,0,0,0,5,0,-1,0,162786,26689,-1.48,-1.48,-1.55,-1.55,-2.28,-86.69,-86.69,-158.7,-158.7,-255.68,121954058,0.0,9.59,19.86,0.04,-1,-1,3016,3128,433,545,0,0,0,3050,83,0,92,79,1118,89,19,920,527,458,28,424,2889,0,3313,81.43322475570034,12.28,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index 7830877..1c146a1 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h55m24s,0h32m1s,34420.0,1.8,17210.0,23,1196.24,30978,0,0,0,0,0,0,0,84,2,-1,0,1618669,250632,-0.3,-0.3,-0.44,-0.44,-0.73,-12.11,-12.11,-18.83,-18.83,-29.4,1353757569,0.0,19.59,15.78,4.41,0.64,-1,30864,31102,2807,3045,0,0,0,30978,631,0,685,2044,4015,2105,1318,7432,2838,2786,94,866,22836,0,23702,93.19664492078284,10.73,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h57m56s,0h33m31s,34420.0,1.8,17210.0,23,1202.9,30978,0,0,0,0,0,0,0,82,2,-1,0,1618491,250568,-0.3,-0.3,-0.44,-0.44,-0.73,-12.11,-12.11,-18.83,-18.83,-29.4,1353757569,0.0,19.59,15.78,4.41,0.64,-1,30864,31102,2807,3045,0,0,0,30978,631,0,685,2044,4015,2105,1318,7432,2838,2786,94,866,22836,0,23702,93.19664492078284,10.73,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/uart/final_summary_report.csv b/signoff/uart/final_summary_report.csv
index 6d20ca0..e37c172 100644
--- a/signoff/uart/final_summary_report.csv
+++ b/signoff/uart/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart,uart_core,uart,Flow_completed,0h5m17s,0h3m27s,43433.333333333336,0.12,21716.666666666668,32,525.34,2606,0,0,0,0,0,0,0,0,0,-1,0,82639,18254,-0.57,-0.57,-0.5,-0.5,-0.67,-40.55,-40.55,-39.96,-39.96,-45.73,60185370,0.0,13.32,18.01,0.0,-1,-1,2605,2625,454,474,0,0,0,2606,59,0,30,41,182,125,26,685,435,396,16,278,1410,0,1688,93.72071227741331,10.67,10,AREA 0,5,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/uart,uart_core,uart,Flow_completed,0h6m30s,0h4m1s,46133.33333333334,0.12,23066.66666666667,35,545.72,2768,0,0,0,0,0,0,0,1,0,-1,0,91647,20662,-0.67,-0.67,-0.47,-0.47,-0.73,-37.32,-37.32,-45.39,-45.39,-68.63,62910936,0.0,19.11,18.79,0.06,-1,-1,2767,2787,454,474,0,0,0,2768,59,0,30,41,182,125,26,685,435,396,17,278,1410,0,1688,93.19664492078284,10.73,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 1eda607..b4b1f0b 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h48m32s,0h6m22s,3.1133250311332503,10.2784,1.5566625155666252,0,574.53,16,0,0,0,0,0,0,65,0,23,-1,6,1272729,5759,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,2.81,4.04,0.21,1.09,-1,852,1470,843,1461,0,0,0,16,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h38m39s,0h5m4s,1.362079701120797,10.2784,0.6810398505603985,0,575.3,7,0,0,0,0,0,0,0,0,0,-1,-1,1229122,6052,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,2.38,3.7,0.68,1.42,0.27,842,1460,842,1460,0,0,0,7,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index d8a99da..ca1bdbe 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h7m33s,0h4m35s,35490.0,0.2,17745.0,24,610.75,3549,0,0,0,0,0,0,0,22,0,-1,0,305549,29594,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,264347444,0.0,37.57,10.91,25.23,-1,-1,3270,3912,529,1171,0,0,0,3549,85,0,5,9,30,27,13,915,660,813,16,130,2343,137,2610,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h9m40s,0h6m56s,30470.0,0.2,15235.0,25,613.2,3047,0,0,0,0,0,0,0,1,0,-1,0,335681,32215,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,282222295,0.0,47.7,13.38,29.5,-1,-1,2769,3411,458,1100,0,0,0,3047,83,0,5,8,30,27,9,776,590,739,15,130,2343,0,2473,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index fcbedf8..751e1e1 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h7m29s,0h3m50s,6465.0,0.4,3232.5,6,563.65,1293,0,0,0,0,0,0,0,9,0,0,0,468040,17506,0.0,0.0,0.0,0.0,-1.15,0.0,0.0,0.0,0.0,-29.57,415332616,0.0,44.92,11.38,31.98,0.1,-1,1043,1616,204,777,0,0,0,1293,244,0,75,15,111,0,0,180,431,418,11,130,4719,0,4849,89.68609865470852,11.15,10,AREA 0,4,50,1,50,153.18,0.32,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h10m43s,0h6m55s,5877.272727272727,0.44,2938.6363636363635,5,580.27,1293,0,0,0,0,0,0,0,2,0,-1,0,496849,21106,0.0,0.0,0.0,0.0,-0.83,0.0,0.0,0.0,0.0,-79.64,424741802,0.0,31.77,8.67,21.85,-1,-1,1043,1616,204,777,0,0,0,1293,244,0,75,15,111,0,0,180,431,418,11,130,5189,0,5319,92.33610341643582,10.83,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/verilog/rtl/digital_core/src/digital_core.sv b/verilog/rtl/digital_core/src/digital_core.sv
index 7e76212..53dcb62 100644
--- a/verilog/rtl/digital_core/src/digital_core.sv
+++ b/verilog/rtl/digital_core/src/digital_core.sv
@@ -59,6 +59,12 @@
 ////          u_risc_top - test_mode & test_rst_n                 ////
 ////          u_intercon - s*_wbd_err_i                           ////
 ////          unused wb_cti_i is removed from u_sdram_ctrl        ////
+////    0.7 - 28th June 2021, Dinesh A                            ////
+////          wb_interconnect master port are interchanged for    ////
+////          better physical placement.                          ////
+////          m0 - External HOST                                  ////
+////          m1 - RISC IMEM                                      ////
+////          m2 - RISC DMEM                                      ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -288,6 +294,7 @@
        .wbm_err_o        (                     ),  
 
     // Slave Port
+       .wbs_clk_out      (wbd_clk_int          ),  
        .wbs_clk_i        (wbd_clk_int          ),  
        .wbs_cyc_o        (wbd_int_cyc_i        ),  
        .wbs_stb_o        (wbd_int_stb_i        ),  
@@ -450,39 +457,39 @@
 wb_interconnect  u_intercon (
          .clk_i         (wbd_clk_int           ), 
          .rst_n         (wbd_int_rst_n         ),
+
+         // Master 0 Interface
+         .m0_wbd_dat_i  (wbd_int_dat_i         ),
+         .m0_wbd_adr_i  (wbd_int_adr_i         ),
+         .m0_wbd_sel_i  (wbd_int_sel_i         ),
+         .m0_wbd_we_i   (wbd_int_we_i          ),
+         .m0_wbd_cyc_i  (wbd_int_cyc_i         ),
+         .m0_wbd_stb_i  (wbd_int_stb_i         ),
+         .m0_wbd_dat_o  (wbd_int_dat_o         ),
+         .m0_wbd_ack_o  (wbd_int_ack_o         ),
+         .m0_wbd_err_o  (wbd_int_err_o         ),
          
          // Master 0 Interface
-         .m0_wbd_dat_i  (wbd_riscv_imem_dat_i  ),
-         .m0_wbd_adr_i  (wbd_riscv_imem_adr_i  ),
-         .m0_wbd_sel_i  (wbd_riscv_imem_sel_i  ),
-         .m0_wbd_we_i   (wbd_riscv_imem_we_i   ),
-         .m0_wbd_cyc_i  (wbd_riscv_imem_stb_i  ),
-         .m0_wbd_stb_i  (wbd_riscv_imem_stb_i  ),
-         .m0_wbd_dat_o  (wbd_riscv_imem_dat_o  ),
-         .m0_wbd_ack_o  (wbd_riscv_imem_ack_o  ),
-         .m0_wbd_err_o  (wbd_riscv_imem_err_o  ),
+         .m1_wbd_dat_i  (wbd_riscv_imem_dat_i  ),
+         .m1_wbd_adr_i  (wbd_riscv_imem_adr_i  ),
+         .m1_wbd_sel_i  (wbd_riscv_imem_sel_i  ),
+         .m1_wbd_we_i   (wbd_riscv_imem_we_i   ),
+         .m1_wbd_cyc_i  (wbd_riscv_imem_stb_i  ),
+         .m1_wbd_stb_i  (wbd_riscv_imem_stb_i  ),
+         .m1_wbd_dat_o  (wbd_riscv_imem_dat_o  ),
+         .m1_wbd_ack_o  (wbd_riscv_imem_ack_o  ),
+         .m1_wbd_err_o  (wbd_riscv_imem_err_o  ),
          
          // Master 1 Interface
-         .m1_wbd_dat_i  (wbd_riscv_dmem_dat_i  ),
-         .m1_wbd_adr_i  (wbd_riscv_dmem_adr_i  ),
-         .m1_wbd_sel_i  (wbd_riscv_dmem_sel_i  ),
-         .m1_wbd_we_i   (wbd_riscv_dmem_we_i   ),
-         .m1_wbd_cyc_i  (wbd_riscv_dmem_stb_i  ),
-         .m1_wbd_stb_i  (wbd_riscv_dmem_stb_i  ),
-         .m1_wbd_dat_o  (wbd_riscv_dmem_dat_o  ),
-         .m1_wbd_ack_o  (wbd_riscv_dmem_ack_o  ),
-         .m1_wbd_err_o  (wbd_riscv_dmem_err_o  ),
-         
-         // Master 2 Interface
-         .m2_wbd_dat_i  (wbd_int_dat_i  ),
-         .m2_wbd_adr_i  (wbd_int_adr_i  ),
-         .m2_wbd_sel_i  (wbd_int_sel_i  ),
-         .m2_wbd_we_i   (wbd_int_we_i   ),
-         .m2_wbd_cyc_i  (wbd_int_cyc_i  ),
-         .m2_wbd_stb_i  (wbd_int_stb_i  ),
-         .m2_wbd_dat_o  (wbd_int_dat_o  ),
-         .m2_wbd_ack_o  (wbd_int_ack_o  ),
-         .m2_wbd_err_o  (wbd_int_err_o  ),
+         .m2_wbd_dat_i  (wbd_riscv_dmem_dat_i  ),
+         .m2_wbd_adr_i  (wbd_riscv_dmem_adr_i  ),
+         .m2_wbd_sel_i  (wbd_riscv_dmem_sel_i  ),
+         .m2_wbd_we_i   (wbd_riscv_dmem_we_i   ),
+         .m2_wbd_cyc_i  (wbd_riscv_dmem_stb_i  ),
+         .m2_wbd_stb_i  (wbd_riscv_dmem_stb_i  ),
+         .m2_wbd_dat_o  (wbd_riscv_dmem_dat_o  ),
+         .m2_wbd_ack_o  (wbd_riscv_dmem_ack_o  ),
+         .m2_wbd_err_o  (wbd_riscv_dmem_err_o  ),
          
          
          // Slave 0 Interface
diff --git a/verilog/rtl/lib/async_wb.sv b/verilog/rtl/lib/async_wb.sv
index 48bce58..6174875 100644
--- a/verilog/rtl/lib/async_wb.sv
+++ b/verilog/rtl/lib/async_wb.sv
@@ -18,6 +18,11 @@
 ////  Revision :                                                  ////
 ////    0.1 - 25th Feb 2021, Dinesh A                             ////
 ////          initial version                                     ////
+////    0.2 - 28th Feb 2021, Dinesh A                             ////
+////          reduced the response FIFO path depth to 2 as        ////
+////          return path used by only read logic and read is     ////
+////          blocking request and expect only one location will  ////
+////          be used                                             ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -165,7 +170,10 @@
                    .rd_data       (s_cmd_rd_data     )
 	     );
 
-async_fifo #(.W(33), .DP(4), .WR_FAST(1), .RD_FAST(1)) u_resp_if (
+
+// Response used only read path, read is blocking access, expect
+// only one location used in return path - reduced the depth to 2
+async_fifo #(.W(33), .DP(2), .WR_FAST(1), .RD_FAST(1)) u_resp_if (
 	           // Sync w.r.t WR clock
 	           .wr_clk        (wbs_clk_i          ),
                    .wr_reset_n    (wbs_rst_n          ),
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index c642421..0dc98b6 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -66,7 +66,8 @@
        output  logic               wbm_err_o        ,  // error
 
     // Slave Port
-       output  logic               wbs_clk_i        ,  // System clock
+       output  logic               wbs_clk_out      ,  // System clock
+       input   logic               wbs_clk_i        ,  // System clock
        output  logic               wbs_cyc_o        ,  // strobe/request
        output  logic               wbs_stb_o        ,  // strobe/request
        output  logic [31:0]        wbs_adr_o        ,  // address
@@ -120,7 +121,7 @@
 assign wbm_rst_n = !wbm_rst_i;
 assign wbs_rst_n = !wbm_rst_i;
 
-assign wbs_clk_i =  wbm_clk_i;
+assign wbs_clk_out =  wbm_clk_i;
 
 assign  wbm_dat_o   = (reg_sel) ? reg_rdata : wbm_dat_int;  // data input
 assign  wbm_ack_o   = (reg_sel) ? reg_ack   : wbm_ack_int; // acknowlegement
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index e6c9f40..9ef5574 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -28,6 +28,12 @@
 ////    0.4 - 27th June 2021, Dinesh A                            ////
 ////          unused tie off at digital core level brought inside ////
 ////          to avoid core level power hook up                   ////
+////    0.5 - 28th June 2021, Dinesh A                            ////
+////          interchange the Master port for better physical     ////
+////          placement                                           ////
+////          m0: external host                                   ////
+////          m1: risc imem                                       ////
+////          m2: risc dmem                                       ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -195,26 +201,6 @@
 
 type_wb_wr_intf  s_bus_wr;  // Multiplexed Master I/F
 type_wb_rd_intf  s_bus_rd;  // Multiplexed Slave I/F
-//------------------------------
-// RISC Data Memory Map
-// 0x0000_0000 to 0x0FFF_FFFF  - SPI FLASH MEMORY
-// 0x1000_0000 to 0x1000_00FF  - SPI REGISTER
-// 0x2000_0000 to 0x2FFF_FFFF  - SDRAM
-// 0x3000_0000 to 0x3000_00FF  - GLOBAL REGISTER
-// 0x3000_0000 to 0x3001_00FF  - UART Register
-//-----------------------------
-// 
-wire [3:0] m0_wbd_tid_i     = (m0_wbd_adr_i[31:28] ==  4'b0000 ) ? 4'b0000 :
-                              (m0_wbd_adr_i[31:28] ==  4'b0001 ) ? 4'b0000 :
-                              (m0_wbd_adr_i[31:28] ==  4'b0010 ) ? 4'b0001 :
-                              (m0_wbd_adr_i[31:16] == 16'h3000 ) ? 4'b0010 : 
-                              (m0_wbd_adr_i[31:16] == 16'h3001 ) ? 4'b0011 : 4'b0000; 
-
-wire [3:0] m1_wbd_tid_i     = (m1_wbd_adr_i[31:28] ==  4'b0000 ) ? 4'b0000 :
-                              (m1_wbd_adr_i[31:28] ==  4'b0001 ) ? 4'b0000 :
-                              (m1_wbd_adr_i[31:28] ==  4'b0010 ) ? 4'b0001 : 
-                              (m1_wbd_adr_i[31:16] == 16'h3000 ) ? 4'b0010 : 
-                              (m1_wbd_adr_i[31:16] == 16'h3001 ) ? 4'b0011 : 4'b0000; 
 
 
 //-------------------------------------------------------------------
@@ -227,12 +213,32 @@
 // 0x3080_0000 to 0x3080_00FF  - WB HOST (This decoding happens at wb_host block)
 // ---------------------------------------------------------------------------
 //
-wire [3:0] m2_wbd_tid_i       = (m2_wbd_adr_i[31:28] == 4'b0000  ) ? 4'b0000 :
-                                (m2_wbd_adr_i[31:28] == 4'b0001  ) ? 4'b0000 :
-                                (m2_wbd_adr_i[31:28] == 4'b0010  ) ? 4'b0001 :
-                                (m2_wbd_adr_i[31:16] == 16'h3000 ) ? 4'b0010 : 
-                                (m2_wbd_adr_i[31:16] == 16'h3001 ) ? 4'b0011 : 4'b0000; 
+wire [3:0] m0_wbd_tid_i       = (m0_wbd_adr_i[31:28] == 4'b0000  ) ? 4'b0000 :
+                                (m0_wbd_adr_i[31:28] == 4'b0001  ) ? 4'b0000 :
+                                (m0_wbd_adr_i[31:28] == 4'b0010  ) ? 4'b0001 :
+                                (m0_wbd_adr_i[31:16] == 16'h3000 ) ? 4'b0010 : 
+                                (m0_wbd_adr_i[31:16] == 16'h3001 ) ? 4'b0011 : 4'b0000; 
 
+//------------------------------
+// RISC Data Memory Map
+// 0x0000_0000 to 0x0FFF_FFFF  - SPI FLASH MEMORY
+// 0x1000_0000 to 0x1000_00FF  - SPI REGISTER
+// 0x2000_0000 to 0x2FFF_FFFF  - SDRAM
+// 0x3000_0000 to 0x3000_00FF  - GLOBAL REGISTER
+// 0x3000_0000 to 0x3001_00FF  - UART Register
+//-----------------------------
+// 
+wire [3:0] m1_wbd_tid_i     = (m1_wbd_adr_i[31:28] ==  4'b0000 ) ? 4'b0000 :
+                              (m1_wbd_adr_i[31:28] ==  4'b0001 ) ? 4'b0000 :
+                              (m1_wbd_adr_i[31:28] ==  4'b0010 ) ? 4'b0001 :
+                              (m1_wbd_adr_i[31:16] == 16'h3000 ) ? 4'b0010 : 
+                              (m1_wbd_adr_i[31:16] == 16'h3001 ) ? 4'b0011 : 4'b0000; 
+
+wire [3:0] m2_wbd_tid_i     = (m2_wbd_adr_i[31:28] ==  4'b0000 ) ? 4'b0000 :
+                              (m2_wbd_adr_i[31:28] ==  4'b0001 ) ? 4'b0000 :
+                              (m2_wbd_adr_i[31:28] ==  4'b0010 ) ? 4'b0001 : 
+                              (m2_wbd_adr_i[31:16] == 16'h3000 ) ? 4'b0010 : 
+                              (m2_wbd_adr_i[31:16] == 16'h3001 ) ? 4'b0011 : 4'b0000; 
 //----------------------------------------
 // Master Mapping
 // -------------------------------------