diff --git a/Makefile b/Makefile
index 67a92ac..b89e69f 100644
--- a/Makefile
+++ b/Makefile
@@ -20,6 +20,7 @@
 MCW_ROOT?=$(PWD)/mgmt_core_wrapper
 SIM?=RTL
 DUMP?=OFF
+RISC_CORE ?=0
 
 export SKYWATER_COMMIT=c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
 export OPEN_PDKS_COMMIT=7519dfb04400f224f140749cda44ee7de6f5e095
@@ -41,6 +42,22 @@
 	CARAVEL_TAG := $(MPW_TAG)
 endif
 
+# Install caravel as submodule, (1): submodule, (0): clone
+SUBMODULE?=1
+
+#RISCV COMPLIANCE test Environment
+COREMARK_DIR   = verilog/dv/riscv_regress/dependencies/coremark
+RISCV_COMP_DIR = verilog/dv/riscv_regress/dependencies/riscv-compliance
+RISCV_TEST_DIR = verilog/dv/riscv_regress/dependencies/riscv-tests
+
+COREMARK_REPO   =  https://github.com/eembc/coremark
+RISCV_COMP_REPO =  https://github.com/riscv/riscv-compliance
+RISCV_TEST_REPO =  https://github.com/riscv/riscv-tests
+
+COREMARK_BRANCH   =  7f420b6bdbff436810ef75381059944e2b0d79e8
+RISCV_COMP_BRANCH =  d51259b2a949be3af02e776c39e135402675ac9b
+RISCV_TEST_BRANCH =  e30978a71921159aec38eeefd848fca4ed39a826
+
 # Include Caravel Makefile Targets
 .PHONY: % : check-caravel
 %:
@@ -75,8 +92,8 @@
 dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf)
 
 TARGET_PATH=$(shell pwd)
-verify_command="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} && make"
-dv_base_dependencies=
+verify_command="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} RISC_CORE=${RISC_CORE} && make"
+dv_base_dependencies= ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo
 docker_run_verify=\
 	docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
 		-v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
@@ -93,14 +110,8 @@
 .PHONY: harden
 harden: $(blocks)
 
-.PHONY: verify-all-rtl
-verify-all-rtl: $(dv-targets-rtl)
-
-.PHONY: verify-all-gl
-verify-all-gl: $(dv-targets-gl)
-
-.PHONY: verify-all-gl-sdf
-verify-all-gl-sdf: $(dv-targets-gl-sdf)
+.PHONY: verify
+verify: $(dv-targets)
 
 $(dv-targets-rtl): SIM=RTL
 $(dv-targets-rtl): verify-%-rtl: $(dv_base_dependencies)
@@ -201,6 +212,27 @@
 		exit 1; \
 	fi
 
+check-coremark_repo:
+	@if [ ! -d "$(COREMARK_DIR)" ]; then \
+		echo "Installing Core Mark Repo.."; \
+		git clone $(COREMARK_REPO) $(COREMARK_DIR); \
+		cd $(COREMARK_DIR); git checkout $(COREMARK_BRANCH); \
+	fi
+
+check-riscv_comp_repo:
+	@if [ ! -d "$(RISCV_COMP_DIR)" ]; then \
+		echo "Installing Risc V Complance Repo.."; \
+		git clone $(RISCV_COMP_REPO) $(RISCV_COMP_DIR); \
+		cd $(RISCV_COMP_DIR); git checkout $(RISCV_COMP_BRANCH); \
+	fi
+
+check-riscv_test_repo:
+	@if [ ! -d "$(RISCV_TEST_DIR)" ]; then \
+		echo "Installing RiscV Test Repo.."; \
+		git clone $(RISCV_TEST_REPO) $(RISCV_TEST_DIR); \
+		cd $(RISCV_TEST_DIR); git checkout $(RISCV_TEST_BRANCH); \
+	fi
+
 zip:
 	gzip -f def/*
 	gzip -f lef/*
@@ -223,6 +255,3 @@
 help:
 	cd $(CARAVEL_ROOT) && $(MAKE) help
 	@$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
-
-
-
diff --git a/verilog/dv/c_func/inc/pwm.h b/verilog/dv/c_func/inc/pwm.h
new file mode 100644
index 0000000..580a9a8
--- /dev/null
+++ b/verilog/dv/c_func/inc/pwm.h
@@ -0,0 +1,8 @@
+
+void	InitTimers         ();
+void	InitTimersSafe     ();     //doesn't init timers responsible for time keeping functions
+void	pwmWrite           (uint8_t pin, uint8_t val);
+void	pwmWriteHR         (uint8_t pin, uint16_t val);   //accepts a 16 bit value and maps it down to the timer for maximum resolution
+bool	SetPinFrequency    (int8_t pin, uint32_t frequency);
+bool	SetPinFrequencySafe(int8_t pin, uint32_t frequency);	//does not set timers responsible for time keeping functions
+float	GetPinResolution(uint8_t pin);  //gets the PWM resolution of a pin in base 2, 0 is returned if the pin is not connected to a timer
diff --git a/verilog/dv/c_func/inc/user_reg_map.h b/verilog/dv/c_func/inc/user_reg_map.h
new file mode 100644
index 0000000..4508fb2
--- /dev/null
+++ b/verilog/dv/c_func/inc/user_reg_map.h
@@ -0,0 +1,38 @@
+
+
+//-------------------------------------
+// PinMux Register
+// ------------------------------------
+#define reg_pinmux_chip_id           (*(volatile uint32_t*)0x30020000)  // reg_0  - Chip ID
+#define reg_pinmux_gbl_cfg0          (*(volatile uint32_t*)0x30020004)  // reg_1  - Global Config-2
+#define reg_pinmux_gbl_cfg1          (*(volatile uint32_t*)0x30020008)  // reg_2  - Global Config-1
+#define reg_pinmux_gbl_intr_msk      (*(volatile uint32_t*)0x3002000C)  // reg_3  - Global Interrupt Mask
+#define reg_pinmux_gbl_intr          (*(volatile uint32_t*)0x30020010)  // reg_4  - Global Interrupt
+#define reg_pinmux_gpio_idata        (*(volatile uint32_t*)0x30020014)  // reg_5  - GPIO Data In
+#define reg_pinmux_gpio_odata        (*(volatile uint32_t*)0x30020018)  // reg_6  - GPIO Data Out
+#define reg_pinmux_gpio_dsel         (*(volatile uint32_t*)0x3002001C)  // reg_7  - GPIO Direction Select
+#define reg_pinmux_gpio_type         (*(volatile uint32_t*)0x30020020)  // reg_8  - GPIO TYPE - Static/Waveform
+#define reg_pinmux_gpio_intr_stat    (*(volatile uint32_t*)0x30020024)  // reg_9  - GPIO Interrupt status
+#define reg_pinmux_gpio_intr_clr     (*(volatile uint32_t*)0x30020024)  // reg_9  - GPIO Interrupt Clear
+#define reg_pinmux_gpio_intr_set     (*(volatile uint32_t*)0x30020028)  // reg_10 - GPIO Interrupt Set
+#define reg_pinmux_gpio_intr_mask    (*(volatile uint32_t*)0x3002002C)  // reg_11 - GPIO Interrupt Mask
+#define reg_pinmux_gpio_pos_intr     (*(volatile uint32_t*)0x30020030)  // reg_12 - GPIO Posedge Interrupt
+#define reg_pinmux_gpio_neg_intr     (*(volatile uint32_t*)0x30020034)  // reg_13 - GPIO Neg Interrupt
+#define reg_pinmux_gpio_multi_func   (*(volatile uint32_t*)0x30020038)  // reg_14 - GPIO Multi Function
+#define reg_pinmux_soft_reg_0        (*(volatile uint32_t*)0x3002003C)  // reg_15 - Soft Register
+#define reg_pinmux_cfg_pwm0          (*(volatile uint32_t*)0x30020040)  // reg_16 - PWM Reg-0
+#define reg_pinmux_cfg_pwm1          (*(volatile uint32_t*)0x30020044)  // reg_17 - PWM Reg-1
+#define reg_pinmux_cfg_pwm2          (*(volatile uint32_t*)0x30020048)  // reg_18 - PWM Reg-2
+#define reg_pinmux_cfg_pwm3          (*(volatile uint32_t*)0x3002004C)  // reg_19 - PWM Reg-3
+#define reg_pinmux_cfg_pwm4          (*(volatile uint32_t*)0x30020050)  // reg_20 - PWM Reg-4
+#define reg_pinmux_cfg_pwm5          (*(volatile uint32_t*)0x30020054)  // reg_21 - PWM Reg-5
+#define reg_pinmux_soft_reg_1        (*(volatile uint32_t*)0x30020058)  // reg_22 - Sof Register
+#define reg_pinmux_soft_reg_2        (*(volatile uint32_t*)0x3002005C)  // reg_23 - Sof Register
+#define reg_pinmux_soft_reg_3        (*(volatile uint32_t*)0x30020060)  // reg_24 - Sof Register
+#define reg_pinmux_soft_reg_4        (*(volatile uint32_t*)0x30020064)  // reg_25 - Sof Register
+#define reg_pinmux_soft_reg_5        (*(volatile uint32_t*)0x30020068)  // reg_26 - Sof Register
+#define reg_pinmux_soft_reg_6        (*(volatile uint32_t*)0x3002006C)  // reg_27 - Sof Register
+#define reg_pinmux_cfg_timer0        (*(volatile uint32_t*)0x30020070)  // reg_28 - Timer-0
+#define reg_pinmux_cfg_timer1        (*(volatile uint32_t*)0x30020074)  // reg_28 - Timer-1
+#define reg_pinmux_cfg_timer2        (*(volatile uint32_t*)0x30020078)  // reg_28 - Timer-2
+
diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master/uart_master_tb.v
index 004f8d7..1442c8c 100644
--- a/verilog/dv/uart_master/uart_master_tb.v
+++ b/verilog/dv/uart_master/uart_master_tb.v
@@ -24,7 +24,6 @@
 `include "spiflash.v"
 `include "uart_agent.v"
 `include "user_reg_map.v"
-`define ADDR_SPACE_PINMUX  32'h3002_0000
 
 module uart_master_tb;
 	reg clock;
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index 148833e..c9bcd8b 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -155,7 +155,7 @@
    repeat (100) @(posedge clock);  
 
     @(posedge  clock);
-    $display("---------- Initialize I2C Master: %x ----------",`ADDR_SPACE_I2CM); 
+    $display("---------- Initialize I2C Master ----------"); 
 
     //Wrire Prescale registers
      wb_user_core_write(`ADDR_SPACE_I2CM+(8'h0<<2),8'hC7);  
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index 2fb66d0..aed3a9d 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -130,8 +130,6 @@
 		       output  logic           pulse1m_mclk,
 	               output  logic [31:0]    pinmux_debug
 
-
-
    );