diff --git a/openlane/sdram/sta.tcl b/openlane/sdram/sta.tcl
new file mode 100644
index 0000000..f4f630d
--- /dev/null
+++ b/openlane/sdram/sta.tcl
@@ -0,0 +1,134 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+
+set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(CURRENT_NETLIST) /project/openlane/sdram/runs/sdram/results/lvs/sdrc_top.lvs.powered.v
+set ::env(DESIGN_NAME) "sdrc_top"
+set ::env(CURRENT_SPEF) /project/openlane/sdram/runs/sdram/results/routing/sdrc_top.spef
+set ::env(BASE_SDC_FILE) "/project/openlane/sdram/base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+read_liberty -min $::env(LIB_FASTEST)
+read_liberty -max $::env(LIB_SLOWEST)
+read_verilog $::env(CURRENT_NETLIST)
+link_design  $::env(DESIGN_NAME)
+
+read_spef  $::env(CURRENT_SPEF)
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup  -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+report_power 
+report_checks -unique -slack_max -0.0 -group_count 100 
+report_checks -unique -slack_min -0.0 -group_count 100 
+report_checks -path_delay min_max 
+report_checks -group_count 100  -slack_max -0.01  > timing.rpt
+
+report_checks -group_count 100  -slack_min -0.01 >> timing.rpt
+
+report_checks -to [get_port io_out[0]]  -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[1]]  -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[2]]  -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[3]]  -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[4]]  -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[5]]  -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[6]]  -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[7]]  -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[8]]  -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[9]]  -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[10]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[11]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[12]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[13]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[14]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[15]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[16]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[17]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[18]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[19]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[20]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[21]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[22]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[23]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[24]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[25]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[26]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[27]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[28]] -path_delay min >> timing.rpt
+
+report_checks -to [get_port io_out[0]]  -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[1]]  -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[2]]  -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[3]]  -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[4]]  -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[5]]  -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[6]]  -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[7]]  -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[8]]  -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[9]]  -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[10]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[11]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[12]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[13]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[14]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[15]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[16]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[17]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[18]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[19]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[20]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[21]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[22]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[23]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[24]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[25]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[26]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[27]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[28]] -path_delay max >> timing.rpt
+
+report_checks -from [get_port io_in[0]] -path_delay max >> timing.rpt
+report_checks -from [get_port io_in[1]] -path_delay max >> timing.rpt
+report_checks -from [get_port io_in[2]] -path_delay max >> timing.rpt
+report_checks -from [get_port io_in[3]] -path_delay max >> timing.rpt
+report_checks -from [get_port io_in[4]] -path_delay max >> timing.rpt
+report_checks -from [get_port io_in[5]] -path_delay max >> timing.rpt
+report_checks -from [get_port io_in[6]] -path_delay max >> timing.rpt
+report_checks -from [get_port io_in[7]] -path_delay max >> timing.rpt
+
+report_checks -from [get_port io_in[0]] -path_delay min >> timing.rpt
+report_checks -from [get_port io_in[1]] -path_delay min >> timing.rpt
+report_checks -from [get_port io_in[2]] -path_delay min >> timing.rpt
+report_checks -from [get_port io_in[3]] -path_delay min >> timing.rpt
+report_checks -from [get_port io_in[4]] -path_delay min >> timing.rpt
+report_checks -from [get_port io_in[5]] -path_delay min >> timing.rpt
+report_checks -from [get_port io_in[6]] -path_delay min >> timing.rpt
+report_checks -from [get_port io_in[7]] -path_delay min >> timing.rpt
diff --git a/openlane/spi_master/pin_order.cfg b/openlane/spi_master/pin_order.cfg
index fc7556c..e2ec32c 100644
--- a/openlane/spi_master/pin_order.cfg
+++ b/openlane/spi_master/pin_order.cfg
@@ -16,10 +16,8 @@
 io_in\[2\]         
 io_out\[2\]        
 io_oeb\[2\]  
-io_in\[1\]         
 io_out\[1\]        
 io_oeb\[1\]  
-io_in\[0\]         
 io_out\[0\]        
 io_oeb\[0\]  
 
diff --git a/openlane/spi_master/sta.tcl b/openlane/spi_master/sta.tcl
new file mode 100644
index 0000000..af91726
--- /dev/null
+++ b/openlane/spi_master/sta.tcl
@@ -0,0 +1,88 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(CURRENT_NETLIST) /project/openlane/spi_master/runs/spi_master/results/lvs/spim_top.lvs.powered.v
+set ::env(DESIGN_NAME) "spim_top"
+set ::env(CURRENT_SPEF) /project/openlane/spi_master/runs/spi_master/results/routing/spim_top.spef
+set ::env(BASE_SDC_FILE) "/project/openlane/spi_master/base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+read_liberty -min $::env(LIB_FASTEST)
+read_liberty -max $::env(LIB_SLOWEST)
+read_verilog $::env(CURRENT_NETLIST)
+link_design  $::env(DESIGN_NAME)
+
+read_spef  $::env(CURRENT_SPEF)
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup  -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+report_power 
+report_checks -unique -slack_max -0.0 -group_count 100 
+report_checks -unique -slack_min -0.0 -group_count 100 
+report_checks -path_delay min_max 
+report_checks -group_count 100  -slack_max -0.01  > timing.rpt
+
+report_checks -group_count 100  -slack_min -0.01 >> timing.rpt
+
+
+report_checks -to [get_port io_out[5]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[4]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[3]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[2]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_out[1]] -path_delay min >> timing.rpt
+
+report_checks -to [get_port io_out[5]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[4]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[3]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[2]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_out[1]] -path_delay max >> timing.rpt
+
+report_checks -to [get_port io_oeb[5]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_oeb[4]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_oeb[3]] -path_delay min >> timing.rpt
+report_checks -to [get_port io_oeb[2]] -path_delay min >> timing.rpt
+
+report_checks -to [get_port io_oeb[5]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_oeb[4]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_oeb[3]] -path_delay max >> timing.rpt
+report_checks -to [get_port io_oeb[2]] -path_delay max >> timing.rpt
+
+report_checks -from [get_port io_in[5]] -path_delay min >> timing.rpt
+report_checks -from [get_port io_in[4]] -path_delay min >> timing.rpt
+report_checks -from [get_port io_in[3]] -path_delay min >> timing.rpt
+report_checks -from [get_port io_in[2]] -path_delay min >> timing.rpt
+
+report_checks -from [get_port io_in[5]] -path_delay max >> timing.rpt
+report_checks -from [get_port io_in[4]] -path_delay max >> timing.rpt
+report_checks -from [get_port io_in[3]] -path_delay max >> timing.rpt
+report_checks -from [get_port io_in[2]] -path_delay max >> timing.rpt
diff --git a/openlane/syntacore/sta.tcl b/openlane/syntacore/sta.tcl
new file mode 100644
index 0000000..d23ac5a
--- /dev/null
+++ b/openlane/syntacore/sta.tcl
@@ -0,0 +1,56 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(CURRENT_NETLIST) /project/openlane/syntacore/runs/syntacore/results/lvs/scr1_top_wb.lvs.powered.v
+set ::env(DESIGN_NAME) "scr1_top_wb"
+set ::env(CURRENT_SPEF) /project/openlane/syntacore/runs/syntacore/results/routing/scr1_top_wb.spef
+set ::env(BASE_SDC_FILE) "/project/openlane/syntacore/base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+read_liberty -min $::env(LIB_FASTEST)
+read_liberty -max $::env(LIB_SLOWEST)
+read_verilog $::env(CURRENT_NETLIST)
+link_design  $::env(DESIGN_NAME)
+
+read_spef  $::env(CURRENT_SPEF)
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup  -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+report_power 
+report_checks -unique -slack_max -0.0 -group_count 100 
+report_checks -unique -slack_min -0.0 -group_count 100 
+report_checks -path_delay min_max 
+report_checks -group_count 100  -slack_max -0.01  > timing.rpt
+
+report_checks -group_count 100  -slack_min -0.01 >> timing.rpt
+
+
diff --git a/openlane/uart/sta.tcl b/openlane/uart/sta.tcl
new file mode 100644
index 0000000..e9d4a77
--- /dev/null
+++ b/openlane/uart/sta.tcl
@@ -0,0 +1,56 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(CURRENT_NETLIST) /project/openlane/uart/runs/uart/results/lvs/uart_core.lvs.powered.v
+set ::env(DESIGN_NAME) "uart_core"
+set ::env(CURRENT_SPEF) /project/openlane/uart/runs/uart/results/routing/uart_core.spef
+set ::env(BASE_SDC_FILE) "/project/openlane/uart/base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+read_liberty -min $::env(LIB_FASTEST)
+read_liberty -max $::env(LIB_SLOWEST)
+read_verilog $::env(CURRENT_NETLIST)
+link_design  $::env(DESIGN_NAME)
+
+read_spef  $::env(CURRENT_SPEF)
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+#check_setup  -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type bc_wc
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+report_power 
+report_checks -unique -slack_max -0.0 -group_count 100 
+report_checks -unique -slack_min -0.0 -group_count 100 
+report_checks -path_delay min_max 
+report_checks -group_count 100  -slack_max -0.01 
+
+
+
+
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
index c34974f..dae8ae2 100644
--- a/signoff/spi_master/final_summary_report.csv
+++ b/signoff/spi_master/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h8m14s,0h4m36s,45758.33333333334,0.24,22879.16666666667,33,610.27,5491,0,0,0,0,0,0,0,0,4,-1,0,245032,41843,-0.01,-0.01,0.0,0.0,0.0,-0.01,-0.01,0.0,0.0,0.0,192057060,0.0,17.63,27.97,0.04,-1,-1,5427,5569,901,1043,0,0,0,5491,223,0,184,93,748,126,37,1613,982,921,24,424,2889,0,3313,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h6m47s,0h3m51s,45758.33333333334,0.24,22879.16666666667,33,615.0,5491,0,0,0,0,0,0,0,4,4,-1,0,244856,41928,-0.01,-0.01,0.0,0.0,0.0,-0.01,-0.01,0.0,0.0,0.0,192084576,0.0,17.57,28.06,0.0,-1,-1,5427,5567,901,1041,0,0,0,5491,223,0,184,93,748,126,37,1613,982,921,24,424,2889,0,3313,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 4ddaa70..be68387 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h41m45s,0h5m8s,3.3079078455790785,10.2784,1.6539539227895392,0,569.2,17,0,0,0,0,0,0,0,0,30,-1,-1,1188996,4053,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.29,4.08,0.96,2.29,-1,852,1470,852,1470,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h40m0s,0h5m24s,3.3079078455790785,10.2784,1.6539539227895392,0,569.79,17,0,0,0,0,0,0,0,0,30,-1,-1,1186056,4163,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.29,4.06,0.96,2.29,-1,852,1470,852,1470,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/verilog/rtl/spi_master/src/spim_ctrl.sv b/verilog/rtl/spi_master/src/spim_ctrl.sv
index 9e81d98..e53a531 100644
--- a/verilog/rtl/spi_master/src/spim_ctrl.sv
+++ b/verilog/rtl/spi_master/src/spim_ctrl.sv
@@ -242,7 +242,7 @@
 	            FSM_READ_WAIT,FSM_READ_PHASE,FSM_TX_DONE,FSM_CS_DEASEERT} state,next_state;
 
  
-  assign ctrl_state =  state;
+  assign ctrl_state =  state[3:0];
   assign en_quad_in = (s_spi_mode == SPI_STD) ? 1'b0 : 1'b1;
 
   assign spi_mode = s_spi_mode;
diff --git a/verilog/rtl/spi_master/src/spim_top.sv b/verilog/rtl/spi_master/src/spim_top.sv
index 1d153b5..35bcd62 100644
--- a/verilog/rtl/spi_master/src/spim_top.sv
+++ b/verilog/rtl/spi_master/src/spim_top.sv
@@ -103,7 +103,7 @@
     output logic                 [31:0]  spi_debug,
 
     // PAD I/f
-    input  logic [5:0]                   io_in    ,
+    input  logic [5:2]                   io_in    ,
     output logic  [5:0]                  io_out   ,
     output logic  [5:0]                  io_oeb
 
@@ -188,7 +188,7 @@
     assign spi_debug  =   {m0_res_fifo_flush,m1_res_fifo_flush,spi_init_done,
 		          m0_cmd_fifo_full,m0_cmd_fifo_empty,m0_res_fifo_full,m0_res_fifo_empty,
 		          m1_cmd_fifo_full,m1_cmd_fifo_empty,m1_res_fifo_full,m1_res_fifo_empty,
-		          ctrl_state[3:0], m0_state[3:0],m1_state[3:0],spi_ctrl_status};
+		          ctrl_state[3:0], m0_state[3:0],m1_state[3:0],spi_ctrl_status[8:0]};
 
 //-------------------------------------------------------
 // SPI Interface moved inside to support carvel IO pad 
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 65f936c..610b812 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -88,6 +88,9 @@
 ////          sdram_clock goint to io_out[29] directly from       ////
 ////          global register block, this help in better SDRAM    ////
 ////          interface timing control                            ////
+////    0.9 - 7th July 2021, Dinesh A                             ////
+////          Removed 2 Unused port connection io_in[31:30] to    ////
+////          spi_master to avoid lvs issue                       ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -465,7 +468,7 @@
     .spi_debug              (spi_debug                 ),
 
     // Pad Interface
-    .io_in                  (io_in[35:30]              ),
+    .io_in                  (io_in[35:32]              ), // io_in[31:30] unused ports
     .io_out                 ({io_out[35:31],io_in_30_} ),
     .io_oeb                 (io_oeb[35:30]             )