diff --git a/gds/pinmux_top.gds.gz b/gds/pinmux_top.gds.gz
index c004dfd..a8cf7e6 100644
--- a/gds/pinmux_top.gds.gz
+++ b/gds/pinmux_top.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 8ddef2d..6c2d71f 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/gds/wb_host.gds.gz b/gds/wb_host.gds.gz
index 4d08159..11093ea 100644
--- a/gds/wb_host.gds.gz
+++ b/gds/wb_host.gds.gz
Binary files differ
diff --git a/lef/pinmux_top.lef.gz b/lef/pinmux_top.lef.gz
index 1d19338..0e7986a 100644
--- a/lef/pinmux_top.lef.gz
+++ b/lef/pinmux_top.lef.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index aa0d2c5..d75d274 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/lef/wb_host.lef.gz b/lef/wb_host.lef.gz
index bf095a2..fd2c96b 100644
--- a/lef/wb_host.lef.gz
+++ b/lef/wb_host.lef.gz
Binary files differ
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index 8c844d5..aec92b4 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl
@@ -88,7 +88,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 500 800"
+set ::env(DIE_AREA) "0 0 500 750"
 
 
 # If you're going to use multiple power domains, then keep this disabled.
@@ -98,8 +98,8 @@
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.35"
-set ::env(CELL_PAD) "8"
+set ::env(PL_TARGET_DENSITY) "0.38"
+set ::env(CELL_PAD) "4"
 #set ::env(GRT_ADJUSTMENT) {0.2}
 
 
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg
index cd68806..25515be 100644
--- a/openlane/pinmux_top/pin_order.cfg
+++ b/openlane/pinmux_top/pin_order.cfg
@@ -72,6 +72,8 @@
 s_reset_n
 rtc_clk
 usb_clk
+strap_uartm\[1\]
+strap_uartm\[0\]
 strap_sticky\[31\]
 strap_sticky\[30\]
 strap_sticky\[29\]
@@ -301,7 +303,7 @@
 
 
 #N
-digital_io_oen\[37\]  000 0 2
+digital_io_oen\[37\]  000 0 4
 digital_io_out\[37\]
 digital_io_in\[37\]
 digital_io_oen\[36\]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index da00168..d1a637e 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -136,6 +136,7 @@
 set ::env(VDD_PIN) {vccd1}
 set ::env(GND_PIN) {vssd1}
 
+set ::env(DRT_OPT_ITERS) {32}
 
 set ::env(GRT_OBS) "                              \
 	                li1   150 130  833.1  546.54,\
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 368aff0..e702974 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,7 +1,7 @@
 u_qspi_master                2250             650           N
 u_uart_i2c_usb_spi           2250            1350           N
 u_pinmux                     2250            2250           N
-u_pll                        2300            3148           N
+u_pll                        2500            3148           N
 
 u_riscv_top.i_core_top_0    50	            1400 	       N
 u_riscv_top.u_connect       735	            1400	       N
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index ad81b5f..08d18dd 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -96,8 +96,8 @@
 
 
 
-#set ::env(FP_IO_VEXTEND) 4
-#set ::env(FP_IO_HEXTEND) 4
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
 
 set ::env(FP_PDN_VPITCH) 100
 set ::env(FP_PDN_HPITCH) 100
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 25aea17..26c9f8e 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -315,6 +315,8 @@
 p_reset_n
 s_reset_n
 xtal_clk
+strap_uartm\[1\]
+strap_uartm\[0\]
 strap_sticky\[31\]
 strap_sticky\[30\]
 strap_sticky\[29\]
diff --git a/spef/pinmux_top.spef.gz b/spef/pinmux_top.spef.gz
index a5affea..533f3c9 100644
--- a/spef/pinmux_top.spef.gz
+++ b/spef/pinmux_top.spef.gz
Binary files differ
diff --git a/spef/user_project_wrapper.spef.gz b/spef/user_project_wrapper.spef.gz
index 935bc18..876c971 100644
--- a/spef/user_project_wrapper.spef.gz
+++ b/spef/user_project_wrapper.spef.gz
Binary files differ
diff --git a/spef/wb_host.spef.gz b/spef/wb_host.spef.gz
index 9434fbf..14df172 100644
--- a/spef/wb_host.spef.gz
+++ b/spef/wb_host.spef.gz
Binary files differ
diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz
index e44f891..ff9c375 100644
--- a/spi/lvs/user_project_wrapper.spice.gz
+++ b/spi/lvs/user_project_wrapper.spice.gz
Binary files differ
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl
index e4a1421..9c9b9cd 100644
--- a/sta/scripts/caravel_timing.tcl
+++ b/sta/scripts/caravel_timing.tcl
@@ -207,9 +207,9 @@
     set tsram_iport [get_pins {mprj/u_tsram0_2kb/din0[*]}]
 	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/addr0[*]}]]
 	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/addr1[*]}]]
-	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/csb0[*]}]]
-	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/csb1[*]}]]
-	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/web0[*]}]]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/csb0}]]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/csb1}]]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/web0}]]
 	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/wmask0[*]}]]
 
     set tsram_oport [get_pins {mprj/u_tsram0_2kb/dout0[*]}]
@@ -228,12 +228,12 @@
         }
 
     #ICACHE SRAM 
-    set isram_iport [                     get_pins {mprj/u_icahce_2kb/din0[*]}]
+    set isram_iport [                     get_pins {mprj/u_icache_2kb/din0[*]}]
 	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/addr0[*]}]]
 	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/addr1[*]}]]
-	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/csb0[*]}]]
-	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/csb1[*]}]]
-	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/web0[*]}]]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/csb0}]]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/csb1}]]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/web0}]]
 	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/wmask0[*]}]]
 
     set isram_oport [                     get_pins {mprj/u_icache_2kb/dout0[*]}]
@@ -252,12 +252,12 @@
         }
 
     #DCACHE SRAM 
-    set dsram_iport [                     get_pins {mprj/u_dcahce_2kb/din0[*]}]
+    set dsram_iport [                     get_pins {mprj/u_dcache_2kb/din0[*]}]
 	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/addr0[*]}]]
 	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/addr1[*]}]]
-	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/csb0[*]}]]
-	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/csb1[*]}]]
-	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/web0[*]}]]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/csb0}]]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/csb1}]]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/web0}]]
 	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/wmask0[*]}]]
 
     set dsram_oport [                     get_pins {mprj/u_dcache_2kb/dout0[*]}]
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc
index b4df712..ab8d910 100644
--- a/sta/sdc/caravel.sdc
+++ b/sta/sdc/caravel.sdc
@@ -18,17 +18,17 @@
 
 
 create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks master_clock] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i]
-create_clock -name int_pll_clock -period 5.0000  [get_pins {mprj/u_wb_host/u_clkbuf_pll.u_buf/X}]
+create_clock -name int_pll_clock -period 5.0000  [get_pins {mprj/u_pinmux/int_pll_clock}]
 
-create_clock -name wbs_ref_clk -period 5.0000   [get_pins {mprj/u_wb_host/u_wbs_ref_clkbuf.u_buf/X}]
+create_clock -name wbs_ref_clk -period 5.0000   [get_pins {mprj/u_wb_host/u_reg.u_wbs_ref_clkbuf.u_buf/X}]
 create_clock -name wbs_clk_i   -period 10.0000  [get_pins {mprj/u_wb_host/wbs_clk_out}]
 
-create_clock -name cpu_ref_clk -period 5.0000   [get_pins {mprj/u_wb_host/u_cpu_ref_clkbuf.u_buf/X}]
+create_clock -name cpu_ref_clk -period 5.0000   [get_pins {mprj/u_wb_host/u_reg.u_cpu_ref_clkbuf.u_buf/X}]
 create_clock -name cpu_clk     -period 10.0000  [get_pins {mprj/u_wb_host/cpu_clk}]
 
 create_clock -name rtc_clk     -period 50.0000  [get_pins {mprj/u_pinmux/rtc_clk}]
 
-create_clock -name pll_ref_clk -period 20.0000  [get_pins {mprj/u_wb_host/pll_ref_clk}]
+create_clock -name pll_ref_clk -period 20.0000  [get_pins {mprj/u_pinmux/pll_ref_clk}]
 create_clock -name pll_clk_0   -period 5.0000   [get_pins {mprj/u_pll/ringosc.ibufp01/Y}]
 
 create_clock -name usb_ref_clk -period 5.0000   [get_pins {mprj/u_pinmux/u_glbl_reg.u_usb_ref_clkbuf.u_buf/X}]
@@ -84,7 +84,7 @@
 set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[1]}]
 
 #disable clock gating check at static clock select pins
-set_false_path -through [get_pins mprj/u_wb_host/u_wbs_clk_sel.genblk1.u_mux/S]
+#set_false_path -through [get_pins mprj/u_wb_host/u_wbs_clk_sel.genblk1.u_mux/S]
 
 set_propagated_clock [all_clocks]
 
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index e5717ba..37b0dcc 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,11 +19,13 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec user_cache_bypass user_gpio user_spi_isp arduino_risc_boot arduino_hello_world arduino_ascii_table arduino_multi_serial arduino_arrays arduino_switchCase2 arduino_character_analysis arduino_string arduino_digital_port_control user_sspi user_aes user_sema arduino_timer_intr
+PATTERNS = user_basic user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_aes user_spi_isp user_timer user_uart_master user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 riscv_regress
 
 all:  ${PATTERNS}
+	echo "################# Test case Summary #####################" > regression.rpt
+	xterm -e /usr/bin/watch -n 25 /bin/cat regression.rpt & 
 	for i in ${PATTERNS}; do \
-		( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+		( cd $$i && make | tee run.log && grep Monitor run.log | grep $$i >> ../regression.rpt) ; \
 	done
 
 DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
diff --git a/verilog/dv/arduino_arrays/arduino_arrays_tb.v b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
index d804ea5..f7f4808 100644
--- a/verilog/dv/arduino_arrays/arduino_arrays_tb.v
+++ b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
@@ -238,15 +238,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Ardunio arrays  (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: Ardunio arrays (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Ardunio arrays (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: Ardunio arrays (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
index ee76859..5152893 100644
--- a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
+++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
@@ -235,15 +235,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone Hello World (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone Hello World (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone Hello World (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone Hello World (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
index 0aaefb7..275b18b 100644
--- a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
+++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
@@ -283,15 +283,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	   $display("Monitor: character_analysis (GL) Passed");
+	    	   $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: character_analysis (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	   $display("Monitor: character_analysis (GL) Failed");
+	    	   $display("Monitor: %m  (GL) Failed");
 		    `else
-		       $display("Monitor: character_analysis (RTL) Failed");
+		       $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
index e12c308..eaf97d5 100644
--- a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
+++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
@@ -209,15 +209,15 @@
 	  $display("###################################################");
       if(test_fail == 0) begin
 	    `ifdef GL
-	           $display("Monitor: Ardunio Digital Port Control  (GL) Passed");
+	           $display("Monitor: %m (GL) Passed");
 	    `else
-	       $display("Monitor: Ardunio Digital Port Control (RTL) Passed");
+	       $display("Monitor: %m (RTL) Passed");
 	    `endif
 	  end else begin
 	  `ifdef GL
-	      $display("Monitor: Ardunio Digital Port Control (GL) Failed");
+	      $display("Monitor: %m (GL) Failed");
 	  `else
-	      $display("Monitor: Ardunio Digital Port Control (RTL) Failed");
+	      $display("Monitor: %m (RTL) Failed");
 	  `endif
 	  end
 	    $display("###################################################");
diff --git a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
index 92495ad..23e360e 100644
--- a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
+++ b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
@@ -358,15 +358,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone String (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone String (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone String (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone String (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
index beb220f..44b41db 100644
--- a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
+++ b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
@@ -237,15 +237,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone Hello World (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone Hello World (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone Hello World (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone Hello World (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
index f8f2cfb..ace2a5b 100644
--- a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
@@ -245,15 +245,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone i2c scanner (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone i2c scanner (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone i2c scanner (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone i2c scanner (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
index b507fb0..3c94c7d 100644
--- a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
+++ b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
@@ -242,15 +242,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone i2c scanner (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone i2c scanner (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone i2c scanner (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone i2c scanner (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
index 5c7f4d0..fc55f4c 100644
--- a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
+++ b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
@@ -203,7 +203,7 @@
                 tb_uart1.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
                                                uart_stick_parity, uart_timeout, uart_divisor);
 
-                repeat (1000) @(posedge clock);  // wait for Processor Get Ready
+                repeat (10000) @(posedge clock);  // wait for Processor Get Ready
 	            flag  = 0;
 		        check_sum = 0;
                 
@@ -263,15 +263,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone Multi Serial (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone Multi Serial (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone Multi Serial (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone Multi Serial (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
index d0e77dd..34247b0 100644
--- a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
+++ b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
@@ -141,15 +141,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone User Risc Boot (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone User Risc Boot (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/arduino_string/arduino_string_tb.v b/verilog/dv/arduino_string/arduino_string_tb.v
index 539b87d..a02727a 100644
--- a/verilog/dv/arduino_string/arduino_string_tb.v
+++ b/verilog/dv/arduino_string/arduino_string_tb.v
@@ -238,15 +238,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone String (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone String (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone String (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone String (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
index 081eca4..3432fca 100644
--- a/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
+++ b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
@@ -298,15 +298,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: arduino_switchCase2 (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: arduino_switchCase2 (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: arduino_switchCase2 (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: arduino_switchCase2 (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
index 90dee0b..043a19a 100644
--- a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
+++ b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
@@ -247,15 +247,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone String (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone String (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone String (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone String (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v b/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v
index 5c9a9c9..43929a1 100644
--- a/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v
+++ b/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v
@@ -239,15 +239,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone String (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone String (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone String (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone String (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/common/agents/user_tasks.sv b/verilog/dv/common/agents/user_tasks.sv
index 969fb3a..2a1edbe 100644
--- a/verilog/dv/common/agents/user_tasks.sv
+++ b/verilog/dv/common/agents/user_tasks.sv
@@ -4,7 +4,7 @@
 wire  [15:0]    strap_in;
 assign strap_in[`PSTRAP_CLK_SRC] = 2'b00;            // System Clock Source wbs/riscv: User clock1
 assign strap_in[`PSTRAP_CLK_DIV] = 2'b00;            // Clock Division for wbs/riscv : 0 Div
-assign strap_in[`PSTRAP_UARTM_CFG] = 1'b0;           // uart master config control -  constant value based on system clock selection
+assign strap_in[`PSTRAP_UARTM_CFG] = 2'b0;           // uart master config control -  constant value based on system clock selection
 assign strap_in[`PSTRAP_QSPI_SRAM] = 1'b1;           // QSPI SRAM Mode Selection - Quad 
 assign strap_in[`PSTRAP_QSPI_FLASH] = 2'b10;         // QSPI Fash Mode Selection - Quad
 assign strap_in[`PSTRAP_RISCV_RESET_MODE] = 1'b1;    // Riscv Reset control - Removed Riscv on Power On Reset
@@ -30,9 +30,9 @@
 //---------------------------------------------------------
 
 `ifdef RISC_BOOT // RISCV Based Test case
-parameter bit  [15:0] PAD_STRAP = 16'b0000_0001_1011_0000;
+parameter bit  [15:0] PAD_STRAP = 16'b0000_0001_1010_0000;
 `else
-parameter bit  [15:0] PAD_STRAP = 16'b0000_0000_1011_0000;
+parameter bit  [15:0] PAD_STRAP = 16'b0000_0000_1010_0000;
 `endif
 
 //-------------------------------------------------------------
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 31842cb..51bde45 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -151,9 +151,9 @@
 		$display("%c[1;31m",27);
 		$display ("##########################################################");
 		`ifdef GL
-			$display ("Monitor: Timeout, Test Risc Boot (GL) Failed");
+			$display ("Monitor: Timeout, %m (GL) Failed");
 		`else
-			$display ("Monitor: Timeout, Test Risc Boot (RTL) Failed");
+			$display ("Monitor: Timeout, %m (RTL) Failed");
 		`endif
 		$display ("##########################################################");
 		$display("%c[0m",27);
@@ -228,15 +228,15 @@
               $display("###################################################");
               if(test_fail == 0) begin
                  `ifdef GL
-                     $display("Monitor: Standalone User Risc Boot Test (GL) Passed");
+                     $display("Monitor: %m (GL) Passed");
                  `else
-                     $display("Monitor: Standalone User Risc Boot Test (RTL) Passed");
+                     $display("Monitor: %m (RTL) Passed");
                  `endif
               end else begin
                   `ifdef GL
-                      $display("Monitor: Standalone User Risc Boot Test (GL) Failed");
+                      $display("Monitor: %m (GL) Failed");
                   `else
-                      $display("Monitor: Standalone User Risc Boot Test (RTL) Failed");
+                      $display("Monitor: %m (RTL) Failed");
                   `endif
                end
               $display("###################################################");
diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master/uart_master_tb.v
index a8b6f9e..2a99ff7 100644
--- a/verilog/dv/uart_master/uart_master_tb.v
+++ b/verilog/dv/uart_master/uart_master_tb.v
@@ -91,9 +91,9 @@
 		$display("%c[1;31m",27);
 		$display ("##########################################################");
 		`ifdef GL
-		   $display ("Monitor: Timeout, Test UART Master (GL) Failed");
+		   $display ("Monitor: Timeout, %m (GL) Failed");
 		`else
-		   $display ("Monitor: Timeout, Test UART Master (RTL) Failed");
+		   $display ("Monitor: Timeout, %m (RTL) Failed");
 		`endif
 		$display ("##########################################################");
 		$display("%c[0m",27);
@@ -162,15 +162,15 @@
            $display("###################################################");
            if(test_fail == 0) begin
               `ifdef GL
-                  $display("Monitor: Standalone User UART Master (GL) Passed");
+                  $display("Monitor: %m (GL) Passed");
               `else
-                  $display("Monitor: Standalone User Uart Master (RTL) Passed");
+                  $display("Monitor: %m (RTL) Passed");
               `endif
            end else begin
                `ifdef GL
-                   $display("Monitor: Standalone User Uart Master (GL) Failed");
+                   $display("Monitor: %m (GL) Failed");
                `else
-                   $display("Monitor: Standalone User Uart Master (RTL) Failed");
+                   $display("Monitor: %m (RTL) Failed");
                `endif
             end
            $display("###################################################");
diff --git a/verilog/dv/user_aes/user_aes_tb.v b/verilog/dv/user_aes/user_aes_tb.v
index 548f113..3d47bd3 100644
--- a/verilog/dv/user_aes/user_aes_tb.v
+++ b/verilog/dv/user_aes/user_aes_tb.v
@@ -210,15 +210,15 @@
                $display("###################################################");
                if(test_fail == 0) begin
                   `ifdef GL
-                      $display("Monitor: Standalone User AES Test (GL) Passed");
+                      $display("Monitor: %m (GL) Passed");
                   `else
-                      $display("Monitor: Standalone User AES Test (RTL) Passed");
+                      $display("Monitor: %m (RTL) Passed");
                   `endif
                end else begin
                    `ifdef GL
-                       $display("Monitor: Standalone User AES Test (GL) Failed");
+                       $display("Monitor: %m (GL) Failed");
                    `else
-                       $display("Monitor: Standalone User AES Test (RTL) Failed");
+                       $display("Monitor: %m (RTL) Failed");
                    `endif
                 end
                $display("###################################################");
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile
index c1ad8ae..1067943 100644
--- a/verilog/dv/user_basic/Makefile
+++ b/verilog/dv/user_basic/Makefile
@@ -73,7 +73,7 @@
 endif
 
 %.vcd: %.vvp
-	vvp $<
+	vvp $< 
 
 
 # ---- Clean ----
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 6cb1360..2a1858d 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -422,15 +422,15 @@
       $display("###################################################");
       if(test_fail == 0) begin
          `ifdef GL
-             $display("Monitor: Standalone User UART Test (GL) Passed");
+             $display("Monitor: %m (GL) Passed");
          `else
-             $display("Monitor: Standalone User UART Test (RTL) Passed");
+             $display("Monitor: %m (RTL) Passed");
          `endif
       end else begin
           `ifdef GL
-              $display("Monitor: Standalone User UART Test (GL) Failed");
+              $display("Monitor: %m (GL) Failed");
           `else
-              $display("Monitor: Standalone User UART Test (RTL) Failed");
+              $display("Monitor: %m (RTL) Failed");
           `endif
        end
       $display("###################################################");
diff --git a/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
index 838cb98..b8909fa 100644
--- a/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
+++ b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
@@ -130,15 +130,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone User Risc Boot (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone User Risc Boot (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/user_gpio/user_gpio_tb.v b/verilog/dv/user_gpio/user_gpio_tb.v
index 406fb8b..0efe8fe 100644
--- a/verilog/dv/user_gpio/user_gpio_tb.v
+++ b/verilog/dv/user_gpio/user_gpio_tb.v
@@ -332,15 +332,15 @@
 
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: GPIO Mode (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: GPIO Mode (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: GPIO Mode (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: GPIO Mode (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index 0328fea..0547990 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -245,15 +245,15 @@
      $display("###################################################");
      if(test_fail == 0) begin
         `ifdef GL
-            $display("Monitor: Standalone User I2M Test (GL) Passed");
+            $display("Monitor: %m (GL) Passed");
         `else
-            $display("Monitor: Standalone User I2M Test (RTL) Passed");
+            $display("Monitor: %m (RTL) Passed");
         `endif
      end else begin
          `ifdef GL
-             $display("Monitor: Standalone User I2M Test (GL) Failed");
+             $display("Monitor: %m (GL) Failed");
          `else
-             $display("Monitor: Standalone User I2M Test (RTL) Failed");
+             $display("Monitor: %m (RTL) Failed");
          `endif
       end
      $display("###################################################");
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v
index 5ec74d4..8d7a20a 100644
--- a/verilog/dv/user_pwm/user_pwm_tb.v
+++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -143,15 +143,15 @@
 
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: PWM Mode (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: PWM Mode (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: PWM Mode (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: PWM Mode (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v
index 35f1cd2..9801bdd 100644
--- a/verilog/dv/user_qspi/user_qspi_tb.v
+++ b/verilog/dv/user_qspi/user_qspi_tb.v
@@ -1111,15 +1111,15 @@
 
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: SPI Master Mode (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: SPI Master Mode (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: SPI Master Mode (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: SPI Master Mode (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 527ac4e..0901b82 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -144,15 +144,15 @@
 	    	$display("###################################################");
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Standalone User Risc Boot (GL) Passed");
+	    	   $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Standalone User Risc Boot (GL) Failed");
+	    	    $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/user_sema/user_sema_tb.v b/verilog/dv/user_sema/user_sema_tb.v
index 1f6c3b6..fa2b8a8 100644
--- a/verilog/dv/user_sema/user_sema_tb.v
+++ b/verilog/dv/user_sema/user_sema_tb.v
@@ -172,15 +172,15 @@
       $display("###################################################");
       if(test_fail == 0) begin
          `ifdef GL
-             $display("Monitor: Semaphore Test (GL) Passed");
+             $display("Monitor: %m (GL) Passed");
          `else
-             $display("Monitor: Semaphore Test (RTL) Passed");
+             $display("Monitor: %m (RTL) Passed");
          `endif
       end else begin
           `ifdef GL
-              $display("Monitor: Semaphore Test (GL) Failed");
+              $display("Monitor: %m (GL) Failed");
           `else
-              $display("Monitor: Semaphore Test (RTL) Failed");
+              $display("Monitor: %m (RTL) Failed");
           `endif
        end
       $display("###################################################");
diff --git a/verilog/dv/user_spi_isp/user_spi_isp_tb.v b/verilog/dv/user_spi_isp/user_spi_isp_tb.v
index 0b31aa1..bc6a80c 100644
--- a/verilog/dv/user_spi_isp/user_spi_isp_tb.v
+++ b/verilog/dv/user_spi_isp/user_spi_isp_tb.v
@@ -134,15 +134,15 @@
    $display("###################################################");
    if(u_spim.err_cnt == 0) begin
       `ifdef GL
-          $display("Monitor: Standalone User SPI ISP (GL) Passed");
+          $display("Monitor: %m (GL) Passed");
       `else
-          $display("Monitor: Standalone User SPI ISP (RTL) Passed");
+          $display("Monitor: %m (RTL) Passed");
       `endif
    end else begin
        `ifdef GL
-           $display("Monitor: Standalone User SPI ISP (GL) Failed");
+           $display("Monitor: %m (GL) Failed");
        `else
-           $display("Monitor: Standalone User SPI ISP (RTL) Failed");
+           $display("Monitor: %m (RTL) Failed");
        `endif
     end
    $display("###################################################");
diff --git a/verilog/dv/user_sram_exec/user_sram_exec_tb.v b/verilog/dv/user_sram_exec/user_sram_exec_tb.v
index fb7095d..277dae2 100644
--- a/verilog/dv/user_sram_exec/user_sram_exec_tb.v
+++ b/verilog/dv/user_sram_exec/user_sram_exec_tb.v
@@ -142,15 +142,15 @@
 	    $display("###################################################");
         if(test_fail == 0) begin
 		`ifdef GL
-	    	$display("Monitor: Standalone User Risc Boot (GL) Passed");
+	    	$display("Monitor: %m (GL) Passed");
 		`else
-		    $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+		    $display("Monitor: %m (RTL) Passed");
 		`endif
 	    end else begin
 		`ifdef GL
-	       $display("Monitor: Standalone User Risc Boot (GL) Failed");
+	       $display("Monitor: %m (GL) Failed");
 		`else
-		   $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+		   $display("Monitor: %m (RTL) Failed");
 		`endif
 		 end
 	   	 $display("###################################################");
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v
index 2ecf28e..1650d50 100644
--- a/verilog/dv/user_sspi/user_sspi_tb.v
+++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -352,15 +352,15 @@
 
         if(test_fail == 0) begin
 		`ifdef GL
-	    	$display("Monitor: SPI Master Mode (GL) Passed");
+	    	$display("Monitor: %m (GL) Passed");
 		`else
-		    $display("Monitor: SPI Master Mode (RTL) Passed");
+		    $display("Monitor: %m (RTL) Passed");
 		`endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: SPI Master Mode (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: SPI Master Mode (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v
index 0fd19b9..62aa667 100644
--- a/verilog/dv/user_timer/user_timer_tb.v
+++ b/verilog/dv/user_timer/user_timer_tb.v
@@ -195,15 +195,15 @@
 
           	if(test_fail == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: Timer Mode (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: Timer Mode (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: Timer Mode (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: Timer Mode (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index db86ad0..8029645 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -217,15 +217,15 @@
       $display("###################################################");
       if(test_fail == 0) begin
          `ifdef GL
-             $display("Monitor: Standalone User UART Test (GL) Passed");
+             $display("Monitor: %m (GL) Passed");
          `else
-             $display("Monitor: Standalone User UART Test (RTL) Passed");
+             $display("Monitor: %m (RTL) Passed");
          `endif
       end else begin
           `ifdef GL
-              $display("Monitor: Standalone User UART Test (GL) Failed");
+              $display("Monitor: %m (GL) Failed");
           `else
-              $display("Monitor: Standalone User UART Test (RTL) Failed");
+              $display("Monitor: %m (RTL) Failed");
           `endif
        end
       $display("###################################################");
diff --git a/verilog/dv/user_uart1/user_uart1_tb.v b/verilog/dv/user_uart1/user_uart1_tb.v
index 91405a8..2d1c2b2 100644
--- a/verilog/dv/user_uart1/user_uart1_tb.v
+++ b/verilog/dv/user_uart1/user_uart1_tb.v
@@ -213,15 +213,15 @@
       $display("###################################################");
       if(test_fail == 0) begin
          `ifdef GL
-             $display("Monitor: Standalone User UART Test (GL) Passed");
+             $display("Monitor: %m (GL) Passed");
          `else
-             $display("Monitor: Standalone User UART Test (RTL) Passed");
+             $display("Monitor: %m (RTL) Passed");
          `endif
       end else begin
           `ifdef GL
-              $display("Monitor: Standalone User UART Test (GL) Failed");
+              $display("Monitor: %m (GL) Failed");
           `else
-              $display("Monitor: Standalone User UART Test (RTL) Failed");
+              $display("Monitor: %m (RTL) Failed");
           `endif
        end
       $display("###################################################");
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v
index 682d986..33277cb 100644
--- a/verilog/dv/user_uart_master/user_uart_master_tb.v
+++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -116,7 +116,7 @@
 initial
 begin
    strap_in = 0;
-   strap_in[`PSTRAP_UARTM_CFG] = 0; // uart master config control - load from LA
+   strap_in[`PSTRAP_UARTM_CFG] = 2'b11; // uart master config control - load from LA
    apply_strap(strap_in);
 
    uart_data_bit           = 2'b11;
@@ -181,15 +181,15 @@
    $display("###################################################");
    if(test_fail == 0) begin
       `ifdef GL
-          $display("Monitor: Standalone User UART Master (GL) Passed");
+          $display("Monitor: %m (GL) Passed");
       `else
-          $display("Monitor: Standalone User Uart Master (RTL) Passed");
+          $display("Monitor: %m (RTL) Passed");
       `endif
    end else begin
        `ifdef GL
-           $display("Monitor: Standalone User Uart Master (GL) Failed");
+           $display("Monitor: %m (GL) Failed");
        `else
-           $display("Monitor: Standalone User Uart Master (RTL) Failed");
+           $display("Monitor: %m (RTL) Failed");
        `endif
     end
    $display("###################################################");
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v
index 8f4a49c..7c0dac5 100644
--- a/verilog/dv/user_usb/user_usb_tb.v
+++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -145,15 +145,15 @@
 
           	if(test_control.error_count == 0) begin
 		   `ifdef GL
-	    	       $display("Monitor: USB Mode (GL) Passed");
+	    	       $display("Monitor: %m (GL) Passed");
 		   `else
-		       $display("Monitor: USB Mode (RTL) Passed");
+		       $display("Monitor: %m (RTL) Passed");
 		   `endif
 	        end else begin
 		    `ifdef GL
-	    	        $display("Monitor: USB Mode (GL) Failed");
+	    	        $display("Monitor: %m (GL) Failed");
 		    `else
-		        $display("Monitor: USB Mode (RTL) Failed");
+		        $display("Monitor: %m (RTL) Failed");
 		    `endif
 		 end
 	    	$display("###################################################");
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index ea2d2c2..271e092 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -71,9 +71,9 @@
 		$display("%c[1;31m",27);
 		$display ("##########################################################");
 		`ifdef GL
-			$display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
+			$display ("Monitor: Timeout, %m (GL) Failed");
 		`else
-			$display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");
+			$display ("Monitor: Timeout, %m (RTL) Failed");
 		`endif
 		$display ("##########################################################");
 		$display("%c[0m",27);
@@ -87,9 +87,9 @@
 		wait(checkbits == 16'h AB6A);
 		$display ("##########################################################");
 		`ifdef GL
-	    	$display("Monitor: Mega-Project WB (GL) Passed");
+	    	$display("Monitor: %m (GL) Passed");
 		`else
-		    $display("Monitor: Mega-Project WB (RTL) Passed");
+		    $display("Monitor: %m (RTL) Passed");
 		`endif
 		$display ("##########################################################");
 	    $finish;
diff --git a/verilog/gl/pinmux_top.v.gz b/verilog/gl/pinmux_top.v.gz
index 45e74f3..2b73266 100644
--- a/verilog/gl/pinmux_top.v.gz
+++ b/verilog/gl/pinmux_top.v.gz
Binary files differ
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index 09b8a2e..d3570af 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ
diff --git a/verilog/gl/wb_host.v.gz b/verilog/gl/wb_host.v.gz
index 1e4b933..85265ec 100644
--- a/verilog/gl/wb_host.v.gz
+++ b/verilog/gl/wb_host.v.gz
Binary files differ
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv
index 33d37b4..a8e21c7 100644
--- a/verilog/rtl/pinmux/src/glbl_reg.sv
+++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -62,6 +62,7 @@
                        // to/from Global Reset FSM
 	                    input  logic [31:0]    system_strap           ,
 	                    output logic [31:0]    strap_sticky           ,
+	                    output logic [1:0]     strap_uartm            ,
                        
 
                        // Global Reset control
@@ -304,7 +305,6 @@
 
 glbl_rst_reg  #(32'h0) u_reg_1	(
 	      //List of Inputs
-          .e_reset_n  (e_reset_n     ),
 	      .s_reset_n  (s_reset_n     ),
           .rst_in     (rst_in        ),
 	      .clk        (mclk          ),
@@ -490,7 +490,8 @@
 	      
 	      //List of Outs
            .strap_latch         (strap_latch ),
-	       .strap_sticky        (strap_sticky) 
+	       .strap_sticky        (strap_sticky),
+	       .strap_uartm         (strap_uartm) 
          );
 
 
diff --git a/verilog/rtl/pinmux/src/glbl_rst_reg.sv b/verilog/rtl/pinmux/src/glbl_rst_reg.sv
index cca7d0b..c0f8019 100644
--- a/verilog/rtl/pinmux/src/glbl_rst_reg.sv
+++ b/verilog/rtl/pinmux/src/glbl_rst_reg.sv
@@ -26,7 +26,6 @@
 **********************************************************************************/
 
 module  glbl_rst_reg	(
-	      input logic        e_reset_n,
 	      input logic        s_reset_n,
 	      //List of Inputs
           input logic [31:0] rst_in,
@@ -41,22 +40,23 @@
 
   parameter   RESET_DEFAULT    = 32'h0;  
 
-logic [31:0] data_out_l;
 
-always @ (posedge clk or negedge e_reset_n) begin 
-  if (e_reset_n == 1'b0) begin
+logic flag;
+always @ (posedge clk or negedge s_reset_n) begin 
+  if (s_reset_n == 1'b0) begin
     data_out       <= RESET_DEFAULT ;
-    data_out_l     <= 'h0 ;
-  end else if (s_reset_n == 1'b0) begin
-    data_out       <= RESET_DEFAULT ;
-    data_out_l     <= rst_in ;
+    flag           <= 1'b1;
   end else begin
-    data_out  <= data_out_l;
-    if(cs && we[0]) data_out_l[7:0]   <= data_in[7:0];
-    if(cs && we[1]) data_out_l[15:8]  <= data_in[15:8];
-    if(cs && we[2]) data_out_l[23:16] <= data_in[23:16];
-    if(cs && we[3]) data_out_l[31:24] <= data_in[31:24];
-  end
+      flag         <= 1'b0;
+      if (flag == 1'b1) begin
+        data_out    <= rst_in ;
+      end else begin
+        if(cs && we[0]) data_out[7:0]   <= data_in[7:0];
+        if(cs && we[1]) data_out[15:8]  <= data_in[15:8];
+        if(cs && we[2]) data_out[23:16] <= data_in[23:16];
+        if(cs && we[3]) data_out[31:24] <= data_in[31:24];
+      end
+   end
 end
 
 
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv
index 1e7c96b..c9de5f1 100755
--- a/verilog/rtl/pinmux/src/pinmux_top.sv
+++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -94,6 +94,7 @@
                         input  logic           cfg_strap_pad_ctrl     ,
 	                    input  logic [31:0]    system_strap           ,
 	                    output logic [31:0]    strap_sticky           ,
+                        output logic [1:0]     strap_uartm            ,
 
                         input logic            user_clock1            ,
                         input logic            user_clock2            ,
@@ -352,6 +353,7 @@
           .pad_strap_in                 (pad_strap_in            ),
           .system_strap                 (system_strap            ),
           .strap_sticky                 (strap_sticky            ),
+          .strap_uartm                  (strap_uartm             ),
 
           .user_clock1                  (user_clock1             ),
           .user_clock2                  (user_clock2             ),
diff --git a/verilog/rtl/pinmux/src/strap_ctrl.sv b/verilog/rtl/pinmux/src/strap_ctrl.sv
index 643a6de..c0405b0 100644
--- a/verilog/rtl/pinmux/src/strap_ctrl.sv
+++ b/verilog/rtl/pinmux/src/strap_ctrl.sv
@@ -68,16 +68,14 @@
                  01 - 2 Div
                  10 - 4 Div
                  11 - 8 Div
-     bit [4]   - uart master config control
-                 0   - load from LA
-                 1   - constant value based on system clock selection (Default)
+     bit [4]   - Reserved
      bit [5]   - QSPI SRAM Mode Selection
-                 1'b0 - Single (Default)
-                 1'b1 - Quad
+                 1'b0 - Single 
+                 1'b1 - Quad   (Default)
      bit [7:6] - QSPI Fash Mode Selection
-                 2'b00 - Single (Default)
+                 2'b00 - Single 
                  2'b01 - Double
-                 2'b10 - Quad
+                 2'b10 - Quad   (Default)
                  2'b11 - QDDR
      bit [8]   - Riscv Reset control
                  0 - Keep Riscv on Reset
@@ -93,6 +91,11 @@
                  2'b01 - Default value + 2               
                  2'b10 - Default value + 4               
                  2'b11 - Default value - 4 
+     bit [4:13]   - uart master config control
+                 2'b00   - constant value based on system clock-50Mhz (Default)
+                 2'b01   - constant value based on system clock-40Mhz 
+                 2'b10   - constant value based on system clock-60Mhz (USB Ref Clock)
+                 2'b11   - load from LA
      bit [14:13] - Reserved
      bit [15]    - Strap Mode
                    0 - Normal
@@ -165,7 +168,8 @@
 	         
 	         //List of Outs
              output logic [15:0] strap_latch         ,
-	         output logic [31:0] strap_sticky 
+	         output logic [31:0] strap_sticky        ,
+             output logic [1:0]  strap_uartm           // Uart Master Strap Config
 
          );
 
@@ -195,13 +199,16 @@
                    pstrap_select[8]     , // bit[12]      - Riscv Reset control
                    pstrap_select[7:6]   , // bit[11:10]   - QSPI FLASH Mode Selection CS#0
                    pstrap_select[5]     , // bit[9]       - QSPI SRAM Mode Selection CS#2
-                   pstrap_select[4]     , // bit[8]       - uart master config control
+                   pstrap_select[4]     , // bit[8]       - Reserved
                    pstrap_select[3:2]   , // bit[7:6]     - riscv clock div
                    pstrap_select[1:0]   , // bit[5:4]     - riscv clock source sel
                    pstrap_select[3:2]   , // bit[3:2]     - wbs clock division
                    pstrap_select[1:0]     // bit[1:0]     - wbs clock source sel
                    };
 
+
+assign strap_uartm = strap_latch[`PSTRAP_UARTM_CFG];
+
 //------------------------------------
 // Generating strap latch
 //------------------------------------
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index e7c639e..a8b8341 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh
@@ -10,7 +10,7 @@
 
 parameter SKEW_RESET_VAL = 32'b0000_0000_1000_0111_1001_1000_1001_1000;
 
-parameter PSTRAP_DEFAULT_VALUE = 15'b000_0111_1011_0000;
+parameter PSTRAP_DEFAULT_VALUE = 15'b000_0111_1010_0000;
 
 /*****************************************************
 pad_strap_in decoding
@@ -24,10 +24,7 @@
                  01 - 2 Div       
                  10 - 4 Div
                  11 - 8 Div
-     bit [4]   - uart master config control
-                 0   - load from LA
-                 1   - constant value based 
-                       on system clock selection  (Default)
+     bit [4]   - Reserved
      bit [5]   - QSPI SRAM Mode Selection
                  1'b0 - Single    
                  1'b1 - Quad      (Default)
@@ -50,6 +47,11 @@
                  2'b01 - Default value + 2               
                  2'b10 - Default value + 4               
                  2'b11 - Default value - 4 
+     bit [4:13]   - uart master config control
+                 2'b00   - constant value based on system clock-50Mhz (Default)
+                 2'b01   - constant value based on system clock-40Mhz 
+                 2'b10   - constant value based on system clock-60Mhz (USB Ref Clock)
+                 2'b11   - load from LA
 
      bit[15]   - Strap Mode
                 0 - [14:0] loaded from pad
@@ -66,6 +68,7 @@
 `define PSTRAP_RISCV_CACHE_BYPASS  9
 `define PSTRAP_RISCV_SRAM_CLK_EDGE 10
 `define PSTRAP_CLK_SKEW            12:11
+`define PSTRAP_UARTM_CFG           14:13
 
 `define PSTRAP_DEFAULT_VALUE       15
 
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index b3e2be1..f832c7e 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -269,6 +269,10 @@
 ////          pinmux to help risc core to do pll config and reboot////
 ////          B. PLL configuration are kept in p_reset_n to avoid ////
 ////           initialized on soft reboot.                        ////
+////          C. Master Uart has two strap bit to control the     ////
+////          boot up config                                      ////
+////          2'b00 - 50Mhz, 2'b01 - 40Mhz, 2'b10 - 50Mhz,        ////
+////          2'b11 - LA control                                  ////
 ////                                                              ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
@@ -752,6 +756,7 @@
 //---------------------------------------------------------------------
 wire [31:0]                    system_strap                           ;
 wire [31:0]                    strap_sticky                           ;
+wire [1:0]                     strap_uartm                            ;
 wire [1:0]  strap_qspi_flash       = system_strap[`STRAP_QSPI_FLASH];
 wire        strap_qspi_sram        = system_strap[`STRAP_QSPI_SRAM];
 wire        strap_qspi_pre_sram    = system_strap[`STRAP_QSPI_PRE_SRAM];
@@ -805,6 +810,7 @@
           .cfg_strap_pad_ctrl      (cfg_strap_pad_ctrl      ),
 	      .system_strap            (system_strap            ),
 	      .strap_sticky            (strap_sticky            ),
+	      .strap_uartm             (strap_uartm             ),
 
           .wbd_int_rst_n           (wbd_int_rst_n           ),
           .wbd_pll_rst_n           (wbd_pll_rst_n           ),
@@ -1378,6 +1384,7 @@
           .cfg_strap_pad_ctrl      (cfg_strap_pad_ctrl      ),
           .system_strap            (system_strap            ),
           .strap_sticky            (strap_sticky            ),
+	      .strap_uartm             (strap_uartm             ),
 
           .user_clock1             (wb_clk_i                ),
           .user_clock2             (user_clock2             ),
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index cabcdc1..e35f5cb 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -108,6 +108,7 @@
         output  logic              cfg_strap_pad_ctrl,
 	    output  logic [31:0]       system_strap      ,
 	    input   logic [31:0]       strap_sticky      ,
+	    input   logic [1:0]        strap_uartm       ,
 
 
     // Master Port
@@ -265,20 +266,27 @@
 //    Uart Baud-16x computation
 //      Assumption is default wb clock is 50Mhz 
 //      For 9600 Baud
-//        50,000,000/(9600*16) = 325;
-//      Configured Value = 325-2 = 323
+//        50,000,000/(9600*16) = 324;
+//      Configured Value = 325-2 = 324
 //      Internally we have used pos and neg counter
 //      it has additional 1 cycle additional count,
 //      so we are subtracting desired count by 2
+// strap_uartm
+//     2'b00 - 50Mhz - 324
+//     2'b01 - 40Mhz - 258
+//     2'b10 - 60Mhz - 389
+//     2'b11 - Load from LA
 //-------------------------------------------------
 
-wire strap_uart_cfg_mode = system_strap[`STRAP_UARTM_CFG];
 
-wire       cfg_uartm_tx_enable   = (strap_uart_cfg_mode==0) ? la_data_in[1]     : 1'b1;
-wire       cfg_uartm_rx_enable   = (strap_uart_cfg_mode==0) ? la_data_in[2]     : 1'b1;
-wire       cfg_uartm_stop_bit    = (strap_uart_cfg_mode==0) ? la_data_in[3]     : 1'b1;
-wire [11:0]cfg_uart_baud_16x     = (strap_uart_cfg_mode==0) ? la_data_in[15:4]  : 323;
-wire [1:0] cfg_uartm_cfg_pri_mod = (strap_uart_cfg_mode==0) ? la_data_in[17:16] : 2'b0;
+wire       cfg_uartm_tx_enable   = (strap_uartm==2'b11) ? la_data_in[1]     : 1'b1;
+wire       cfg_uartm_rx_enable   = (strap_uartm==2'b11) ? la_data_in[2]     : 1'b1;
+wire       cfg_uartm_stop_bit    = (strap_uartm==2'b11) ? la_data_in[3]     : 1'b1;
+wire [1:0] cfg_uartm_cfg_pri_mod = (strap_uartm==2'b11) ? la_data_in[17:16] : 2'b0;
+
+wire [11:0]cfg_uart_baud_16x     = (strap_uartm==2'b00) ? 324:
+                                   (strap_uartm==2'b01) ? 258:
+                                   (strap_uartm==2'b10) ? 389: la_data_in[15:4];
 
 
 // UART Master