)]}'
{
  "commit": "3084fb74abea4cecfe61f5bcb7210ea18ef45dd4",
  "tree": "4885cf1ef10d876aa72392691b0b5a0ac917aa50",
  "parents": [
    "ef03218dc27fc14cd0abbd3079348da5a7b90991"
  ],
  "author": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Thu Jan 06 10:44:39 2022 +0530"
  },
  "committer": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Thu Jan 06 10:44:39 2022 +0530"
  },
  "message": "tcm memory access bug fix and riscv regression update\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "28a6d02f7b20a35f36a2c2e2ea334434341b4ecf",
      "old_mode": 33188,
      "old_path": "README.md",
      "new_id": "72719673964d8307f9b84668cb07f8684e1b9d33",
      "new_mode": 33188,
      "new_path": "README.md"
    },
    {
      "type": "modify",
      "old_id": "86fc231941fe98dcc5437b4859a5890bebf4ed8b",
      "old_mode": 33188,
      "old_path": "signoff/pinmux/final_summary_report.csv",
      "new_id": "7241d947aa6031f2d5646156cc2e478aa8641e6e",
      "new_mode": 33188,
      "new_path": "signoff/pinmux/final_summary_report.csv"
    },
    {
      "type": "modify",
      "old_id": "d573af167a7130c2d42fa7b7e5868c4fccc99246",
      "old_mode": 33188,
      "old_path": "signoff/syntacore/final_summary_report.csv",
      "new_id": "04c97bded3e8789c7aecfe0ab777861605cb8ed6",
      "new_mode": 33188,
      "new_path": "signoff/syntacore/final_summary_report.csv"
    },
    {
      "type": "modify",
      "old_id": "22fcfa7b1c5ec0cf06ffcbc6b38cb5dfb5c5ad4d",
      "old_mode": 33188,
      "old_path": "signoff/user_project_wrapper/final_summary_report.csv",
      "new_id": "a6e08b89fe70eba9d1b66e41a438ad5f58311a1c",
      "new_mode": 33188,
      "new_path": "signoff/user_project_wrapper/final_summary_report.csv"
    },
    {
      "type": "modify",
      "old_id": "2ed56863c242ab4907cd3eb0cb86ded4769d012f",
      "old_mode": 33188,
      "old_path": "verilog/dv/agents/uart_agent.v",
      "new_id": "72121e9427bbcf638f61f8c9bb269fc1b792005c",
      "new_mode": 33188,
      "new_path": "verilog/dv/agents/uart_agent.v"
    },
    {
      "type": "modify",
      "old_id": "38144e84ea34af669ef4769af3b7381bf0dc3d4c",
      "old_mode": 33188,
      "old_path": "verilog/dv/risc_boot/risc_boot_tb.v",
      "new_id": "4332e90ed9e4f3c2755c7a6f13c459ef0526f255",
      "new_mode": 33188,
      "new_path": "verilog/dv/risc_boot/risc_boot_tb.v"
    },
    {
      "type": "modify",
      "old_id": "1958002f925de9769763fabe9df0b3e80e1f8296",
      "old_mode": 33188,
      "old_path": "verilog/dv/riscv_regress/Makefile",
      "new_id": "645b9cde9e571abadf9317d5a869eb19b9f5e09b",
      "new_mode": 33188,
      "new_path": "verilog/dv/riscv_regress/Makefile"
    },
    {
      "type": "modify",
      "old_id": "8f12e4eba2346d71691d742b7eb89ac2b9b32398",
      "old_mode": 33188,
      "old_path": "verilog/dv/riscv_regress/riscv_runtests.sv",
      "new_id": "bfbb3bb47de17da159842b9e08000b213c8c5d73",
      "new_mode": 33188,
      "new_path": "verilog/dv/riscv_regress/riscv_runtests.sv"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "7e1401b24ec356c06b98b6b70c7db63ae6594045",
      "new_mode": 33261,
      "new_path": "verilog/dv/riscv_regress/run_iverilog"
    },
    {
      "type": "delete",
      "old_id": "e53865fd60992ff3087d069f74e271b7c1188b16",
      "old_mode": 33188,
      "old_path": "verilog/dv/riscv_regress/uprj_netlists.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "modify",
      "old_id": "4dd6abf2d0c94daad301329d6e59d0d36f2a50d9",
      "old_mode": 33188,
      "old_path": "verilog/dv/riscv_regress/user_risc_regress_tb.v",
      "new_id": "894ffb3e63ffb4e9ba738f6f587f037c3f1da377",
      "new_mode": 33188,
      "new_path": "verilog/dv/riscv_regress/user_risc_regress_tb.v"
    },
    {
      "type": "modify",
      "old_id": "549a5e57a796c252c56d420b946291e155b1ef04",
      "old_mode": 33188,
      "old_path": "verilog/dv/user_risc_boot/Makefile",
      "new_id": "d84401da7f5e8a3e230e8bdaa92ef0e0edeb5484",
      "new_mode": 33188,
      "new_path": "verilog/dv/user_risc_boot/Makefile"
    },
    {
      "type": "modify",
      "old_id": "b5689918c90eaffaefdf5ee23fc28efdce519724",
      "old_mode": 33188,
      "old_path": "verilog/rtl/pinmux/src/pinmux_reg.sv",
      "new_id": "e3b9044a868a5533b2e113568d1a7bf552d0a62d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/pinmux/src/pinmux_reg.sv"
    },
    {
      "type": "modify",
      "old_id": "2d354429f123ef63cd8b5b6b6206f3d0727d26d9",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/sim/tests/common/common.mk",
      "new_id": "6075f73d4c1cb1e2b90662fa5a87321965c25010",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/common/common.mk"
    },
    {
      "type": "modify",
      "old_id": "31653f1a4f3978b053c141bb225f522af6062f1f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/sim/tests/common/link.ld",
      "new_id": "6df66593567b021ee986e950c4b6f3d228224a9a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/common/link.ld"
    },
    {
      "type": "modify",
      "old_id": "c49465e82427fedada99d58dca2077108a4910d3",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld",
      "new_id": "3840ec36ae4cacdeabbccf8e042493dbd4da7858",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld"
    },
    {
      "type": "modify",
      "old_id": "d2b210bd364217170e0a8e57a7fc1c23698bccbb",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/Makefile",
      "new_id": "05584345449227b07cc4675ba48f5e814bf0f0f7",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/Makefile"
    },
    {
      "type": "modify",
      "old_id": "945519cf509975e4d3bb71c2abb54cc76f0acc9e",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/Makefile",
      "new_id": "b95364247c20658a3724521b0378890e8e8aab86",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/Makefile"
    },
    {
      "type": "modify",
      "old_id": "2524fd330d1fbf4e5dc7e83139adfbba4af64900",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv",
      "new_id": "db8174e3acbe9dedaa20a9815d3f58a74322e702",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv"
    },
    {
      "type": "modify",
      "old_id": "8ef66fd725dbb29f46a7e84de1e146a7c6b708d4",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "2f5d2c13e264170a0574536787f87a78fcbae84f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}
