diff --git a/docs/source/_static/user_project_wrapper.gds.png b/docs/source/_static/user_project_wrapper.gds.png
new file mode 100644
index 0000000..b856180
--- /dev/null
+++ b/docs/source/_static/user_project_wrapper.gds.png
Binary files differ
diff --git a/openlane/clk_skew_adjust/config.tcl b/openlane/clk_skew_adjust/config.tcl
index d1b3e25..df2b534 100644
--- a/openlane/clk_skew_adjust/config.tcl
+++ b/openlane/clk_skew_adjust/config.tcl
@@ -44,6 +44,8 @@
 ### Macro Placement
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
+#set ::env(FP_SIZING) absolute
+#set ::env(DIE_AREA) "0 0 50 50"
 
 
 
@@ -56,7 +58,7 @@
 # Fill this
 set ::env(CLOCK_TREE_SYNTH) 0
 
-set ::env(CELL_PAD) 0
+set ::env(CELL_PAD) 4
 
 set ::env(FP_CORE_UTIL) 40
 set ::env(PL_RANDOM_GLB_PLACEMENT) 1
diff --git a/openlane/sdram/base.sdc b/openlane/sdram/base.sdc
index 350ae31..2bdd058 100644
--- a/openlane/sdram/base.sdc
+++ b/openlane/sdram/base.sdc
@@ -35,6 +35,7 @@
 
 
 set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {wb_rst_n}
+set_input_delay 2.0 -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] {sdram_resetn}
 
 set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_stb_i*]
 set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_addr_i*]
@@ -54,6 +55,8 @@
 set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_twr_d*]
 set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfsh*]
 set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfmax*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_colbits*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_width*]
 
 set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_dat_o*]
 set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_ack_o*]
@@ -68,37 +71,69 @@
 puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
 puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
 
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[0]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[1]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[2]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[3]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[4]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[5]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[6]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[7]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[8]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[9]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[10]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[11]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[12]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[13]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[14]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[15]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[16]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[17]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[18]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[19]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[20]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[21]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[22]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[23]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[24]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[25]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[26]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[27]]
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[28]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[0]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[1]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[2]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[3]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[4]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[5]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[6]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[7]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[8]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[9]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[10]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[11]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[12]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[13]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[14]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[15]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[16]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[17]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[18]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[19]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[20]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[21]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[22]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[23]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[24]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[25]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[26]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[27]]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[28]]
 #set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[29]] Masked SDRAM clock
-set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_oeb*]
+set_output_delay $sdram_output_delay_value  -max -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_oeb*]
+
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[0]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[1]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[2]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[3]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[4]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[5]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[6]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[7]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[8]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[9]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[10]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[11]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[12]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[13]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[14]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[15]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[16]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[17]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[18]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[19]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[20]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[21]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[22]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[23]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[24]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[25]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[26]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[27]]
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[28]]
+#set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_out[29]] Masked SDRAM clock
+set_output_delay -0.5  -min -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port io_oeb*]
 
 ################################################
 # PAD SDRAM Clock domain input output
@@ -107,7 +142,8 @@
 ################################################
 
 create_clock [get_ports $::env(PAD_SDRAM_CLOCK_PORT)]  -name $::env(PAD_SDRAM_CLOCK_PORT)  -period $::env(SDRAM_CLOCK_PERIOD)
-set_input_delay  $sdram_input_delay_value   -clock [get_clocks $::env(PAD_SDRAM_CLOCK_PORT)] [get_port io_in*]
+set_input_delay  $sdram_input_delay_value -max  -clock [get_clocks $::env(PAD_SDRAM_CLOCK_PORT)] [get_port io_in*]
+set_input_delay  1                        -min -clock [get_clocks $::env(PAD_SDRAM_CLOCK_PORT)] [get_port io_in*]
 
 
 set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_PORT)] -group [get_clocks $::env(SDRAM_CLOCK_PORT)]
diff --git a/openlane/sdram/pin_order.cfg b/openlane/sdram/pin_order.cfg
index 8f3bcb1..d05e596 100644
--- a/openlane/sdram/pin_order.cfg
+++ b/openlane/sdram/pin_order.cfg
@@ -6,7 +6,6 @@
 wb_rst_n            0000 1
 
 
-
 #N
 io_oeb\[29\]  
 io_out\[29\]        
@@ -163,6 +162,38 @@
 cfg_sdr_rfmax\[1\]   0000 59
 cfg_sdr_rfmax\[0\]   0000 60
 
+sdram_debug\[0\]     200  0
+sdram_debug\[1\]   
+sdram_debug\[2\]   
+sdram_debug\[3\]   
+sdram_debug\[4\]   
+sdram_debug\[5\]   
+sdram_debug\[6\]   
+sdram_debug\[7\]   
+sdram_debug\[8\]   
+sdram_debug\[9\]   
+sdram_debug\[10\]   
+sdram_debug\[11\]   
+sdram_debug\[12\]   
+sdram_debug\[13\]   
+sdram_debug\[14\]   
+sdram_debug\[15\]   
+sdram_debug\[16\]   
+sdram_debug\[17\]   
+sdram_debug\[18\]   
+sdram_debug\[19\]   
+sdram_debug\[20\]   
+sdram_debug\[21\]   
+sdram_debug\[22\]   
+sdram_debug\[23\]   
+sdram_debug\[24\]   
+sdram_debug\[25\]   
+sdram_debug\[26\]   
+sdram_debug\[27\]   
+sdram_debug\[28\]   
+sdram_debug\[29\]   
+sdram_debug\[30\]   
+sdram_debug\[31\]   
 
 #S
 wb_stb_i             0000 0
diff --git a/openlane/spi_master/base.sdc b/openlane/spi_master/base.sdc
index cd78ed8..aab27ac 100644
--- a/openlane/spi_master/base.sdc
+++ b/openlane/spi_master/base.sdc
@@ -19,10 +19,16 @@
 set ::env(WB_CLOCK_PERIOD) "10"
 set ::env(WB_CLOCK_PORT) "mclk"
 
+set ::env(SPI_CLOCK_PORT)  "spiclk"
+set ::env(SPI_CLOCK_PERIOD) "20"
+
 ######################################
 # WB Clock domain input output
 ######################################
 create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_PORT)  -period $::env(WB_CLOCK_PERIOD)
+
+create_generated_clock -name $::env(SPI_CLOCK_PORT) -source [get_ports $::env(WB_CLOCK_PORT)] -master_clock $::env(WB_CLOCK_PORT) -divide_by 2  -add -comment "SPI Clock Out"  [get_port io_out[0]]
+
 set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
 set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
 puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
@@ -37,27 +43,54 @@
 set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_dat_i*]
 set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_sel_i*]
 
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_in[5]]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_in[4]]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_in[3]]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_in[2]]
 
 set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_dat_o*]
 set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_ack_o*]
 set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_err_o*]
 set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_debug*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_out[5]]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_out[4]]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_out[3]]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_out[2]]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_out[1]]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_out[0]]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_oeb[5]]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_oeb[4]]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_oeb[3]]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_oeb[2]]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_oeb[1]]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port io_oeb[0]]
+
+### SPI I/F constaints
+set spi_input_delay_value  [expr $::env(SPI_CLOCK_PERIOD) * 0.6]
+set spi_output_delay_value [expr $::env(SPI_CLOCK_PERIOD) * 0.6]
+
+set_input_delay  6   -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[5]]
+set_input_delay  6   -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[4]]
+set_input_delay  6   -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[3]]
+set_input_delay  6   -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[2]]
+
+set_input_delay  0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[5]]
+set_input_delay  0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[4]]
+set_input_delay  0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[3]]
+set_input_delay  0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_in[2]]
+
+#io_out[0] is spiclcok
+#set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[0]]
+set_output_delay 6  -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[5]]
+set_output_delay 6  -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[4]]
+set_output_delay 6  -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[3]]
+set_output_delay 6  -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[2]]
+set_output_delay 6  -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[1]]
+
+set_output_delay 6  -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[5]]
+set_output_delay 6  -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[4]]
+set_output_delay 6  -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[3]]
+set_output_delay 6  -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[2]]
+set_output_delay 6  -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[1]]
+
+set_output_delay -0.5   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[5]]
+set_output_delay -0.5   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[4]]
+set_output_delay -0.5   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[3]]
+set_output_delay -0.5   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[2]]
+set_output_delay 0.0    -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[1]]
+
+# Chip select asserted multiple cycle eariler than spi clock
+set_output_delay 0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[1]]
+
+set_output_delay 0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[5]]
+set_output_delay 0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[4]]
+set_output_delay 0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[3]]
+set_output_delay 0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[2]]
+set_output_delay 0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[1]]
 
 # TODO set this as parameter
 set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
diff --git a/openlane/spi_master/config.tcl b/openlane/spi_master/config.tcl
index 7c87b91..ade6318 100755
--- a/openlane/spi_master/config.tcl
+++ b/openlane/spi_master/config.tcl
@@ -45,6 +45,7 @@
         $script_dir/../../verilog/rtl/spi_master/src/spim_rx.sv \
         $script_dir/../../verilog/rtl/spi_master/src/spim_tx.sv "
 
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 set ::env(SDC_FILE) "$script_dir/base.sdc"
 set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
 
diff --git a/openlane/spi_master/pin_order.cfg b/openlane/spi_master/pin_order.cfg
index 2413319..fc7556c 100644
--- a/openlane/spi_master/pin_order.cfg
+++ b/openlane/spi_master/pin_order.cfg
@@ -4,42 +4,7 @@
 #W
 mclk                   0000 0
 rst_n                  
-spi_debug\[31\]        
-spi_debug\[30\]        
-spi_debug\[29\]        
-spi_debug\[28\]        
-spi_debug\[27\]        
-spi_debug\[26\]        
-spi_debug\[25\]        
-spi_debug\[24\]        
-spi_debug\[23\]        
-spi_debug\[22\]        
-spi_debug\[21\]        
-spi_debug\[20\]        
-spi_debug\[19\]        
-spi_debug\[18\]        
-spi_debug\[17\]        
-spi_debug\[16\]        
-spi_debug\[15\]        
-spi_debug\[14\]        
-spi_debug\[13\]        
-spi_debug\[12\]        
-spi_debug\[11\]        
-spi_debug\[10\]        
-spi_debug\[9\]        
-spi_debug\[8\]        
-spi_debug\[7\]        
-spi_debug\[6\]        
-spi_debug\[5\]        
-spi_debug\[4\]        
-spi_debug\[3\]        
-spi_debug\[2\]        
-spi_debug\[1\]        
-spi_debug\[0\]        
-
-
-#N
-io_in\[5\]             0000 0
+io_in\[5\]             0200 0
 io_out\[5\]        
 io_oeb\[5\]  
 io_in\[4\]         
@@ -58,6 +23,39 @@
 io_out\[0\]        
 io_oeb\[0\]  
 
+#E
+spi_debug\[0\]        0000 0 
+spi_debug\[1\]        
+spi_debug\[2\]        
+spi_debug\[3\]        
+spi_debug\[4\]        
+spi_debug\[5\]        
+spi_debug\[6\]        
+spi_debug\[7\]        
+spi_debug\[8\]        
+spi_debug\[9\]        
+spi_debug\[10\]        
+spi_debug\[11\]        
+spi_debug\[12\]        
+spi_debug\[13\]        
+spi_debug\[14\]        
+spi_debug\[15\]        
+spi_debug\[16\]        
+spi_debug\[17\]        
+spi_debug\[18\]        
+spi_debug\[19\]        
+spi_debug\[20\]        
+spi_debug\[21\]        
+spi_debug\[22\]        
+spi_debug\[23\]        
+spi_debug\[24\]        
+spi_debug\[25\]        
+spi_debug\[26\]        
+spi_debug\[27\]        
+spi_debug\[28\]        
+spi_debug\[29\]        
+spi_debug\[30\]        
+spi_debug\[31\]        
 
 #S
 wbd_stb_i              0000 0
diff --git a/openlane/syntacore/pin_order.cfg b/openlane/syntacore/pin_order.cfg
index fb94b98..1ecdcf1 100644
--- a/openlane/syntacore/pin_order.cfg
+++ b/openlane/syntacore/pin_order.cfg
@@ -10,7 +10,8 @@
 wb_clk            0000 0
 wb_rst_n          
 pwrup_rst_n       
-rst_n             
+rst_n        
+     
 
 #N
 wbd_imem_stb_o          0000 0
@@ -272,3 +273,71 @@
 fuse_mhartid\[2\] 
 fuse_mhartid\[1\] 
 fuse_mhartid\[0\] 
+
+#S
+
+riscv_debug\[0\]   500  0 4
+riscv_debug\[1\]
+riscv_debug\[2\]
+riscv_debug\[3\]
+riscv_debug\[4\]
+riscv_debug\[5\]
+riscv_debug\[6\]
+riscv_debug\[7\]
+riscv_debug\[8\]
+riscv_debug\[9\]
+riscv_debug\[10\]
+riscv_debug\[11\]
+riscv_debug\[12\]
+riscv_debug\[13\]
+riscv_debug\[14\]
+riscv_debug\[15\]
+riscv_debug\[16\]
+riscv_debug\[17\]
+riscv_debug\[18\]
+riscv_debug\[19\]
+riscv_debug\[20\]
+riscv_debug\[21\]
+riscv_debug\[22\]
+riscv_debug\[23\]
+riscv_debug\[24\]
+riscv_debug\[25\]
+riscv_debug\[26\]
+riscv_debug\[27\]
+riscv_debug\[28\]
+riscv_debug\[29\]
+riscv_debug\[30\]
+riscv_debug\[31\]
+riscv_debug\[32\]
+riscv_debug\[33\]
+riscv_debug\[34\]
+riscv_debug\[35\]
+riscv_debug\[36\]
+riscv_debug\[37\]
+riscv_debug\[38\]
+riscv_debug\[39\]
+riscv_debug\[40\]
+riscv_debug\[41\]
+riscv_debug\[42\]
+riscv_debug\[43\]
+riscv_debug\[44\]
+riscv_debug\[45\]
+riscv_debug\[46\]
+riscv_debug\[47\]
+riscv_debug\[48\]
+riscv_debug\[49\]
+riscv_debug\[50\]
+riscv_debug\[51\]
+riscv_debug\[52\]
+riscv_debug\[53\]
+riscv_debug\[54\]
+riscv_debug\[55\]
+riscv_debug\[56\]
+riscv_debug\[57\]
+riscv_debug\[58\]
+riscv_debug\[59\]
+riscv_debug\[60\]
+riscv_debug\[61\]
+riscv_debug\[62\]
+riscv_debug\[63\]
+
diff --git a/openlane/uart/base.sdc b/openlane/uart/base.sdc
index c93fb52..01e5123 100644
--- a/openlane/uart/base.sdc
+++ b/openlane/uart/base.sdc
@@ -19,12 +19,23 @@
 set ::env(CORE_CLOCK_PERIOD) "10"
 set ::env(CORE_CLOCK_PORT)   "app_clk"
 
+set ::env(LINE_CLOCK_PERIOD) "100"
+set ::env(LINE_CLOCK_PORT)   "line_clk"
+
 ######################################
 # WB Clock domain input output
 ######################################
 create_clock [get_ports $::env(CORE_CLOCK_PORT)]  -name $::env(CORE_CLOCK_PORT)  -period $::env(CORE_CLOCK_PERIOD)
+create_clock [get_pins  u_lineclk_buf/X ]  -name $::env(LINE_CLOCK_PORT)  -period $::env(LINE_CLOCK_PERIOD)
+
+
+set_clock_groups -name sys_clk -asynchronous -group $::env(CORE_CLOCK_PORT) -group $::env(LINE_CLOCK_PORT)
+
 set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
 set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
+
+set line_input_delay_value  [expr $::env(LINE_CLOCK_PERIOD) * 0.6]
+set line_output_delay_value [expr $::env(LINE_CLOCK_PERIOD) * 0.6]
 puts "\[INFO\]: Setting wb output delay to:$core_output_delay_value"
 puts "\[INFO\]: Setting wb input delay to: $core_input_delay_value"
 
@@ -41,6 +52,9 @@
 set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_PORT)] [get_port reg_rdata*]
 set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_PORT)] [get_port reg_ack*]
 
+set_input_delay  $line_input_delay_value   -clock [get_clocks $::env(LINE_CLOCK_PORT)] [get_port io_in*]
+set_output_delay $line_input_delay_value   -clock [get_clocks $::env(LINE_CLOCK_PORT)] [get_port io_oeb*]
+set_output_delay $line_output_delay_value  -clock [get_clocks $::env(LINE_CLOCK_PORT)] [get_port io_out*]
 
 
 # TODO set this as parameter
diff --git a/openlane/uart/config.tcl b/openlane/uart/config.tcl
index 51088e3..0a94c66 100644
--- a/openlane/uart/config.tcl
+++ b/openlane/uart/config.tcl
@@ -47,6 +47,7 @@
     $script_dir/../../verilog/rtl/lib/registers.v        \
     "
 
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 #set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
 
 set ::env(SDC_FILE) "$script_dir/base.sdc"
diff --git a/openlane/wb_host/base.sdc b/openlane/wb_host/base.sdc
new file mode 100644
index 0000000..0b5df4d
--- /dev/null
+++ b/openlane/wb_host/base.sdc
@@ -0,0 +1,67 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+set_units -time ns
+set ::env(WBM_CLOCK_PERIOD) "10"
+set ::env(WBM_CLOCK_PORT)   "wbm_clk_i"
+
+set ::env(WBS_CLOCK_PERIOD) "10"
+set ::env(WBS_CLOCK_PORT)   "wbs_clk_i"
+
+######################################
+# WB Clock domain input output
+######################################
+create_clock [get_ports $::env(WBM_CLOCK_PORT)]  -name $::env(WBM_CLOCK_PORT)  -period $::env(WBM_CLOCK_PERIOD)
+create_clock [get_ports $::env(WBS_CLOCK_PORT)]  -name $::env(WBS_CLOCK_PORT)  -period $::env(WBS_CLOCK_PERIOD)
+
+
+set wb_input_delay_value [expr $::env(WBM_CLOCK_PERIOD) * 0.6]
+set wb_output_delay_value [expr $::env(WBM_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+
+
+set_input_delay 2.0 -clock [get_clocks $::env(WBM_CLOCK_PORT)] {wbm_rst_i}
+set_input_delay 2.0 -clock [get_clocks $::env(WBM_CLOCK_PORT)] {wbm_rst_i}
+
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port wbm_cyc_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port wbm_stb_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port wbm_adr_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port wbm_we_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port wbm_dat_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port wbm_sel_i*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port wbm_dat_o*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port wbm_ack_o*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WBM_CLOCK_PORT)] [get_port wbm_err_o*]
+
+set_output_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_cyc_o*]
+set_output_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_stb_o*]
+set_output_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_adr_o*]
+set_output_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_we_o*]
+set_output_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_dat_o*]
+set_output_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_sel_o*]
+
+set_input_delay $wb_output_delay_value  -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_dat_i*]
+set_input_delay $wb_output_delay_value  -clock [get_clocks $::env(WBS_CLOCK_PORT)] [get_port wbs_ack_i*]
+
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 1c7005b..6c17252 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -42,8 +42,8 @@
      $script_dir/../../verilog/rtl/lib/clk_ctl.v          \
      $script_dir/../../verilog/rtl/lib/registers.v"
 
-#set ::env(SDC_FILE) "$script_dir/base.sdc"
-#set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
 
 set ::env(LEC_ENABLE) 0
 
@@ -57,7 +57,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 1000 200"
+set ::env(DIE_AREA) "0 0 400 200"
 
 
 # If you're going to use multiple power domains, then keep this disabled.
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 488bc22..db8f388 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -118,390 +118,6 @@
 wbm_dat_o\[31\]  
 wbm_err_o        
 
-la_data_in\[0\]    500 0  2
-la_data_out\[0\]
-la_oenb\[0\]
-la_data_in\[1\]
-la_data_out\[1\]
-la_oenb\[1\]
-la_data_in\[2\]
-la_data_out\[2\]
-la_oenb\[2\]
-la_data_in\[3\]
-la_data_out\[3\]
-la_oenb\[3\]
-la_data_in\[4\]
-la_data_out\[4\]
-la_oenb\[4\]
-la_data_in\[5\]
-la_data_out\[5\]
-la_oenb\[5\]
-la_data_in\[6\]
-la_data_out\[6\]
-la_oenb\[6\]
-la_data_in\[7\]
-la_data_out\[7\]
-la_oenb\[7\]
-la_data_in\[8\]
-la_data_out\[8\]
-la_oenb\[8\]
-la_data_in\[9\]
-la_data_out\[9\]
-la_oenb\[9\]
-la_data_in\[10\]
-la_data_out\[10\]
-la_oenb\[10\]
-la_data_in\[11\]
-la_data_out\[11\]
-la_oenb\[11\]
-la_data_in\[12\]
-la_data_out\[12\]
-la_oenb\[12\]
-la_data_in\[13\]
-la_data_out\[13\]
-la_oenb\[13\]
-la_data_in\[14\]
-la_data_out\[14\]
-la_oenb\[14\]
-la_data_in\[15\]
-la_data_out\[15\]
-la_oenb\[15\]
-la_data_in\[16\]
-la_data_out\[16\]
-la_oenb\[16\]
-la_data_in\[17\]
-la_data_out\[17\]
-la_oenb\[17\]
-la_data_in\[18\]
-la_data_out\[18\]
-la_oenb\[18\]
-la_data_in\[19\]
-la_data_out\[19\]
-la_oenb\[19\]
-la_data_in\[20\]
-la_data_out\[20\]
-la_oenb\[20\]
-la_data_in\[21\]
-la_data_out\[21\]
-la_oenb\[21\]
-la_data_in\[22\]
-la_data_out\[22\]
-la_oenb\[22\]
-la_data_in\[23\]
-la_data_out\[23\]
-la_oenb\[23\]
-la_data_in\[24\]
-la_data_out\[24\]
-la_oenb\[24\]
-la_data_in\[25\]
-la_data_out\[25\]
-la_oenb\[25\]
-la_data_in\[26\]
-la_data_out\[26\]
-la_oenb\[26\]
-la_data_in\[27\]
-la_data_out\[27\]
-la_oenb\[27\]
-la_data_in\[28\]
-la_data_out\[28\]
-la_oenb\[28\]
-la_data_in\[29\]
-la_data_out\[29\]
-la_oenb\[29\]
-la_data_in\[30\]
-la_data_out\[30\]
-la_oenb\[30\]
-la_data_in\[31\]
-la_data_out\[31\]
-la_oenb\[31\]
-la_data_in\[32\]
-la_data_out\[32\]
-la_oenb\[32\]
-la_data_in\[33\]
-la_data_out\[33\]
-la_oenb\[33\]
-la_data_in\[34\]
-la_data_out\[34\]
-la_oenb\[34\]
-la_data_in\[35\]
-la_data_out\[35\]
-la_oenb\[35\]
-la_data_in\[36\]
-la_data_out\[36\]
-la_oenb\[36\]
-la_data_in\[37\]
-la_data_out\[37\]
-la_oenb\[37\]
-la_data_in\[38\]
-la_data_out\[38\]
-la_oenb\[38\]
-la_data_in\[39\]
-la_data_out\[39\]
-la_oenb\[39\]
-la_data_in\[40\]
-la_data_out\[40\]
-la_oenb\[40\]
-la_data_in\[41\]
-la_data_out\[41\]
-la_oenb\[41\]
-la_data_in\[42\]
-la_data_out\[42\]
-la_oenb\[42\]
-la_data_in\[43\]
-la_data_out\[43\]
-la_oenb\[43\]
-la_data_in\[44\]
-la_data_out\[44\]
-la_oenb\[44\]
-la_data_in\[45\]
-la_data_out\[45\]
-la_oenb\[45\]
-la_data_in\[46\]
-la_data_out\[46\]
-la_oenb\[46\]
-la_data_in\[47\]
-la_data_out\[47\]
-la_oenb\[47\]
-la_data_in\[48\]
-la_data_out\[48\]
-la_oenb\[48\]
-la_data_in\[49\]
-la_data_out\[49\]
-la_oenb\[49\]
-la_data_in\[50\]
-la_data_out\[50\]
-la_oenb\[50\]
-la_data_in\[51\]
-la_data_out\[51\]
-la_oenb\[51\]
-la_data_in\[52\]
-la_data_out\[52\]
-la_oenb\[52\]
-la_data_in\[53\]
-la_data_out\[53\]
-la_oenb\[53\]
-la_data_in\[54\]
-la_data_out\[54\]
-la_oenb\[54\]
-la_data_in\[55\]
-la_data_out\[55\]
-la_oenb\[55\]
-la_data_in\[56\]
-la_data_out\[56\]
-la_oenb\[56\]
-la_data_in\[57\]
-la_data_out\[57\]
-la_oenb\[57\]
-la_data_in\[58\]
-la_data_out\[58\]
-la_oenb\[58\]
-la_data_in\[59\]
-la_data_out\[59\]
-la_oenb\[59\]
-la_data_in\[60\]
-la_data_out\[60\]
-la_oenb\[60\]
-la_data_in\[61\]
-la_data_out\[61\]
-la_oenb\[61\]
-la_data_in\[62\]
-la_data_out\[62\]
-la_oenb\[62\]
-la_data_in\[63\]
-la_data_out\[63\]
-la_oenb\[63\]
-la_data_in\[64\]
-la_data_out\[64\]
-la_oenb\[64\]
-la_data_in\[65\]
-la_data_out\[65\]
-la_oenb\[65\]
-la_data_in\[66\]
-la_data_out\[66\]
-la_oenb\[66\]
-la_data_in\[67\]
-la_data_out\[67\]
-la_oenb\[67\]
-la_data_in\[68\]
-la_data_out\[68\]
-la_oenb\[68\]
-la_data_in\[69\]
-la_data_out\[69\]
-la_oenb\[69\]
-la_data_in\[70\]
-la_data_out\[70\]
-la_oenb\[70\]
-la_data_in\[71\]
-la_data_out\[71\]
-la_oenb\[71\]
-la_data_in\[72\]
-la_data_out\[72\]
-la_oenb\[72\]
-la_data_in\[73\]
-la_data_out\[73\]
-la_oenb\[73\]
-la_data_in\[74\]
-la_data_out\[74\]
-la_oenb\[74\]
-la_data_in\[75\]
-la_data_out\[75\]
-la_oenb\[75\]
-la_data_in\[76\]
-la_data_out\[76\]
-la_oenb\[76\]
-la_data_in\[77\]
-la_data_out\[77\]
-la_oenb\[77\]
-la_data_in\[78\]
-la_data_out\[78\]
-la_oenb\[78\]
-la_data_in\[79\]
-la_data_out\[79\]
-la_oenb\[79\]
-la_data_in\[80\]
-la_data_out\[80\]
-la_oenb\[80\]
-la_data_in\[81\]
-la_data_out\[81\]
-la_oenb\[81\]
-la_data_in\[82\]
-la_data_out\[82\]
-la_oenb\[82\]
-la_data_in\[83\]
-la_data_out\[83\]
-la_oenb\[83\]
-la_data_in\[84\]
-la_data_out\[84\]
-la_oenb\[84\]
-la_data_in\[85\]
-la_data_out\[85\]
-la_oenb\[85\]
-la_data_in\[86\]
-la_data_out\[86\]
-la_oenb\[86\]
-la_data_in\[87\]
-la_data_out\[87\]
-la_oenb\[87\]
-la_data_in\[88\]
-la_data_out\[88\]
-la_oenb\[88\]
-la_data_in\[89\]
-la_data_out\[89\]
-la_oenb\[89\]
-la_data_in\[90\]
-la_data_out\[90\]
-la_oenb\[90\]
-la_data_in\[91\]
-la_data_out\[91\]
-la_oenb\[91\]
-la_data_in\[92\]
-la_data_out\[92\]
-la_oenb\[92\]
-la_data_in\[93\]
-la_data_out\[93\]
-la_oenb\[93\]
-la_data_in\[94\]
-la_data_out\[94\]
-la_oenb\[94\]
-la_data_in\[95\]
-la_data_out\[95\]
-la_oenb\[95\]
-la_data_in\[96\]
-la_data_out\[96\]
-la_oenb\[96\]
-la_data_in\[97\]
-la_data_out\[97\]
-la_oenb\[97\]
-la_data_in\[98\]
-la_data_out\[98\]
-la_oenb\[98\]
-la_data_in\[99\]
-la_data_out\[99\]
-la_oenb\[99\]
-la_data_in\[100\]
-la_data_out\[100\]
-la_oenb\[100\]
-la_data_in\[101\]
-la_data_out\[101\]
-la_oenb\[101\]
-la_data_in\[102\]
-la_data_out\[102\]
-la_oenb\[102\]
-la_data_in\[103\]
-la_data_out\[103\]
-la_oenb\[103\]
-la_data_in\[104\]
-la_data_out\[104\]
-la_oenb\[104\]
-la_data_in\[105\]
-la_data_out\[105\]
-la_oenb\[105\]
-la_data_in\[106\]
-la_data_out\[106\]
-la_oenb\[106\]
-la_data_in\[107\]
-la_data_out\[107\]
-la_oenb\[107\]
-la_data_in\[108\]
-la_data_out\[108\]
-la_oenb\[108\]
-la_data_in\[109\]
-la_data_out\[109\]
-la_oenb\[109\]
-la_data_in\[110\]
-la_data_out\[110\]
-la_oenb\[110\]
-la_data_in\[111\]
-la_data_out\[111\]
-la_oenb\[111\]
-la_data_in\[112\]
-la_data_out\[112\]
-la_oenb\[112\]
-la_data_in\[113\]
-la_data_out\[113\]
-la_oenb\[113\]
-la_data_in\[114\]
-la_data_out\[114\]
-la_oenb\[114\]
-la_data_in\[115\]
-la_data_out\[115\]
-la_oenb\[115\]
-la_data_in\[116\]
-la_data_out\[116\]
-la_oenb\[116\]
-la_data_in\[117\]
-la_data_out\[117\]
-la_oenb\[117\]
-la_data_in\[118\]
-la_data_out\[118\]
-la_oenb\[118\]
-la_data_in\[119\]
-la_data_out\[119\]
-la_oenb\[119\]
-la_data_in\[120\]
-la_data_out\[120\]
-la_oenb\[120\]
-la_data_in\[121\]
-la_data_out\[121\]
-la_oenb\[121\]
-la_data_in\[122\]
-la_data_out\[122\]
-la_oenb\[122\]
-la_data_in\[123\]
-la_data_out\[123\]
-la_oenb\[123\]
-la_data_in\[124\]
-la_data_out\[124\]
-la_oenb\[124\]
-la_data_in\[125\]
-la_data_out\[125\]
-la_oenb\[125\]
-la_data_in\[126\]
-la_data_out\[126\]
-la_oenb\[126\]
-la_data_in\[127\]
-la_data_out\[127\]
-la_oenb\[127\]
 
 #N
 wbs_stb_o        0000 0 2
@@ -682,4 +298,4 @@
 cfg_clk_ctrl2\[2\]
 cfg_clk_ctrl2\[1\]
 cfg_clk_ctrl2\[0\]
-  
+
diff --git a/openlane/yifive/config.tcl b/openlane/yifive/config.tcl
index 1787f12..2fe0330 100644
--- a/openlane/yifive/config.tcl
+++ b/openlane/yifive/config.tcl
@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -12,49 +12,56 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 # SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
 
-
+# Base Configurations. Don't Touch
+# section begin
 set script_dir [file dirname [file normalize [info script]]]
 
-set ::env(DESIGN_NAME) digital_core
+source $script_dir/../../caravel/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
 
+set ::env(DESIGN_NAME) yifive
 set verilog_root $script_dir/../../verilog/
 set lef_root $script_dir/../../lef/
 set gds_root $script_dir/../../gds/
+#section end
+
+# User Configurations
+#
+set ::env(DESIGN_IS_CORE) 1
+set ::env(FP_PDN_CORE_RING) 1
 
 
+## Source Verilog Files
 set ::env(VERILOG_FILES) "\
-        $script_dir/../../verilog/rtl/digital_core/src/digital_core.sv \
+	$script_dir/../../caravel/verilog/rtl/defines.v \
+	$script_dir/yifive.v"
+
+## Clock configurations
+set ::env(CLOCK_PORT) "user_clock2 wb_clk_i"
+#set ::env(CLOCK_NET) "mprj.clk"
+
+set ::env(CLOCK_PERIOD) "10"
+
+## Internal Macros
+### Macro Placement
+set ::env(FP_SIZING) "absolute"
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
+
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
+
+### Black-box verilog and views
+set ::env(VERILOG_FILES_BLACKBOX) "\
+        $script_dir/../../verilog/gl/spi_master.v \
+        $script_dir/../../verilog/gl/wb_interconnect.v \
+        $script_dir/../../verilog/gl/glbl_cfg.v     \
+        $script_dir/../../verilog/gl/uart.v     \
+	$script_dir/../../verilog/gl/sdram.v \
+	$script_dir/../../verilog/gl/wb_host.v \
+	$script_dir/../../verilog/gl/clk_skew_adjust.v \
+	$script_dir/../../verilog/gl/syntacore.v \
 	"
-set ::env(SYNTH_READ_BLACKBOX_LIB) "1"
-set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_PERIOD) "50"
-set ::env(SYNTH_STRATEGY) "AREA 0"
-set ::env(SYNTH_MAX_FANOUT) 4
-
-set ::env(FP_PDN_VPITCH) 50
-set ::env(PDN_CFG) $script_dir/pdn.tcl
-
-set ::env(PL_BASIC_PLACEMENT) 1
-
-set ::env(FP_VERTICAL_HALO) 6
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-
-
-set ::env(DESIGN_IS_CORE) 0
-set ::env(FP_PDN_CORE_RING) 0
-set ::env(GLB_RT_MAXLAYER) 5
-
-
-set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
-set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
-set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
-
-
-set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
 
 set ::env(EXTRA_LEFS) "\
 	$lef_root/spi_master.lef \
@@ -62,6 +69,8 @@
 	$lef_root/wb_interconnect.lef \
 	$lef_root/sdram.lef \
 	$lef_root/uart.lef \
+	$lef_root/wb_host.lef \
+	$lef_root/clk_skew_adjust.lef \
 	$lef_root/syntacore.lef \
 	"
 
@@ -69,45 +78,44 @@
 	$gds_root/spi_master.gds \
 	$gds_root/glbl_cfg.gds \
 	$gds_root/wb_interconnect.gds \
-	$gds_root/sdram.gds \
 	$gds_root/uart.gds \
+	$gds_root/sdram.gds \
+	$gds_root/wb_host.gds \
+	$gds_root/clk_skew_adjust.gds \
 	$gds_root/syntacore.gds \
-        "
-
-set ::env(VERILOG_FILES_BLACKBOX) "\
-        $script_dir/../../verilog/gl/spi_master.v \
-        $script_dir/../../verilog/gl/wb_interconnect.v  \
-        $script_dir/../../verilog/gl/glbl_cfg.v     \
-        $script_dir/../../verilog/gl/uart.v     \
-	$script_dir/../../verilog/gl/sdram.v \
-	$script_dir/../../verilog/gl/syntacore.v \
 	"
 
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 
-set ::env(FP_SIZING) relative
-set ::env(DIE_AREA) "0 0 2500 3500"
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
 
-set ::env(LEC_ENABLE) 0
+set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(FP_PDN_CHECK_NODES) 0
+
+set ::env(RUN_KLAYOUT_DRC) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
 
 
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
-set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.20
-set ::env(PL_TARGET_DENSITY_CELLS) 0.20
-set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
-set ::env(CELL_PAD) 4
+# The following is because there are no std cells in the example wrapper project.
+#set ::env(SYNTH_TOP_LEVEL) 1
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
 
-set ::env(GLB_RT_ADJUSTMENT) 0
-set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
-set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
-set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
-set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
-set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
-set ::env(GLB_RT_TILES) 14
-set ::env(PL_DIAMOND_SEARCH_HEIGHT) "400"
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+#
+set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(FILL_INSERTION) 0
+set ::env(TAP_DECAP_INSERTION) 0
+set ::env(CLOCK_TREE_SYNTH) 0
 
-set ::env(DIODE_INSERTION_STRATEGY) 4
+#set ::env(MAGIC_EXT_USE_GDS) "1"
 
 
+set ::env(PL_DIAMOND_SEARCH_HEIGHT) "250"
 
 
diff --git a/openlane/yifive/macro_placement.cfg b/openlane/yifive/macro_placement.cfg
deleted file mode 100644
index 7b2d9a8..0000000
--- a/openlane/yifive/macro_placement.cfg
+++ /dev/null
@@ -1,5 +0,0 @@
-u_riscv_top		300		1200		N
-u_intercon              300             900             N
-u_sdram_ctrl            1100            300             N
-u_glbl_cfg              2300            300             N
-u_spi_master            200             200             N
diff --git a/openlane/yifive/pdn.tcl b/openlane/yifive/pdn.tcl
deleted file mode 100644
index 19314bf..0000000
--- a/openlane/yifive/pdn.tcl
+++ /dev/null
@@ -1,49 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-# Power nets
-set ::power_nets $::env(VDD_PIN)
-set ::ground_nets $::env(GND_PIN)
-
-set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
-
-pdngen::specify_grid stdcell {
-    name grid
-    rails {
-	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
-    }
-    straps {
-	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
-	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
-    }
-    connect {{met1 met4} {met4 met5}}
-}
-
-pdngen::specify_grid macro {
-    power_pins "VPWR"
-    ground_pins "VGND"
-    blockages "li1 met1 met2 met3 met4"
-    straps { 
-    } 
-    connect {{met4_PIN_ver met5}}
-}
-
-set ::halo 4
-
-# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
-set ::rails_start_with "POWER" ;
-
-# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
-set ::stripes_start_with "POWER" ;
diff --git a/openlane/yifive/pin_order.cfg b/openlane/yifive/pin_order.cfg
index e44d520..90cde69 100644
--- a/openlane/yifive/pin_order.cfg
+++ b/openlane/yifive/pin_order.cfg
@@ -1,37 +1,45 @@
 #BUS_SORT
 #NR
+analog_io\[8\]
 io_in\[15\]
 io_out\[15\]
 io_oeb\[15\]
+analog_io\[9\]
 io_in\[16\]
 io_out\[16\]
 io_oeb\[16\]
+analog_io\[10\]
 io_in\[17\]
 io_out\[17\]
 io_oeb\[17\]
+analog_io\[11\]
 io_in\[18\]
 io_out\[18\]
 io_oeb\[18\]
+analog_io\[12\]
 io_in\[19\]
 io_out\[19\]
 io_oeb\[19\]
+analog_io\[13\]
 io_in\[20\]
 io_out\[20\]
 io_oeb\[20\]
+analog_io\[14\]
 io_in\[21\]
 io_out\[21\]
 io_oeb\[21\]
+analog_io\[15\]
 io_in\[22\]
 io_out\[22\]
 io_oeb\[22\]
+analog_io\[16\]
 io_in\[23\]
 io_out\[23\]
 io_oeb\[23\]
 
 #S
-
 wb_.*
-wbd_.*
+wbs_.*
 la_.*
 user_clock2
 user_irq.*
@@ -58,65 +66,85 @@
 io_in\[6\]
 io_out\[6\]
 io_oeb\[6\]
+analog_io\[0\]
 io_in\[7\]
 io_out\[7\]
 io_oeb\[7\]
+analog_io\[1\]
 io_in\[8\]
 io_out\[8\]
 io_oeb\[8\]
+analog_io\[2\]
 io_in\[9\]
 io_out\[9\]
 io_oeb\[9\]
+analog_io\[3\]
 io_in\[10\]
 io_out\[10\]
 io_oeb\[10\]
+analog_io\[4\]
 io_in\[11\]
 io_out\[11\]
 io_oeb\[11\]
+analog_io\[5\]
 io_in\[12\]
 io_out\[12\]
 io_oeb\[12\]
+analog_io\[6\]
 io_in\[13\]
 io_out\[13\]
 io_oeb\[13\]
+analog_io\[7\]
 io_in\[14\]
 io_out\[14\]
 io_oeb\[14\]
 
 #WR
+analog_io\[17\]
 io_in\[24\]
 io_out\[24\]
 io_oeb\[24\]
+analog_io\[18\]
 io_in\[25\]
 io_out\[25\]
 io_oeb\[25\]
+analog_io\[19\]
 io_in\[26\]
 io_out\[26\]
 io_oeb\[26\]
+analog_io\[20\]
 io_in\[27\]
 io_out\[27\]
 io_oeb\[27\]
+analog_io\[21\]
 io_in\[28\]
 io_out\[28\]
 io_oeb\[28\]
+analog_io\[22\]
 io_in\[29\]
 io_out\[29\]
 io_oeb\[29\]
+analog_io\[23\]
 io_in\[30\]
 io_out\[30\]
 io_oeb\[30\]
+analog_io\[24\]
 io_in\[31\]
 io_out\[31\]
 io_oeb\[31\]
+analog_io\[25\]
 io_in\[32\]
 io_out\[32\]
 io_oeb\[32\]
+analog_io\[26\]
 io_in\[33\]
 io_out\[33\]
 io_oeb\[33\]
+analog_io\[27\]
 io_in\[34\]
 io_out\[34\]
 io_oeb\[34\]
+analog_io\[28\]
 io_in\[35\]
 io_out\[35\]
 io_oeb\[35\]
diff --git a/signoff/clk_skew_adjust/final_summary_report.csv b/signoff/clk_skew_adjust/final_summary_report.csv
index 61ff946..713cb84 100644
--- a/signoff/clk_skew_adjust/final_summary_report.csv
+++ b/signoff/clk_skew_adjust/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/clk_skew_adjust,clk_skew_adjust,clk_skew_adjust,Flow_completed,0h1m6s,0h0m30s,64878.892733564026,0.0011560000000000001,25951.55709342561,51,384.71,30,0,0,0,0,0,0,0,0,0,0,0,677,212,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0.0,12.65,11.49,0.0,-1,-1,32,35,32,35,0,0,0,30,0,0,0,0,0,0,0,0,-1,-1,-1,16,5,0,21,90.9090909090909,11,10,AREA 0,5,40,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,0,3
+0,/project/openlane/clk_skew_adjust,clk_skew_adjust,clk_skew_adjust,Flow_completed,0h1m8s,0h0m32s,46875.0,0.0016,18750.0,48,385.05,30,0,0,0,0,0,0,0,0,0,0,0,980,208,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0.0,16.57,18.31,0.0,-1,-1,32,35,32,35,0,0,0,30,0,0,0,0,0,0,0,0,-1,-1,-1,20,6,0,26,90.9090909090909,11,10,AREA 0,5,40,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
index 390656f..7d8ac3a 100644
--- a/signoff/sdram/final_summary_report.csv
+++ b/signoff/sdram/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h8m28s,0h4m15s,40668.57142857143,0.35,20334.285714285714,27,639.29,7117,0,0,0,0,0,0,0,15,0,-1,0,302912,50760,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,239724191,0.0,20.25,16.33,1.79,-1,-1,7052,7280,1239,1467,0,0,0,7117,197,107,81,102,354,212,31,2263,1256,1154,27,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h9m25s,0h5m13s,41131.42857142857,0.35,20565.714285714286,27,654.48,7198,0,0,0,0,0,0,0,14,0,-1,0,307108,51429,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,245789185,0.0,20.86,16.44,1.36,-1,-1,7102,7361,1246,1505,0,0,0,7198,197,107,83,94,354,211,32,2289,1267,1186,27,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
index 7ecde4c..c34974f 100644
--- a/signoff/spi_master/final_summary_report.csv
+++ b/signoff/spi_master/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h6m38s,0h3m39s,45283.33333333334,0.24,22641.66666666667,33,605.61,5434,0,0,0,0,0,0,0,1,5,-1,0,248271,41053,-0.54,-0.54,-0.42,-0.42,-0.39,-0.98,-0.98,-0.94,-0.94,-0.89,196972893,0.0,18.06,28.16,0.23,-1,-1,5370,5512,872,1014,0,0,0,5434,217,0,185,97,764,130,35,1615,982,919,24,424,2889,0,3313,96.24639076034649,10.39,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h8m14s,0h4m36s,45758.33333333334,0.24,22879.16666666667,33,610.27,5491,0,0,0,0,0,0,0,0,4,-1,0,245032,41843,-0.01,-0.01,0.0,0.0,0.0,-0.01,-0.01,0.0,0.0,0.0,192057060,0.0,17.63,27.97,0.04,-1,-1,5427,5569,901,1043,0,0,0,5491,223,0,184,93,748,126,37,1613,982,921,24,424,2889,0,3313,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index 2fc1d06..a01c86f 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h50m19s,0h27m57s,34420.0,1.8,17210.0,22,1198.49,30978,0,0,0,0,0,0,0,56,2,-1,0,1529372,247821,-0.3,-0.3,-0.44,-0.44,-0.49,-12.11,-12.11,-25.78,-25.78,-26.46,1263825045,0.0,18.47,15.11,4.15,0.29,-1,30864,31102,2807,3045,0,0,0,30978,631,0,685,2044,4015,2105,1318,7432,2838,2786,94,866,22836,0,23702,95.32888465204957,10.49,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h51m11s,0h28m28s,34498.88888888888,1.8,17249.44444444444,23,1210.03,31049,0,0,0,0,0,0,0,76,9,-1,0,1617218,250691,-4.42,-4.42,-4.38,-4.38,-4.45,-34.56,-34.56,-34.86,-34.86,-35.41,1349556396,0.0,18.48,16.7,4.85,0.56,-1,30872,31173,2777,3078,0,0,0,31049,637,0,695,2031,3988,2108,1314,7432,2838,2808,95,866,22836,0,23702,69.20415224913495,14.45,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/uart/final_summary_report.csv b/signoff/uart/final_summary_report.csv
index e9d8ff5..63ea5b4 100644
--- a/signoff/uart/final_summary_report.csv
+++ b/signoff/uart/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart,uart_core,uart,Flow_completed,0h5m4s,0h3m18s,46133.33333333334,0.12,23066.66666666667,35,545.71,2768,0,0,0,0,0,0,0,1,0,-1,0,91647,20662,-0.67,-0.67,-0.47,-0.47,-0.73,-37.32,-37.32,-45.39,-45.39,-68.63,62910936,0.0,19.11,18.79,0.06,-1,-1,2767,2787,454,474,0,0,0,2768,59,0,30,41,182,125,26,685,435,396,17,278,1410,0,1688,93.19664492078284,10.73,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/uart,uart_core,uart,Flow_completed,0h4m21s,0h2m40s,46166.66666666667,0.12,23083.333333333336,35,540.52,2770,0,0,0,0,0,0,0,0,0,-1,0,91807,20722,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,62462955,0.0,19.42,18.96,0.0,-1,-1,2769,2789,456,476,0,0,0,2770,56,0,29,41,182,125,26,685,435,396,18,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index a4e190b..4ddaa70 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h42m41s,0h5m47s,3.3079078455790785,10.2784,1.6539539227895392,0,580.84,17,0,0,0,0,0,0,0,0,30,-1,-1,1296299,5489,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,2.61,3.74,0.82,1.49,-1,884,1502,853,1471,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h41m45s,0h5m8s,3.3079078455790785,10.2784,1.6539539227895392,0,569.2,17,0,0,0,0,0,0,0,0,30,-1,-1,1188996,4053,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.29,4.08,0.96,2.29,-1,852,1470,852,1470,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index be336b3..d6c67a7 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h7m6s,0h4m32s,30340.0,0.2,15170.0,25,618.03,3034,0,0,0,0,0,0,0,3,0,-1,0,323344,30030,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,276033708,0.0,49.92,13.67,23.25,-1,-1,2756,3398,457,1099,0,0,0,3034,78,0,3,11,37,27,10,770,589,744,14,130,2343,0,2473,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h5m32s,0h3m51s,72650.0,0.08,36325.0,58,563.27,2906,0,0,0,0,0,0,0,3,0,-1,0,155769,24752,-2.71,-2.71,-2.68,-2.68,-2.73,-85.53,-85.53,-84.64,-84.64,-87.05,121784250,0.0,55.83,29.09,15.64,-1,-1,2753,3014,454,715,0,0,0,2906,77,0,2,14,32,25,10,769,589,744,14,130,905,0,1035,78.55459544383346,12.73,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index 751e1e1..61ca705 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h10m43s,0h6m55s,5877.272727272727,0.44,2938.6363636363635,5,580.27,1293,0,0,0,0,0,0,0,2,0,-1,0,496849,21106,0.0,0.0,0.0,0.0,-0.83,0.0,0.0,0.0,0.0,-79.64,424741802,0.0,31.77,8.67,21.85,-1,-1,1043,1616,204,777,0,0,0,1293,244,0,75,15,111,0,0,180,431,418,11,130,5189,0,5319,92.33610341643582,10.83,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h8m41s,0h4m48s,5868.181818181818,0.44,2934.090909090909,5,582.16,1291,0,0,0,0,0,0,0,1,0,-1,0,483038,20167,0.0,0.0,0.0,0.0,-1.08,0.0,0.0,0.0,0.0,-86.31,415470896,0.0,32.3,8.43,19.36,-1,-1,1041,1614,204,777,0,0,0,1291,244,0,75,15,111,0,0,180,431,414,11,130,5189,0,5319,90.25270758122744,11.08,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 457dcf7..26eeaf8 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -380,6 +380,68 @@
 	);
 
 
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+	force uut.mprj.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio0.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay1_sdio0.VNB  = VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio0.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio0.VNB  = VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio0.VPWR    =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio0.VPB     =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio0.VGND    =VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio0.VNB     =VSS;
+
+
+	force uut.mprj.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio1.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay1_sdio1.VNB = VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio1.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio1.VNB = VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio1.VPWR    =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio1.VPB     =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio1.VGND    =VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio1.VNB     =VSS;
+
+	force uut.mprj.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio2.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay1_sdio2.VNB = VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio2.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio2.VNB = VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio2.VPWR    =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio2.VPB     =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio2.VGND    =VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio2.VNB     =VSS;
+
+	force uut.mprj.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio3.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay1_sdio3.VNB = VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio3.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio3.VNB = VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio3.VPWR    =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio3.VPB     =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio3.VGND    =VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio3.VNB     =VSS;
+          
+	force uut.mprj.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force uut.mprj.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force uut.mprj.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force uut.mprj.u_uart_core.u_lineclk_buf.VNB = VSS;
+    end
+`endif    
 
 
 /**
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 348ecd0..bb63a42 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -252,6 +252,68 @@
 
 );
 
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+	force u_top.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio0.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio0.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio0.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio0.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio0.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio0.VNB    =VSS;
+
+	force u_top.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio1.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio1.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio1.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio1.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio1.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio1.VNB    =VSS;
+
+	force u_top.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio2.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio2.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio2.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio2.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio2.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio2.VNB    =VSS;
+
+	force u_top.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio3.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio3.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio3.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio3.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
+          
+	force u_top.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force u_top.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force u_top.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force u_top.u_uart_core.u_lineclk_buf.VNB = VSS;
+    end
+`endif    
+
 //------------------------------------------------------
 //  Integrate the Serial flash with qurd support to
 //  user core using the gpio pads
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index de9fe38..0489af7 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -386,6 +386,68 @@
 
 );
 
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+	force u_top.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio0.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio0.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio0.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio0.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio0.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio0.VNB    =VSS;
+
+	force u_top.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio1.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio1.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio1.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio1.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio1.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio1.VNB    =VSS;
+
+	force u_top.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio2.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio2.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio2.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio2.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio2.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio2.VNB    =VSS;
+
+	force u_top.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio3.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio3.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio3.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio3.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
+          
+	force u_top.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force u_top.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force u_top.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force u_top.u_uart_core.u_lineclk_buf.VNB = VSS;
+    end
+`endif    
+
 //------------------------------------------------------
 //  Integrate the Serial flash with qurd support to
 //  user core using the gpio pads
diff --git a/verilog/dv/user_uart/uprj_netlists.v b/verilog/dv/user_uart/uprj_netlists.v
index ae6502e..e8f024b 100644
--- a/verilog/dv/user_uart/uprj_netlists.v
+++ b/verilog/dv/user_uart/uprj_netlists.v
@@ -15,11 +15,10 @@
 
 // Include caravel global defines for the number of the user project IO pads 
 `include "defines.v"
-`define USE_POWER_PINS
-`define UNIT_DELAY #0.1
+       `define USE_POWER_PINS
+       `define UNIT_DELAY #0.1
 
 `ifdef GL
-
        `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
        `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
        `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
@@ -37,7 +36,6 @@
 	`include "clk_skew_adjust.v"
 
 `else
-
      `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
      `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
      `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 4852c4b..9f3e22c 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -149,7 +149,7 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("risc_boot.vcd");
-	   	$dumpvars(2, user_uart_tb);
+	   	$dumpvars(3, user_uart_tb);
 	   end
        `endif
 
@@ -291,6 +291,67 @@
 
 );
 
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+	force u_top.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio0.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio0.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio0.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio0.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio0.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio0.VNB    =VSS;
+
+	force u_top.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio1.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio1.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio1.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio1.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio1.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio1.VNB    =VSS;
+
+	force u_top.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio2.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio2.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio2.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio2.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio2.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio2.VNB    =VSS;
+
+	force u_top.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay1_sdio3.VGND =VSS;
+	force u_top.u_spi_master.u_delay1_sdio3.VNB = VSS;
+	force u_top.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_spi_master.u_delay2_sdio3.VGND =VSS;
+	force u_top.u_spi_master.u_delay2_sdio3.VNB = VSS;
+	force u_top.u_spi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
+	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
+	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
+          
+	force u_top.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force u_top.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force u_top.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force u_top.u_uart_core.u_lineclk_buf.VNB = VSS;
+    end
+`endif    
 //------------------------------------------------------
 //  Integrate the Serial flash with qurd support to
 //  user core using the gpio pads
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index 19c32ee..d156539 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -25,6 +25,7 @@
 ## User Project Pointers
 UPRJ_VERILOG_PATH ?= ../../../verilog
 UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
 UPRJ_BEHAVIOURAL_MODELS = ../
 UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
 UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
@@ -55,9 +56,9 @@
 	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
 	$< -o $@ 
 else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_GL_PATH)  -I$(UPRJ_RTL_PATH)  -I $(UPRJ_VERILOG_PATH) \
 	$< -o $@ 
 endif
 
diff --git a/verilog/dv/wb_port/run_verilog b/verilog/dv/wb_port/run_verilog
new file mode 100644
index 0000000..c28480e
--- /dev/null
+++ b/verilog/dv/wb_port/run_verilog
@@ -0,0 +1,2 @@
+#iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I /home/dinesha/workarea/pdk/sky130A -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog -I ../ -I../../../verilog/rtl -I../../../verilog/gl  -I ../../../verilog wb_port_tb.v -o wb_port.vvp
+iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -DGL -I /home/dinesha/workarea/pdk/sky130A -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog -I ../ -I../../../verilog/rtl -I../../../verilog/gl  -I ../../../verilog wb_port_tb.v -o wb_port.vvp
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 684f275..9292946 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -123,18 +123,27 @@
 
 
     if (reg_mprj_globl_reg6  != 0x11223344) bFail = 1;
+    if (bFail == 1) reg_mprj_datal = 0xAB610000;
     if (reg_mprj_globl_reg7  != 0x22334455) bFail = 1;
+    if (bFail == 1) reg_mprj_datal = 0xAB620000;
     if (reg_mprj_globl_reg8  != 0x33445566) bFail = 1;
+    if (bFail == 1) reg_mprj_datal = 0xAB630000;
     if (reg_mprj_globl_reg9  != 0x44556677) bFail = 1;
+    if (bFail == 1) reg_mprj_datal = 0xAB640000;
     if (reg_mprj_globl_reg10 != 0x55667788) bFail = 1;
+    if (bFail == 1) reg_mprj_datal = 0xAB650000;
     if (reg_mprj_globl_reg11 != 0x66778899) bFail = 1;
+    if (bFail == 1) reg_mprj_datal = 0xAB660000;
     if (reg_mprj_globl_reg12 != 0x778899AA) bFail = 1;
+    if (bFail == 1) reg_mprj_datal = 0xAB670000;
     if (reg_mprj_globl_reg13 != 0x8899AABB) bFail = 1;
+    if (bFail == 1) reg_mprj_datal = 0xAB680000;
     if (reg_mprj_globl_reg14 != 0x99AABBCC) bFail = 1;
+    if (bFail == 1) reg_mprj_datal = 0xAB690000;
     if (reg_mprj_globl_reg15 != 0xAABBCCDD) bFail = 1;
 
     if(bFail == 0) {
-        reg_mprj_datal = 0xAB610000;
+        reg_mprj_datal = 0xAB6A0000;
     } else {
         reg_mprj_datal = 0xAB600000;
     }
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index 2455069..1ea0baa 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -50,7 +50,10 @@
 	`ifdef WFDUMP
 	initial begin
 		$dumpfile("wb_port.vcd");
-		$dumpvars(0, wb_port_tb.uut.mprj);
+		$dumpvars(1, wb_port_tb);
+		$dumpvars(2, wb_port_tb.uut);
+		//$dumpvars(1, wb_port_tb.uut.mprj);
+		$dumpvars(1, wb_port_tb.uut.mprj.u_wb_host);
 	end
        `endif
 
@@ -76,7 +79,7 @@
 	initial begin
 	   wait(checkbits == 16'h AB60);
 		$display("Monitor: MPRJ-Logic WB Started");
-		wait(checkbits == 16'h AB61);
+		wait(checkbits == 16'h AB6A);
 		$display ("##########################################################");
 		`ifdef GL
 	    	$display("Monitor: Mega-Project WB (GL) Passed");
@@ -162,5 +165,67 @@
 		.io3()			// not used
 	);
 
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+	force uut.mprj.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio0.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay1_sdio0.VNB  = VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio0.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio0.VNB  = VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio0.VPWR    =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio0.VPB     =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio0.VGND    =VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio0.VNB     =VSS;
+
+
+	force uut.mprj.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio1.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay1_sdio1.VNB = VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio1.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio1.VNB = VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio1.VPWR    =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio1.VPB     =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio1.VGND    =VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio1.VNB     =VSS;
+
+	force uut.mprj.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio2.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay1_sdio2.VNB = VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio2.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio2.VNB = VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio2.VPWR    =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio2.VPB     =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio2.VGND    =VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio2.VNB     =VSS;
+
+	force uut.mprj.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay1_sdio3.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay1_sdio3.VNB = VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_delay2_sdio3.VGND =VSS;
+	force uut.mprj.u_spi_master.u_delay2_sdio3.VNB = VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio3.VPWR    =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio3.VPB     =USER_VDD1V8;
+	force uut.mprj.u_spi_master.u_buf_sdio3.VGND    =VSS;
+	force uut.mprj.u_spi_master.u_buf_sdio3.VNB     =VSS;
+          
+	force uut.mprj.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force uut.mprj.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force uut.mprj.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force uut.mprj.u_uart_core.u_lineclk_buf.VNB = VSS;
+    end
+`endif    
 endmodule
 `default_nettype wire
diff --git a/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv b/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv
index 038ef52..b826235 100644
--- a/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv
+++ b/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv
@@ -129,21 +129,21 @@
   wire d30;
 
 
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_1  (.A(clk_in),  .X(clk_d1));
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_2  (.A(clk_d1),    .X(clk_d2));
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_3  (.A(clk_d2),    .X(clk_d3));
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_4  (.A(clk_d3),    .X(clk_d4));
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_5  (.A(clk_d4),    .X(clk_d5));
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_6  (.A(clk_d5),    .X(clk_d6));
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_7  (.A(clk_d6),    .X(clk_d7));
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_8  (.A(clk_d7),    .X(clk_d8));
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_9  (.A(clk_d8),    .X(clk_d9));
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_10 (.A(clk_d9),    .X(clk_d10));
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_11 (.A(clk_d10),   .X(clk_d11));
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_12 (.A(clk_d11),   .X(clk_d12));
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_13 (.A(clk_d12),   .X(clk_d13));
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_14 (.A(clk_d13),   .X(clk_d14));
-  sky130_fd_sc_hd__clkbuf_1 clkbuf_15 (.A(clk_d14),   .X(clk_d15));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_1  (.A(clk_in),  .X(clk_d1));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_2  (.A(clk_d1),    .X(clk_d2));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_3  (.A(clk_d2),    .X(clk_d3));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_4  (.A(clk_d3),    .X(clk_d4));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_5  (.A(clk_d4),    .X(clk_d5));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_6  (.A(clk_d5),    .X(clk_d6));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_7  (.A(clk_d6),    .X(clk_d7));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_8  (.A(clk_d7),    .X(clk_d8));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_9  (.A(clk_d8),    .X(clk_d9));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_10 (.A(clk_d9),    .X(clk_d10));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_11 (.A(clk_d10),   .X(clk_d11));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_12 (.A(clk_d11),   .X(clk_d12));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_13 (.A(clk_d12),   .X(clk_d13));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_14 (.A(clk_d13),   .X(clk_d14));
+  sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_15 (.A(clk_d14),   .X(clk_d15));
 
 
   // Tap point selection
@@ -186,7 +186,7 @@
   sky130_fd_sc_hd__mux2_1 u_mux_level_21 ( .X (d21) , .A0 (d12), .A1(d13), .S(sel[2]));
 
   // fourth level mux - 1
-  sky130_fd_sc_hd__mux2_1 u_mux_level_30 ( .X (d30) , .A0 (d20), .A1(d21), .S(sel[3]));
+  sky130_fd_sc_hd__mux2_4 u_mux_level_30 ( .X (d30) , .A0 (d20), .A1(d21), .S(sel[3]));
 
 
   assign clk_out = d30;
diff --git a/verilog/rtl/digital_core/src/digital_core.sv b/verilog/rtl/digital_core/src/digital_core.sv
index 4b8a056..2eb4b27 100644
--- a/verilog/rtl/digital_core/src/digital_core.sv
+++ b/verilog/rtl/digital_core/src/digital_core.sv
@@ -83,6 +83,11 @@
 ////          m0 - External HOST                                  ////
 ////          m1 - RISC IMEM                                      ////
 ////          m2 - RISC DMEM                                      ////
+////    0.8 - 6th July 2021, Dinesh A                             ////
+////          For Better SDRAM Interface timing we have taping    ////
+////          sdram_clock goint to io_out[29] directly from       ////
+////          global register block, this help in better SDRAM    ////
+////          interface timing control                            ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -136,6 +141,11 @@
     output  wire [WB_WIDTH-1:0]        wbs_dat_o       ,  // data input
     output  wire                       wbs_ack_o       ,  // acknowlegement
 
+    // Analog (direct connection to GPIO pad---use with caution)
+    // Note that analog I/O is not available on the 7 lowest-numbered
+    // GPIO pads, and so the analog_io indexing is offset from the
+    // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+    inout [`MPRJ_IO_PADS-10:0] analog_io,
  
     // Logic Analyzer Signals
     input  wire [127:0]                la_data_in      ,
@@ -775,7 +785,7 @@
                .vccd1      (vccd1                      ),// User area 1 1.8V supply
                .vssd1      (vssd1                      ),// User area 1 digital ground
 `endif
-	       .clk_in     (io_in[29]                 ), 
+	       .clk_in     (sdram_clk                 ), 
 	       .sel        (cfg_cska_sd_ci            ), 
 	       .clk_out    (io_in_29_                 ) 
        );
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v
index bf1cd8b..6c06615 100755
--- a/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v
+++ b/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v
@@ -100,6 +100,7 @@
 		reset_n,
                 sdr_width,
 		cfg_colbits,
+                debug,
 
 		/* Request from app */
 		app_req,	        // Transfer Request
@@ -163,7 +164,7 @@
 input                   reset_n             ; // Reset Signal
 input [1:0]             sdr_width           ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
 input [1:0]             cfg_colbits         ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
-
+output [21:0]           debug               ;
 
 //------------------------------------------------
 // Request from app
@@ -294,6 +295,10 @@
 assign sdr_dout  = sdr_dout_int ;
 
 
+assign debug  = {r2x_idle,r2b_req,r2b_start,r2b_last,b2r_ack,b2r_arb_ok,r2b_write,
+                 b2x_idle,b2x_req,b2x_start,b2x_wrap,x2b_ack,b2x_tras_ok,x2b_refresh,x2b_pre_ok,x2b_act_ok,
+	         x2b_rdok,x2b_wrok,x2a_rdstart,x2a_wrstart,x2a_rdlast,x2a_wrlast};
+
 // To meet the timing at read path, read data is registered w.r.t pad_sdram_clock and register back to sdram_clk
 // assumption, pad_sdram_clk is synhronous and delayed clock of sdram_clk.
 // register w.r.t pad sdram clk
diff --git a/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v b/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
index 6aba2a6..c845d02 100755
--- a/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
+++ b/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
@@ -57,6 +57,8 @@
 	          Unused port wb_cti_i removed
              0.5 - 29th June 2021
 	          Wishbone Stagging FF added to break timing path
+             0.6 - 6th July 2021, Dinesh A
+	          32 bit debug port added
 
                                                              
  Copyright (C) 2000 Authors and OPENCORES.ORG                
@@ -90,6 +92,8 @@
            (
                     cfg_sdr_width       ,
                     cfg_colbits         ,
+
+		    sdram_debug         ,
                     
                 // WB bus
                     wb_rst_n            ,
@@ -149,6 +153,7 @@
 input [1:0]             cfg_sdr_width      ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
 input [1:0]             cfg_colbits        ; // 2'b00 - 8 Bit column address, 
                                              // 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
+output [31:0]           sdram_debug        ; // SDRAM debug signals
 
 //--------------------------------------
 // Wish Bone Interface
@@ -265,6 +270,11 @@
 // sdram pad clock is routed back through pad
 // SDRAM Clock from Pad, used for registering Read Data
 //wire #(1.0) sdram_pad_clk = sdram_clk;
+//
+wire [21:0] core_debug;
+assign sdram_debug = {sdr_init_done,wb_stag_stb_i,wb_stag_we_i,wb_stag_ack_o, 
+                      app_req,app_req_wr_n,app_req_ack,app_busy_n,app_wr_next_req, app_rd_valid,	      
+		      core_debug[21:0]};
 
 /************** Ends Here **************************/
 
@@ -340,6 +350,7 @@
           .reset_n            (sdram_resetn       ) ,
           .sdr_width          (cfg_sdr_width      ) ,
           .cfg_colbits        (cfg_colbits        ) ,
+	  .debug              (core_debug         ) ,
 
  		/* Request from app */
           .app_req            (app_req            ) ,// Transfer Request
diff --git a/verilog/rtl/spi_master/src/spim_top.sv b/verilog/rtl/spi_master/src/spim_top.sv
index fbb25b8..1d153b5 100644
--- a/verilog/rtl/spi_master/src/spim_top.sv
+++ b/verilog/rtl/spi_master/src/spim_top.sv
@@ -51,6 +51,9 @@
 ////     V.1  - June 25, 2021                                     ////
 ////            Pad logic is brought inside the block to avoid    ////
 ////            logic at digital core level for caravel project   ////
+////     V.2  - July 6, 2021                                      ////
+////            Added Hold fix cell for SPI data out signal to    ////
+////            met interface hold                                ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -182,7 +185,7 @@
     logic [3:0]   ctrl_state        ;
 
 
-    assign spi_debug  =   {3'h0,
+    assign spi_debug  =   {m0_res_fifo_flush,m1_res_fifo_flush,spi_init_done,
 		          m0_cmd_fifo_full,m0_cmd_fifo_empty,m0_res_fifo_full,m0_res_fifo_empty,
 		          m1_cmd_fifo_full,m1_cmd_fifo_empty,m1_res_fifo_full,m1_res_fifo_empty,
 		          ctrl_state[3:0], m0_state[3:0],m1_state[3:0],spi_ctrl_status};
@@ -207,6 +210,15 @@
 logic                          spi_sdi3;
 logic                          spi_en_tx;
 logic                          spi_init_done;
+logic                          spi_sdo0_out;
+logic                          spi_sdo1_out;
+logic                          spi_sdo2_out;
+logic                          spi_sdo3_out;
+
+logic                          spi_sdo0_dl;
+logic                          spi_sdo1_dl;
+logic                          spi_sdo2_dl;
+logic                          spi_sdo3_dl;
 
 
 assign  spi_sdi0  =  io_in[2];
@@ -215,12 +227,30 @@
 assign  spi_sdi3  =  io_in[5];
 
 assign  io_out[0] =  spi_clk;
-assign  io_out[1] =  spi_csn0;
-assign  io_out[2] =  spi_sdo0;
-assign  io_out[3] =  spi_sdo1;
-assign  io_out[4] =  spi_sdo2;
-assign  io_out[5] =  spi_sdo3;
-   
+assign  io_out[1] =  spi_csn0;// No hold fix for CS#, as it asserted much eariler than SPI clock
+assign  io_out[2] =  spi_sdo0_out;
+assign  io_out[3] =  spi_sdo1_out;
+assign  io_out[4] =  spi_sdo2_out;
+assign  io_out[5] =  spi_sdo3_out;
+
+// ADDing Delay cells for Interface hold fix
+sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio0 (.X(spi_sdo0_d1),.A(spi_sdo0));
+sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio0 (.X(spi_sdo0_d2),.A(spi_sdo0_d1));
+sky130_fd_sc_hd__clkbuf_16 u_buf_sdio0    (.X(spi_sdo0_out),.A(spi_sdo0_d2));
+
+sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio1 (.X(spi_sdo1_d1),.A(spi_sdo1));
+sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio1 (.X(spi_sdo1_d2),.A(spi_sdo1_d1));
+sky130_fd_sc_hd__clkbuf_16 u_buf_sdio1    (.X(spi_sdo1_out),.A(spi_sdo1_d2));
+
+sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio2 (.X(spi_sdo2_d1),.A(spi_sdo2));
+sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio2 (.X(spi_sdo2_d2),.A(spi_sdo2_d1));
+sky130_fd_sc_hd__clkbuf_16 u_buf_sdio2    (.X(spi_sdo2_out),.A(spi_sdo2_d2));
+
+sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio3 (.X(spi_sdo3_d1),.A(spi_sdo3));
+sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio3 (.X(spi_sdo3_d2),.A(spi_sdo3_d1));
+sky130_fd_sc_hd__clkbuf_16 u_buf_sdio3    (.X(spi_sdo3_out),.A(spi_sdo3_d2));
+
+
 assign  io_oeb[0] =  1'b0;         // spi_clk
 assign  io_oeb[1] =  1'b0;         // spi_csn
 assign  io_oeb[2] =  !spi_en_tx;   // spi_dio0
diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
index 3779eb5..634069e 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
@@ -47,6 +47,7 @@
 module scr1_pipe_top (
     // Common
     input   logic                                       pipe_rst_n,                 // Pipe reset
+    output  logic [48:0]                                pipe_debug,
 `ifdef SCR1_DBG_EN
     input   logic                                       pipe2hdu_rdc_qlfy_i,        // Pipe RDC qualifier
     input   logic                                       dbg_rst_n,                  // Debug reset
@@ -289,6 +290,10 @@
 logic                                       pipe2clkctl_wake_req_o;
 `endif // SCR1_CLKCTRL_EN
 
+
+assign pipe_debug = {curr_pc[31:0],new_pc_req,stop_fetch, exu_exc_req,brkpt,exu_init_pc,wfi_run2halt,instret,
+	             ifu2idu_vd,idu2ifu_rdy,idu2exu_req,exu2idu_rdy,exu2mprf_w_req,exu2csr_r_req,csr2exu_rw_exc,
+	             exu2csr_mret_update,csr2exu_irq,csr2exu_mstatus_mie_up};
 //-------------------------------------------------------------------------------
 // Pipeline logic
 //-------------------------------------------------------------------------------
diff --git a/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv b/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv
index 6df5558..92bbb10 100644
--- a/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv
@@ -43,6 +43,7 @@
     input   logic                                   clk,                        // Core clock
     output  logic                                   core_rst_n_o,               // Core reset
     output  logic                                   core_rdc_qlfy_o,            // Core RDC qualifier
+    output  logic   [48:0]                          core_debug  ,
 `ifdef SCR1_DBG_EN
     output  logic                                   sys_rst_n_o,                // System reset
     output  logic                                   sys_rdc_qlfy_o,             // System RDC qualifier
@@ -290,6 +291,7 @@
 scr1_pipe_top i_pipe_top (
     // Control
     .pipe_rst_n                     (core_rst_n             ),
+    .pipe_debug                     (core_debug             ),
 `ifdef SCR1_DBG_EN
     .pipe2hdu_rdc_qlfy_i            (core2hdu_rdc_qlfy      ),
     .dbg_rst_n                      (hdu_rst_n              ),
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
index ccb49e8..bf6affc 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
@@ -38,6 +38,8 @@
 ////     v1:    June 17, 2021, Dinesh A                           ////
 ////             core and wishbone clock domain are seperated     ////
 ////             Async fifo added in imem and dmem path           ////
+////     v2:    July 7, 2021, Dinesh A                            ////
+////            64bit debug signal added                          ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -92,6 +94,7 @@
     // input   logic                                   test_rst_n,             // Test mode's reset - unused
     input   logic                                   core_clk,               // Core clock
     input   logic                                   rtc_clk,                // Real-time clock
+    output  logic [63:0]                            riscv_debug,
 `ifdef SCR1_DBG_EN
     output  logic                                   sys_rst_n_o,            // External System Reset output
                                                                             //   (for the processor cluster's components or
@@ -242,6 +245,11 @@
 // --------------------------------------------------------------------------------
 assign test_mode = 1'b0;
 assign test_rst_n = 1'b0;
+
+logic [48:0] core_debug;
+assign riscv_debug = {core_imem_req,core_imem_req,core_imem_cmd,core_imem_resp[1:0],
+	              core_dmem_req_ack,core_dmem_req,core_dmem_cmd,core_dmem_resp[1:0],
+		      wb_imem_req,wb_imem_req,wb_imem_cmd,wb_imem_resp[1:0], core_debug };
 //-------------------------------------------------------------------------------
 // Reset logic
 //-------------------------------------------------------------------------------
@@ -304,6 +312,7 @@
     .clk                        (core_clk         ),
     .core_rst_n_o               (core_rst_n_local ),
     .core_rdc_qlfy_o            (                 ),
+    .core_debug                 (core_debug       ),
 `ifdef SCR1_DBG_EN
     .sys_rst_n_o                (sys_rst_n_o      ),
     .sys_rdc_qlfy_o             (sys_rdc_qlfy_o   ),
diff --git a/verilog/rtl/uart/src/uart_core.sv b/verilog/rtl/uart/src/uart_core.sv
index 1141b3d..79c0b47 100644
--- a/verilog/rtl/uart/src/uart_core.sv
+++ b/verilog/rtl/uart/src/uart_core.sv
@@ -205,11 +205,13 @@
 //    cfg_baud_16x = 0xA0 (160)
 //###############################################################
 
-wire line_clk_16x;
+wire line_clk_16x_in;
+
+sky130_fd_sc_hd__clkbuf_16 u_lineclk_buf  (.A(line_clk_16x_in),  .X(line_clk_16x));
 
 clk_ctl #(11) u_clk_ctl (
    // Outputs
-       .clk_o          (line_clk_16x),
+       .clk_o          (line_clk_16x_in),
 
    // Inputs
        .mclk           (app_clk),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 1b2d6b2..65f936c 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -83,6 +83,11 @@
 ////          m0 - External HOST                                  ////
 ////          m1 - RISC IMEM                                      ////
 ////          m2 - RISC DMEM                                      ////
+////    0.8 - 6th July 2021, Dinesh A                             ////
+////          For Better SDRAM Interface timing we have taping    ////
+////          sdram_clock goint to io_out[29] directly from       ////
+////          global register block, this help in better SDRAM    ////
+////          interface timing control                            ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -315,7 +320,9 @@
 wire [11: 0]                      cfg_sdr_rfsh        ;
 wire [2 : 0]                      cfg_sdr_rfmax       ;
 
-
+wire [31:0]                       spi_debug           ;
+wire [31:0]                       sdram_debug         ;
+wire [63:0]                       riscv_debug         ;
 
 
 
@@ -339,6 +346,9 @@
 assign cfg_cska_sd_ci = cfg_clk_ctrl2[7:4]; // SDRAM clock in control
 assign cfg_cska_sp_co = cfg_clk_ctrl2[11:8];// SPI clock out control
 
+//assign la_data_out    = {riscv_debug,spi_debug,sdram_debug};
+assign la_data_out[127:0]    = {sdram_debug,spi_debug,riscv_debug};
+
 
 wb_host u_wb_host(
 
@@ -370,12 +380,8 @@
 
        .cfg_glb_ctrl     (cfg_glb_ctrl         ),
        .cfg_clk_ctrl1    (cfg_clk_ctrl1        ),
-       .cfg_clk_ctrl2    (cfg_clk_ctrl2        ),
+       .cfg_clk_ctrl2    (cfg_clk_ctrl2        )
 
-    // Logic Analyzer Signals
-       .la_data_in       (la_data_in           ),
-       .la_data_out      (la_data_out          ),
-       .la_oenb          (la_oenb              )
     );
 
 
@@ -389,6 +395,7 @@
     .pwrup_rst_n            (wbd_int_rst_n             ),
     .rst_n                  (wbd_int_rst_n             ),
     .cpu_rst_n              (cpu_rst_n                 ),
+    .riscv_debug            (riscv_debug               ),
 
     // Clock
     .core_clk               (cpu_clk                   ),
@@ -476,6 +483,7 @@
      u_sdram_ctrl (
     .cfg_sdr_width          (cfg_sdr_width              ),
     .cfg_colbits            (cfg_colbits                ),
+    .sdram_debug            (sdram_debug                ),
                     
     // WB bus
     .wb_rst_n               (wbd_int_rst_n              ),
@@ -780,7 +788,7 @@
                .vccd1      (vccd1                      ),// User area 1 1.8V supply
                .vssd1      (vssd1                      ),// User area 1 digital ground
 `endif
-	       .clk_in     (io_in[29]                 ), 
+	       .clk_in     (sdram_clk                 ), 
 	       .sel        (cfg_cska_sd_ci            ), 
 	       .clk_out    (io_in_29_                 ) 
        );
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 8032f11..8f9a6dd 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -98,12 +98,8 @@
 
        output logic [7:0]          cfg_glb_ctrl     ,
        output logic [31:0]         cfg_clk_ctrl1    ,
-       output logic [31:0]         cfg_clk_ctrl2    ,
+       output logic [31:0]         cfg_clk_ctrl2    
 
-    // Logic Analyzer Signals
-       input  logic [127:0]        la_data_in       ,
-       output logic [127:0]        la_data_out      ,
-       input  logic [127:0]        la_oenb         
     );
 
 
@@ -138,6 +134,7 @@
 logic [2:0]         cfg_wb_clk_ctr;
 
 
+
 assign wbm_rst_n = !wbm_rst_i;
 assign wbs_rst_n = !wbm_rst_i;