diff --git a/verilog/dv/agents/uart_agent.v b/verilog/dv/agents/uart_agent.v
index c9f11b4..2b12d64 100644
--- a/verilog/dv/agents/uart_agent.v
+++ b/verilog/dv/agents/uart_agent.v
@@ -144,8 +144,8 @@
 reg	parity;
 
 begin
-	data <= 8'h0;
-	parity <= 1;
+	data = 8'h0;
+	parity = 1;
 	timeout_count = 0;
 
 fork	
@@ -162,15 +162,15 @@
 // start cycle
 	@(negedge rxd) 
 	 disable loop_1;
-	 read <= 1;
+	 read = 1;
 
 // data cycle
 	@(posedge uart_rx_clk);
 	 for (i = 0; i < data_bit_number; i = i + 1)
 	  begin
 	    @(posedge uart_rx_clk)
-	    data[i] <=  rxd;
-	    parity <= parity ^ rxd;
+	    data[i] =  rxd;
+	    parity = parity ^ rxd;
 	  end		
 
 // parity cycle
@@ -207,7 +207,7 @@
 		  end
 	end
 
-	read <= 0;
+	read = 0;
 	-> uart_read_done;
 
 	if (expected_data != data)
@@ -239,8 +239,8 @@
 reg	parity;
 
 begin
-	data <= 8'h0;
-	parity <= 1;
+	data = 8'h0;
+	parity = 1;
 	timeout_count = 0;
 	timeout = 0;
 
@@ -256,15 +256,15 @@
 
 // start cycle
 	@(negedge rxd) 
-	 read <= 1;
+	 read = 1;
 
 // data cycle
 	@(posedge uart_rx_clk );
 	 for (i = 0; i < data_bit_number; i = i + 1)
 	  begin
 	    @(posedge uart_rx_clk)
-	    data[i] <=  rxd;
-	    parity <= parity ^ rxd;
+	    data[i] =  rxd;
+	    parity = parity ^ rxd;
 	  end		
 
 // parity cycle
@@ -301,7 +301,7 @@
 		  end
 	end
 
-	read <= 0;
+	read = 0;
 	-> uart_read_done;
 
 //      $display ("(%m) Received Data  %c", data);
@@ -331,8 +331,8 @@
 reg	parity;
 
 begin
-	data <= 8'h0;
-	parity <= 1;
+	data = 8'h0;
+	parity = 1;
 	timeout_count = 0;
 	timeout = 0;
 
@@ -352,15 +352,15 @@
 // start cycle
 	@(negedge rxd) 
 	 disable loop_1;
-	 read <= 1;
+	 read = 1;
 
 // data cycle
 	@(posedge uart_rx_clk);
 	 for (i = 0; i < data_bit_number; i = i + 1)
 	  begin
 	    @(posedge uart_rx_clk)
-	    data[i] <=  rxd;
-	    parity <= parity ^ rxd;
+	    data[i] =  rxd;
+	    parity = parity ^ rxd;
 	  end		
 
 // parity cycle
@@ -397,7 +397,7 @@
 		  end
 	end
 
-	read <= 0;
+	read = 0;
 	-> uart_read_done;
 
 	rxd_data = data;
@@ -424,8 +424,8 @@
 reg	parity;
 
 begin
-	data <= 8'h0;
-	parity <= 1;
+	data = 8'h0;
+	parity = 1;
 
 
 fork	
@@ -433,15 +433,15 @@
 
 // start cycle
 	@(negedge rxd) 
-	 read <= 1;
+	 read = 1;
 
 // data cycle
 	@(posedge uart_rx_clk);
 	 for (i = 0; i < data_bit_number; i = i + 1)
 	  begin
 	    @(posedge uart_rx_clk)
-	    data[i] <=  rxd;
-	    parity <= parity ^ rxd;
+	    data[i] =  rxd;
+	    parity = parity ^ rxd;
 	  end		
 
 // parity cycle
@@ -478,7 +478,7 @@
 		  end
 	end
 
-	read <= 0;
+	read = 0;
 	-> uart_read_done;
 
 	rxd_data = data;
@@ -497,13 +497,13 @@
 reg parity;	// 0: odd parity, 1: even parity
 
 begin
-	parity <=  #1 1;
+	parity =  #1 1;
 
 // start cycle
 	@(posedge uart_clk)
 	 begin
-		txd <= #1 0;
-		write <= #1 1;
+		txd = #1 0;
+		write = #1 1;
 	 end
 
 // data cycle
@@ -511,8 +511,8 @@
 	   for (i = 0; i < data_bit_number; i = i + 1)
 	   begin
 		@(posedge uart_clk)
-		    txd <= #1 data[i];
-		parity <= parity ^ data[i];
+		    txd = #1 data[i];
+		parity = parity ^ data[i];
 	   end
 	end
 
@@ -520,24 +520,24 @@
 	if (control_setup.parity_en)
 	begin
 		@(posedge uart_clk)
-			txd <= #1 
+			txd = #1 
 //				control_setup.stick_parity ? ~control_setup.even_odd_parity : 
 				control_setup.even_odd_parity ? !parity : parity;
 	end
 
 // stop cycle 1
 	@(posedge uart_clk)
-		txd <= #1 stop_err_check ? 0 : 1;
+		txd = #1 stop_err_check ? 0 : 1;
 
 // stop cycle 2
 	@(posedge uart_clk);
-		txd <= #1 1;
+		txd = #1 1;
 	if (data_bit_number == 5)
 		@(negedge uart_clk);
 	else if (control_setup.stop_bit_number)
 		@(posedge uart_clk);
 
-	write <= #1 0;
+	write = #1 0;
 	if(debug_mode)
 	   $display ("%m:... Write data %h to UART done cnt : %d ...\n", data,tx_count+1);
         else
diff --git a/verilog/dv/arduino_timer_intr/Makefile b/verilog/dv/arduino_timer_intr/Makefile
new file mode 100644
index 0000000..aa946e0
--- /dev/null
+++ b/verilog/dv/arduino_timer_intr/Makefile
@@ -0,0 +1,144 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+ 
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?=  $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_timer_intr
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/TIMERClass.cpp -o TIMERClass.cpp.o
+
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+	${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+	${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+	${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+	${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+	${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+	${GCC_PREFIX}-ar rcs core.a TIMERClass.cpp.o
+	${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+	${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+	${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+	${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+	${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+	${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+	${GCC_PREFIX}-ar rcs core.a entry.S.o
+	${GCC_PREFIX}-ar rcs core.a hooks.c.o
+	${GCC_PREFIX}-ar rcs core.a init.S.o
+	${GCC_PREFIX}-ar rcs core.a itoa.c.o
+	${GCC_PREFIX}-ar rcs core.a main.cpp.o
+	${GCC_PREFIX}-ar rcs core.a malloc.c.o
+	${GCC_PREFIX}-ar rcs core.a new.cpp.o
+	${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+	${GCC_PREFIX}-ar rcs core.a start.S.o
+	${GCC_PREFIX}-ar rcs core.a wiring.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+	${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+	${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+	${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+	${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+	${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+	${GCC_PREFIX}-objdump -D  ${PATTERN}.ino.elf >   ${PATTERN}.ino.dump
+	rm *.o *.a
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+   endif
+else  
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
+endif
+
+%.vcd: %.vvp
+	vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino b/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino
new file mode 100644
index 0000000..f38f333
--- /dev/null
+++ b/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino
@@ -0,0 +1,81 @@
+
+/*
+
+  Analog input, analog output, serial output
+
+  Reads an analog input pin, maps the result to a range from 0 to 255 and uses
+
+  the result to set the pulse width modulation (PWM) of an output pin.
+
+  Also prints the results to the Serial Monitor.
+
+  The circuit:
+
+  - potentiometer connected to analog pin 0.
+
+    Center pin of the potentiometer goes to the analog pin.
+
+    side pins of the potentiometer go to +5V and ground
+
+  - LED connected from digital pin 9 to ground
+
+  created 29 Dec. 2008
+
+  modified 9 Apr 2012
+
+  by Tom Igoe
+
+  This example code is in the public domain.
+
+  http://www.arduino.cc/en/Tutorial/AnalogInOutSerial
+
+*/
+
+#include"Arduino.h"
+// These constants won't change. They're used to give names to the pins used:
+
+
+int but1=2;  
+int but2=3;  
+
+
+int Timer_us =0;
+int Timer_ms =0;
+void setup() {
+
+  Timer.begin();  
+  Timer.enable(0, TIMER_MICRO_STEP, 10); // 10 Micro Second
+  Timer.enable(1, TIMER_MILLI_STEP, 1); // 1 Milli Second
+  // initialize serial communications at 9600 bps:
+  Serial.begin(9600);
+  attachInterrupt(timerToInterrupt(0),timer_us_intr,RISING);  
+  attachInterrupt(timerToInterrupt(1),timer_ms_intr,RISING);  
+
+}
+
+void loop() {
+
+  delay(1);
+}
+
+
+void timer_us_intr()  
+ {  
+  Timer_us = Timer_us + 1;
+  if(Timer_us > 255) Timer_us = 0;;   
+  
+  Serial.print("Micro Second: ");
+  Serial.println(Timer_us);
+
+
+  }  
+void timer_ms_intr()  
+ {  
+  Timer_ms = Timer_ms + 1;
+  if(Timer_ms > 255) Timer_ms = 0;;   
+  
+  Serial.print("Milli Second: ");
+  Serial.println(Timer_ms);
+
+
+  }   
diff --git a/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino.cpp b/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino.cpp
new file mode 100644
index 0000000..d59053a
--- /dev/null
+++ b/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino.cpp
@@ -0,0 +1,64 @@
+
+/*
+Testing the Timer Interrupt 
+
+*/
+
+#include"Arduino.h"
+// These constants won't change. They're used to give names to the pins used:
+
+
+
+
+int Timer_us =0;
+int Timer_ms =0;
+void setup();
+void loop();
+void timer_us_intr();
+void timer_ms_intr();
+void setup() {
+
+  Timer.begin();  
+  Timer.enable(0, TIMER_MICRO_STEP, 400); // 1000 Micro Second
+  Timer.enable(1, TIMER_MILLI_STEP, 2); // 2 Milli Second
+  // initialize serial communications at 9600 bps:
+  Serial.begin(1152000);
+  attachInterrupt(timerToInterrupt(0),timer_us_intr,RISING);  
+  attachInterrupt(timerToInterrupt(1),timer_ms_intr,RISING);  
+
+}
+
+void loop() {
+
+  delay(1);
+
+}
+
+
+void timer_us_intr()  
+ {  
+  Timer_us = Timer_us + 1;
+  if(Timer_us > 255) Timer_us = 0;;   
+  
+  Serial.print("Timer-0 Step: ");
+  Serial.println(Timer_us);
+  if(Timer_us > 19) {
+    Timer.disable(0);
+  }
+
+
+
+  }  
+void timer_ms_intr()  
+ {  
+  Timer_ms = Timer_ms + 1;
+  if(Timer_ms > 255) Timer_ms = 0;;   
+  
+  Serial.print("Timer-1 Step: ");
+  Serial.println(Timer_ms);
+
+  if(Timer_ms > 4) {
+    Timer.disable(1);
+  }
+
+  }   
diff --git a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
new file mode 100644
index 0000000..5e423d5
--- /dev/null
+++ b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
@@ -0,0 +1,617 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Standalone User validation Test bench                       ////
+////                                                              ////
+////  This file is part of the riscdunio cores project            ////
+////  https://github.com/dineshannayya/riscdunio.git              ////
+////                                                              ////
+////  Description                                                 ////
+////   This is a standalone test bench to validate the            ////
+////   Digital core.                                              ////
+////   This test bench to validate Arduino Interrupt              ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesh.annayya@gmail.com              ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 29th July 2022, Dinesh A                            ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+
+`define TB_HEX "arduino_timer_intr.ino.hex"
+`define TB_TOP arduino_timer_intr_tb
+
+module `TB_TOP;
+	reg clock;
+	reg wb_rst_i;
+	reg power1, power2;
+	reg power3, power4;
+
+        reg        wbd_ext_cyc_i;  // strobe/request
+        reg        wbd_ext_stb_i;  // strobe/request
+        reg [31:0] wbd_ext_adr_i;  // address
+        reg        wbd_ext_we_i;  // write
+        reg [31:0] wbd_ext_dat_i;  // data output
+        reg [3:0]  wbd_ext_sel_i;  // byte enable
+
+        wire [31:0] wbd_ext_dat_o;  // data input
+        wire        wbd_ext_ack_o;  // acknowlegement
+        wire        wbd_ext_err_o;  // error
+
+	// User I/O
+	wire [37:0] io_oeb;
+	wire [37:0] io_out;
+	wire [37:0] io_in;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+	reg         test_fail;
+	reg [31:0] read_data;
+    //----------------------------------
+    // Uart Configuration
+    // ---------------------------------
+    reg [1:0]      uart_data_bit        ;
+    reg	       uart_stop_bits       ; // 0: 1 stop bit; 1: 2 stop bit;
+    reg	       uart_stick_parity    ; // 1: force even parity
+    reg	       uart_parity_en       ; // parity enable
+    reg	       uart_even_odd_parity ; // 0: odd parity; 1: even parity
+    
+    reg [7:0]      uart_data            ;
+    reg [15:0]     uart_divisor         ;	// divided by n * 16
+    reg [15:0]     uart_timeout         ;// wait time limit
+    
+    reg [15:0]     uart_rx_nu           ;
+    reg [15:0]     uart_tx_nu           ;
+    reg [7:0]      uart_write_data [0:39];
+    reg 	       uart_fifo_enable     ;	// fifo mode disable
+	reg            flag                 ;
+    reg            compare_start        ; // User Need to make sure that compare start match with RiscV core completing initial booting
+
+	reg [31:0]     check_sum            ;
+        
+	integer    d_risc_id;
+
+         integer i,j;
+
+
+
+
+	// 50Mhz CLock
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	    flag  = 0;
+        compare_start = 0;
+        wbd_ext_cyc_i ='h0;  // strobe/request
+        wbd_ext_stb_i ='h0;  // strobe/request
+        wbd_ext_adr_i ='h0;  // address
+        wbd_ext_we_i  ='h0;  // write
+        wbd_ext_dat_i ='h0;  // data output
+        wbd_ext_sel_i ='h0;  // byte enable
+	end
+
+	`ifdef WFDUMP
+	   initial begin
+	   	$dumpfile("simx.vcd");
+	   	$dumpvars(3, `TB_TOP);
+	   	$dumpvars(0, `TB_TOP.u_top.u_riscv_top);
+	   	$dumpvars(0, `TB_TOP.u_top.u_pinmux);
+	   	$dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi);
+	   end
+       `endif
+
+
+	wire [15:0] irq_lines = u_top.u_pinmux.u_glbl_reg.irq_lines;
+
+
+/**********************************************************************
+    Arduino Digital PinMapping
+              ATMGA328 Pin No 	Functionality 	      Arduino Pin 	       Carvel Pin Mapping
+              Pin-2 	        PD0/RXD[0] 	                0 	           digital_io[1]
+              Pin-3 	        PD1/TXD[0] 	                1 	           digital_io[2]
+              Pin-4 	        PD2/RXD[1]/INT0 	        2 	           digital_io[3]
+              Pin-5 	        PD3/INT1/OC2B(PWM0)         3 	           digital_io[4] 
+              Pin-6 	        PD4/TXD[1] 	                4 	           digital_io[5] 
+              Pin-11 	        PD5/SS[3]/OC0B(PWM1)/T1 	5 	           digital_io[8]
+              Pin-12 	        PD6/SS[2]/OC0A(PWM2)/AIN0 	6 	           digital_io[9] /analog_io[2]
+              Pin-13 	        PD7/A1N1 	                7 	           digital_io[10]/analog_io[3]
+              Pin-14 	        PB0/CLKO/ICP1 	            8 	           digital_io[11]
+              Pin-15 	        PB1/SS[1]OC1A(PWM3) 	    9 	           digital_io[12]
+              Pin-16 	        PB2/SS[0]/OC1B(PWM4) 	    10 	           digital_io[13]
+              Pin-17 	        PB3/MOSI/OC2A(PWM5) 	    11 	           digital_io[14]
+              Pin-18 	        PB4/MISO 	                12 	           digital_io[15]
+              Pin-19 	        PB5/SCK 	                13 	           digital_io[16] 
+
+              Pin-23 	        ADC0 	                    14 	           digital_io[18] 
+              Pin-24 	        ADC1 	                    15 	           digital_io[19] 
+              Pin-25 	        ADC2 	                    16 	           digital_io[20] 
+              Pin-26 	        ADC3 	                    17 	           digital_io[21] 
+              Pin-27 	        SDA 	                    18 	           digital_io[22] 
+              Pin-28 	        SCL 	                    19 	           digital_io[23] 
+
+              Pin-9             XTAL1                       20             digital_io[6]
+              Pin-10            XTAL2                       21             digital_io[7]
+              Pin-1             RESET                       22             digital_io[0] 
+*****************************************************************************/
+
+// Exclude UART TXD/RXD and RESET
+reg [21:2] arduino_din;
+assign  {  
+           //io_in[0], - Exclude RESET
+           io_in[7],
+           io_in[6],
+           io_in[23],
+           io_in[22],
+           io_in[21],
+           io_in[20],
+           io_in[19],
+           io_in[18],
+           io_in[16],
+           io_in[15],
+           io_in[14],
+           io_in[13],
+           io_in[12],
+           io_in[11],
+           io_in[10],
+           io_in[9],
+           io_in[8],
+           io_in[5],
+           io_in[4],
+           io_in[3]
+           // Uart pins io_in[2], io_in[1] are excluded
+          } = arduino_din;
+
+       /*************************************************************************
+       * This is Baud Rate to clock divider conversion for Test Bench
+       * Note: DUT uses 16x baud clock, where are test bench uses directly
+       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+       * some resolution loss, we expect at lower baud rate this resolution
+       * loss will be less. For Quick simulation perpose higher baud rate used
+       * *************************************************************************/
+       task tb_set_uart_baud;
+       input [31:0] ref_clk;
+       input [31:0] baud_rate;
+       output [31:0] baud_div;
+       reg   [31:0] baud_div;
+       begin
+	  // for 230400 Baud = (50Mhz/230400) = 216.7
+	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+	  // Baud 16x = 216/16 = 13
+          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+	  // Test bench baud clock , 16x of above value
+	  // 13 * 16 = 208,  
+	  // (Note if you see original value was 216, now it's 208 )
+          baud_div = baud_div * 16;
+	  // Test bench half cycle counter to toggle it 
+	  // 208/2 = 104
+           baud_div = baud_div/2;
+	  //As counter run's from 0 , substract from 1
+	   baud_div = baud_div-1;
+       end
+       endtask
+       
+
+    reg[7:0] pinmap[0:22]; //ardiono to gpio pinmaping
+
+	initial begin
+        arduino_din[22:2]  = 23'b010_1010_1010_1010_1010_10; // Initialise based on test case edge
+        pinmap[0]  = 24;
+	    pinmap[1]  = 25;
+	    pinmap[2]  = 26;
+	    pinmap[3]  = 27;
+	    pinmap[4]  = 28;
+	    pinmap[5]  = 29;
+	    pinmap[6]  = 30;
+	    pinmap[7]  = 31;
+	    pinmap[8]  = 8;
+	    pinmap[9]  = 9;
+	    pinmap[10]  = 10;
+	    pinmap[11]  = 11;
+	    pinmap[12]  = 12;
+	    pinmap[13]  = 13;
+	    pinmap[14]  = 16;
+	    pinmap[15]  = 17;
+	    pinmap[16]  = 18;
+	    pinmap[17]  = 19;
+	    pinmap[18]  = 20;
+	    pinmap[19]  = 21;
+	    pinmap[20]  = 14;
+	    pinmap[21]  = 15;
+	    pinmap[22]  = 22;
+
+
+        uart_data_bit           = 2'b11;
+        uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
+        uart_stick_parity       = 0; // 1: force even parity
+        uart_parity_en          = 0; // parity enable
+        uart_even_odd_parity    = 1; // 0: odd parity; 1: even parity
+	    tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+        uart_timeout            = 2000;// wait time limit
+        uart_fifo_enable        = 0;	// fifo mode disable
+
+		$value$plusargs("risc_core_id=%d", d_risc_id);
+
+		#200; // Wait for reset removal
+	    repeat (10) @(posedge clock);
+		$display("Monitor: Standalone User Risc Boot Test Started");
+
+		// Remove Wb Reset
+		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+	    repeat (2) @(posedge clock);
+		#1;
+        // Remove all the reset
+        if(d_risc_id == 0) begin
+             $display("STATUS: Working with Risc core 0");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+        end else if(d_risc_id == 1) begin
+             $display("STATUS: Working with Risc core 1");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+        end else if(d_risc_id == 2) begin
+             $display("STATUS: Working with Risc core 2");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+        end else if(d_risc_id == 3) begin
+             $display("STATUS: Working with Risc core 3");
+             wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+        end
+
+        repeat (100) @(posedge clock);  // wait for Processor Get Ready
+
+	    tb_uart.debug_mode = 0; // disable debug display
+        tb_uart.uart_init;
+        tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
+                                       uart_stick_parity, uart_timeout, uart_divisor);
+
+        repeat (55000) @(posedge clock);  // wait for Processor Get Ready
+	    flag  = 0;
+		check_sum = 0;
+        compare_start = 1;
+        
+        fork
+
+           begin
+              while(flag == 0)
+              begin
+                 tb_uart.read_char(read_data,flag);
+		         if(flag == 0)  begin
+		            $write ("%c",read_data);
+		            check_sum = check_sum+read_data;
+		         end
+              end
+           end
+           begin
+              repeat (500000) @(posedge clock);  // wait for Processor Get Ready
+           end
+           join_any
+        
+           #1000
+           tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+        
+           test_fail = 0;
+
+		   $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
+           // Check 
+           // if all the 102 byte received
+           // if no error 
+           if(uart_rx_nu != 436) test_fail = 1;
+           if(check_sum != 32'h78cd) test_fail = 1;
+           if(tb_uart.err_cnt != 0) test_fail = 1;
+
+	   
+	    	$display("###################################################");
+          	if(test_fail == 0) begin
+		   `ifdef GL
+	    	       $display("Monitor: Standalone String (GL) Passed");
+		   `else
+		       $display("Monitor: Standalone String (RTL) Passed");
+		   `endif
+	        end else begin
+		    `ifdef GL
+	    	        $display("Monitor: Standalone String (GL) Failed");
+		    `else
+		        $display("Monitor: Standalone String (RTL) Failed");
+		    `endif
+		 end
+	    	$display("###################################################");
+	    $finish;
+	end
+
+	initial begin
+		wb_rst_i <= 1'b1;
+		#100;
+		wb_rst_i <= 1'b0;	    	// Release reset
+	end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+    .vccd1(USER_VDD1V8),	// User area 1 1.8V supply
+    .vssd1(VSS),	// User area 1 digital ground
+`endif
+    .wb_clk_i        (clock),  // System clock
+    .user_clock2     (1'b1),  // Real-time clock
+    .wb_rst_i        (wb_rst_i),  // Regular Reset signal
+
+    .wbs_cyc_i   (wbd_ext_cyc_i),  // strobe/request
+    .wbs_stb_i   (wbd_ext_stb_i),  // strobe/request
+    .wbs_adr_i   (wbd_ext_adr_i),  // address
+    .wbs_we_i    (wbd_ext_we_i),  // write
+    .wbs_dat_i   (wbd_ext_dat_i),  // data output
+    .wbs_sel_i   (wbd_ext_sel_i),  // byte enable
+
+    .wbs_dat_o   (wbd_ext_dat_o),  // data input
+    .wbs_ack_o   (wbd_ext_ack_o),  // acknowlegement
+
+ 
+    // Logic Analyzer Signals
+    .la_data_in      ('1) ,
+    .la_data_out     (),
+    .la_oenb         ('0),
+ 
+
+    // IOs
+    .io_in          (io_in)  ,
+    .io_out         (io_out) ,
+    .io_oeb         (io_oeb) ,
+
+    .user_irq       () 
+
+);
+// SSPI Slave I/F
+assign io_in[0]  = 1'b1; // RESET
+//assign io_in[16] = 1'b0 ; // SPIS SCK 
+
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+
+    end
+`endif    
+
+//------------------------------------------------------
+//  Integrate the Serial flash with qurd support to
+//  user core using the gpio pads
+//  ----------------------------------------------------
+
+   wire flash_clk = io_out[24];
+   wire flash_csb = io_out[25];
+   // Creating Pad Delay
+   wire #1 io_oeb_29 = io_oeb[29];
+   wire #1 io_oeb_30 = io_oeb[30];
+   wire #1 io_oeb_31 = io_oeb[31];
+   wire #1 io_oeb_32 = io_oeb[32];
+   tri  #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
+   tri  #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
+   tri  #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
+   tri  #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+
+   assign io_in[29] = flash_io0;
+   assign io_in[30] = flash_io1;
+   assign io_in[31] = flash_io2;
+   assign io_in[32] = flash_io3;
+
+   // Quard flash
+     s25fl256s #(.mem_file_name(`TB_HEX),
+	             .otp_file_name("none"),
+                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
+		 u_spi_flash_256mb (
+           // Data Inputs/Outputs
+       .SI      (flash_io0),
+       .SO      (flash_io1),
+       // Controls
+       .SCK     (flash_clk),
+       .CSNeg   (flash_csb),
+       .WPNeg   (flash_io2),
+       .HOLDNeg (flash_io3),
+       .RSTNeg  (!wb_rst_i)
+
+       );
+
+
+//---------------------------
+//  UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd   = io_out[2];
+assign io_in[1]  = uart_rxd ;
+ 
+uart_agent tb_uart(
+	.mclk                (clock              ),
+	.txd                 (uart_rxd           ),
+	.rxd                 (uart_txd           )
+	);
+
+
+//----------------------------
+// All the task are defined here
+//----------------------------
+
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h1;  // write
+  wbd_ext_dat_i =data;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  if(data !== cmp_data) begin
+     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+     test_fail = 1;
+  end else begin
+     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  end
+  repeat (2) @(posedge clock);
+end
+endtask
+
+`ifdef GL
+
+wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;
+
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE  user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+    if(`RISC_CORE.wbd_imem_ack_i)
+          $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+    if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+    if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv
index 02ecb2a..22dce38 100755
--- a/verilog/rtl/pinmux/src/pinmux_top.sv
+++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -60,7 +60,7 @@
                        output logic	        wbd_clk_pinmux,
                        // System Signals
                        // Inputs
-		       input logic             mclk,
+		               input logic             mclk,
                        input logic             h_reset_n,
 
                        // Global Reset control
@@ -72,7 +72,7 @@
                        output logic            i2cm_rst_n       ,
                        output logic            usb_rst_n        ,
 
-		       output logic [15:0]     cfg_riscv_ctrl,
+		               output logic [15:0]     cfg_riscv_ctrl,
 
 		       // Reg Bus Interface Signal
                        input logic             reg_cs,
@@ -89,8 +89,8 @@
                        output logic [31:0]     irq_lines,
                        output logic            soft_irq,
                        output logic [2:0]      user_irq,
-		       input  logic            usb_intr,
-		       input  logic            i2cm_intr,
+		               input  logic            usb_intr,
+		               input  logic            i2cm_intr,
 
                        // Digital IO
                        output logic [37:0]     digital_io_out,
@@ -98,11 +98,11 @@
                        input  logic [37:0]     digital_io_in,
 
 		       // SFLASH I/F
-		       input  logic            sflash_sck,
-		       input  logic [3:0]      sflash_ss,
-		       input  logic [3:0]      sflash_oen,
-		       input  logic [3:0]      sflash_do,
-		       output logic [3:0]      sflash_di,
+		               input  logic            sflash_sck,
+		               input  logic [3:0]      sflash_ss,
+		               input  logic [3:0]      sflash_oen,
+		               input  logic [3:0]      sflash_do,
+		               output logic [3:0]      sflash_di,
 
 		       // SSRAM I/F - Temp Masked
 		       //input  logic            ssram_sck,
diff --git a/verilog/rtl/pinmux/src/timer_top.sv b/verilog/rtl/pinmux/src/timer_top.sv
index ae981dc..127d62f 100644
--- a/verilog/rtl/pinmux/src/timer_top.sv
+++ b/verilog/rtl/pinmux/src/timer_top.sv
@@ -132,7 +132,7 @@
 
 timer  u_timer_0
   (
-     .reset_n                      (sreset_n             ),// system syn reset
+     .reset_n                      (h_reset_n            ),// system syn reset
      .mclk                         (mclk                 ),// master clock
      .pulse_1us                    (pulse_1us            ),
      .pulse_1ms                    (pulse_1ms            ),
@@ -152,7 +152,7 @@
 wire [15:0] cfg_timer1_compare = cfg_timer1[15:0];
 timer  u_timer_1
   (
-     .reset_n                      (sreset_n             ),// system syn reset
+     .reset_n                      (h_reset_n            ),// system syn reset
      .mclk                         (mclk                 ),// master clock
      .pulse_1us                    (pulse_1us            ),
      .pulse_1ms                    (pulse_1ms            ),
@@ -173,7 +173,7 @@
 
 timer  u_timer_2
   (
-     .reset_n                      (sreset_n             ),// system syn reset
+     .reset_n                      (h_reset_n            ),// system syn reset
      .mclk                         (mclk                 ),// master clock
      .pulse_1us                    (pulse_1us            ),
      .pulse_1ms                    (pulse_1ms            ),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index d3c9ec7..e54e37a 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -239,6 +239,7 @@
 ////          A. GPIO interrupt generation changed from 1 to 32   ////
 ////          B. Total interrupt to Riscv changed from 16 to 32   ////
 ////          C. uart_master disable option added at pinmux       ////
+////          D. Timer interrupt related clean-up                 ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////